/*
** Halts any currently active transactions
*/
static void PeripheralsHalt(void)
{
RasterIdleModeConfig(LCDC_BASE_ADDR, LCDC_SYSCONFIG_IDLEMODE_FORCE <<
LCDC_SYSCONFIG_STANDBYMODE_SHIFT);
RasterStandbyModeConfig(LCDC_BASE_ADDR,
LCDC_SYSCONFIG_STANDBYMODE_FORCE <<
LCDC_SYSCONFIG_IDLEMODE_SHIFT);
delay(30);
/* Disable EDMA for the transfer */
EDMA3DisableTransfer(EDMA_BASE_ADDR, EDMA3_CHA_MCASP1_TX,
EDMA3_TRIG_MODE_EVENT);
McASPTxReset(MCASP_CTRL_BASE_ADDR);
/* LCD back light OFF */
EcapBkLightDisable();
/* Disable End-of-frame interrupt */
Raster0EOFIntDisable();
CPSWCPDMACmdIdleEnable(CPSW_CPDMA_BASE_ADDR);
/* configure Modules mode to idle mode */
ConfigIdleMode();
TouchScreenFIFOFlush();
if(wakeSource != WAKE_SOURCE_TSC)
{
/* Config ADC in powerdown mode */
TSCADCSetADCPowerDown(ADC_TSC_BASE_ADDR);
TouchDisable();
}
/* Disable GFX power domain */
HWREG(SOC_PRM_GFX_REGS + PRM_GFX_PM_GFX_PWRSTCTRL) = 0x0;
/* Disable GFX module */
HWREG(SOC_CM_GFX_REGS + CM_GFX_L3_CLKSTCTRL) = 0x0;
HWREG(SOC_CM_GFX_REGS + CM_GFX_BITBLT_CLKCTRL) = 0x0;
HWREG(SOC_CM_GFX_REGS + CM_GFX_MMUCFG_CLKCTRL) = 0x0;
HWREG(SOC_CM_GFX_REGS + CM_GFX_MMUDATA_CLKCTRL) = 0x0;
/* Set GFX modules to SW_SLEEP */
HWREG(SOC_CM_GFX_REGS + CM_GFX_L4LS_GFX_CLKSTCTRL) = 0x1;
HWREG(SOC_CM_GFX_REGS + PRM_GFX_PM_GFX_PWRSTCTRL) = 0x1;
/* disable Cust_efuse PD */
HWREG(SOC_PRM_CEFUSE_REGS + PRM_CEFUSE_PM_CEFUSE_PWRSTCTRL) = 0x0;
/* disable cust_efuse module */
HWREG(SOC_CM_CEFUSE_REGS + CM_CEFUSE_CEFUSE_CLKCTRL) = 0x0;
/* Set CUST_EFUSE modules to SW_SLEEP */
HWREG(SOC_CM_CEFUSE_REGS + CM_CEFUSE_CLKSTCTRL) = 0x1;
}
/*
** Configures the McASP Transmit Section for 2 channels in I2S mode.
*/
static void McASPI2STwoChanConfig(void)
{
McASPTxReset(MCASP_INST_BASE);
/* Enable the FIFOs for DMA transfer */
McASPWriteFifoEnable(MCASP_FIFO_REGS, 1, 1);
/* Set I2S format in the transmitter/receiver format units */
McASPTxFmtI2SSet(MCASP_INST_BASE, TONE_WORD_SIZE, TONE_SLOT_SIZE,
MCASP_TX_MODE_DMA);
McASPTxFrameSyncCfg(MCASP_INST_BASE, 2, MCASP_TX_FS_WIDTH_WORD,
MCASP_TX_FS_EXT_BEGIN_ON_RIS_EDGE);
/* configure the clock for transmitter */
McASPTxClkCfg(MCASP_INST_BASE, MCASP_TX_CLK_EXTERNAL, 0, 0);
McASPTxClkPolaritySet(MCASP_INST_BASE, MCASP_TX_CLK_POL_FALL_EDGE);
McASPTxClkCheckConfig(MCASP_INST_BASE, MCASP_TX_CLKCHCK_DIV32,
0x00, 0xFF);
/* Enable the transmitter/receiver slots. I2S uses 2 slots */
McASPTxTimeSlotSet(MCASP_INST_BASE, I2S_SLOTS_L_R);
/* Set the serializer as transmitter */
McASPSerializerTxSet(MCASP_INST_BASE, MCASP_XSER_TX);
/*
** Configure the McASP pins
** Input - Frame Sync, Clock and Serializer 12
** Output - Serializer 11 is connected to the input of the codec
*/
McASPPinMcASPSet(MCASP_INST_BASE, 0xFFFFFFFF);
McASPPinDirOutputSet(MCASP_INST_BASE, MCASP_PIN_AXR(MCASP_XSER_TX));
McASPPinDirInputSet(MCASP_INST_BASE, MCASP_PIN_AFSX
| MCASP_PIN_ACLKX);
}
/*
** Configures the McASP Transmit Section in I2S mode.
*/
static void McASPI2SConfigure(void)
{
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
McASPTxReset(SOC_MCASP_0_CTRL_REGS);
/* Enable the FIFOs for DMA transfer */
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
/* Set I2S format in the transmitter/receiver format units */
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_RX_MODE_DMA);
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_TX_MODE_DMA);
/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
MCASP_RX_FS_EXT_BEGIN_ON_RIS_EDGE);
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
MCASP_TX_FS_EXT_BEGIN_ON_RIS_EDGE);
/* configure the clock for receiver */
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0x00, 0xFF);
/* configure the clock for transmitter */
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL, 0, 0);
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0x00, 0xFF);
/* Enable synchronization of RX and TX sections */
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);
/* Enable the transmitter/receiver slots. I2S uses 2 slots */
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
/*
** Set the serializers, Currently only one serializer is set as
** transmitter and one serializer as receiver.
*/
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);
/*
** Configure the McASP pins
** Input - Frame Sync, Clock and Serializer Rx
** Output - Serializer Tx is connected to the input of the codec
*/
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AXR(MCASP_XSER_TX));
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
| MCASP_PIN_ACLKX
| MCASP_PIN_AFSR
| MCASP_PIN_ACLKR
| MCASP_PIN_AXR(MCASP_XSER_RX));
/* Enable error interrupts for McASP */
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
| MCASP_TX_CLKFAIL
| MCASP_TX_SYNCERROR
| MCASP_TX_UNDERRUN);
McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
| MCASP_RX_CLKFAIL
| MCASP_RX_SYNCERROR
| MCASP_RX_OVERRUN);
}
