_ramfunc uint32_t CGU_Init(void) { __disable_irq(); MemoryPinInit(); // Make sure EMC is in high-speed pin mode /* Set the XTAL oscillator frequency to 12MHz*/ CGU_SetXTALOSC(12000000); CGU_EnableEntity(CGU_CLKSRC_XTAL_OSC, ENABLE); CGU_EntityConnect(CGU_CLKSRC_XTAL_OSC, CGU_BASE_SPIFI); CGU_EntityConnect(CGU_CLKSRC_XTAL_OSC, CGU_BASE_M3); /* Set PL160M 12*1 = 12 MHz */ CGU_EntityConnect(CGU_CLKSRC_XTAL_OSC, CGU_CLKSRC_PLL1); CGU_SetPLL1(1); CGU_EnableEntity(CGU_CLKSRC_PLL1, ENABLE); /* Run SPIFI from PL160M, /2 */ CGU_EntityConnect(CGU_CLKSRC_PLL1, CGU_CLKSRC_IDIVA); CGU_EnableEntity(CGU_CLKSRC_IDIVA, ENABLE); CGU_SetDIV(CGU_CLKSRC_IDIVA, 2); // This gets adjusted in spi_flash.c to slow the clock when writing CGU_EntityConnect(CGU_CLKSRC_IDIVA, CGU_BASE_SPIFI); CGU_UpdateClock(); LPC_CCU1->CLK_M3_EMCDIV_CFG |= (1<<0) | (1<<5); // Turn on clock / 2 LPC_CREG->CREG6 |= (1<<16); // EMC divided by 2 LPC_CCU1->CLK_M3_EMC_CFG |= (1<<0); // Turn on clock /* Set PL160M @ 12*9=108 MHz */ CGU_SetPLL1(9); /* Run base M3 clock from PL160M, no division */ CGU_EntityConnect(CGU_CLKSRC_PLL1, CGU_BASE_M3); emc_WaitMS(30); /* Change the clock to 180 MHz */ /* Set PL160M @ 12*15=180 MHz */ CGU_SetPLL1(15); emc_WaitMS(30); CGU_UpdateClock(); emc_WaitMS(10); __enable_irq(); return 0; }
int main(void) { SystemInit(); CGU_Init(); // Configure external flash MemoryPinInit(); EMCSRDRAMInit(); EMCFlashInit(); // Init SysTick to 1ms SysTick_Config(CGU_GetPCLKFrequency(CGU_PERIPHERAL_M4CORE) / 1000); // Copy image to SDRAM memcpy((void *)SDRAM_BASE_ADDR, (void *)IMAGE_FLASH_ADDR, 2UL*1024*768); // Initialize TFP410 TFP410_Init((void *)SDRAM_BASE_ADDR); while (1) { } }
void vEMC_InitSRDRAM(uint32_t u32BaseAddr, uint32_t u32Width, uint32_t u32Size, uint32_t u32DataBus, uint32_t u32ColAddrBits) { // adjust the CCU delaye for EMI (default to zero) //LPC_SCU->EMCCLKDELAY = (CLK0_DELAY | (CLKE0_DELAY << 16)); // Move all clock delays together LPC_SCU->EMCDELAYCLK = ((CLK0_DELAY) | (CLK0_DELAY << 4) | (CLK0_DELAY << 8) | (CLK0_DELAY << 12)); /* Initialize EMC to interface with SDRAM */ LPC_EMC->CONTROL = 0x00000001; /* Enable the external memory controller */ LPC_EMC->CONFIG = 0; LPC_EMC->DYNAMICCONFIG0 = ((u32Width << 7) | (u32Size << 9) | (1UL << 12) | (u32DataBus << 14)); LPC_EMC->DYNAMICCONFIG2 = ((u32Width << 7) | (u32Size << 9) | (1UL << 12) | (u32DataBus << 14)); LPC_EMC->DYNAMICRASCAS0 = (3 << 0) | (3 << 8); // aem LPC_EMC->DYNAMICRASCAS2 = (3 << 0) | (3 << 8); // aem LPC_EMC->DYNAMICREADCONFIG = EMC_COMMAND_DELAYED_STRATEGY; LPC_EMC->DYNAMICRP = 1; // calculated from xls sheet LPC_EMC->DYNAMICRAS = 3; LPC_EMC->DYNAMICSREX = 5; LPC_EMC->DYNAMICAPR = 0; LPC_EMC->DYNAMICDAL = 4; LPC_EMC->DYNAMICWR = 1; LPC_EMC->DYNAMICRC = 5; LPC_EMC->DYNAMICRFC = 5; LPC_EMC->DYNAMICXSR = 5; LPC_EMC->DYNAMICRRD = 1; LPC_EMC->DYNAMICMRD = 1; LPC_EMC->DYNAMICCONTROL = EMC_CE_ENABLE | EMC_CS_ENABLE | EMC_INIT(EMC_NOP); emc_WaitUS(100); LPC_EMC->DYNAMICCONTROL = EMC_CE_ENABLE | EMC_CS_ENABLE | EMC_INIT(EMC_PRECHARGE_ALL); LPC_EMC->DYNAMICREFRESH = 2; emc_WaitUS(100); LPC_EMC->DYNAMICREFRESH = 50; LPC_EMC->DYNAMICCONTROL = EMC_CE_ENABLE | EMC_CS_ENABLE | EMC_INIT(EMC_MODE); if(u32DataBus == 0) { /* burst size 8 */ *((volatile uint32_t *)(u32BaseAddr | ((3 | (3 << 4)) << (u32ColAddrBits + 1)))); } else { /* burst size 4 */ *((volatile uint32_t *)(u32BaseAddr | ((2UL | (2UL << 4)) << (u32ColAddrBits + 2)))); } LPC_EMC->DYNAMICCONTROL = 0; // EMC_CE_ENABLE | EMC_CS_ENABLE; LPC_EMC->DYNAMICCONFIG0 = ((u32Width << 7) | (u32Size << 9) | (1UL << 12) | (u32DataBus << 14)) | EMC_B_ENABLE; LPC_EMC->DYNAMICCONFIG1 = ((u32Width << 7) | (u32Size << 9) | (1UL << 12) | (u32DataBus << 14)) | EMC_B_ENABLE; LPC_EMC->DYNAMICCONFIG2 = ((u32Width << 7) | (u32Size << 9) | (1UL << 12) | (u32DataBus << 14)) | EMC_B_ENABLE; LPC_EMC->DYNAMICCONFIG3 = ((u32Width << 7) | (u32Size << 9) | (1UL << 12) | (u32DataBus << 14)) | EMC_B_ENABLE; MemoryPinInit(); }