/**
* @brief This routine write the spare area information for the specified
* pages addresses.
* @param pBuffer: pointer on the Buffer containing data to be written
* @param Address: First page address
* @param NumSpareAreaTowrite: Number of Spare Area to write
* @retval New status of the NAND operation. This parameter can be:
* - NAND_TIMEOUT_ERROR: when the previous operation generate
* a Timeout error
* - NAND_READY: when memory is ready for the next operation
* And the new status of the increment address operation. It can be:
* - NAND_VALID_ADDRESS: When the new address is valid address
* - NAND_INVALID_ADDRESS: When the new address is invalid address
*/
uint32_t NAND_WriteSpareArea(uint8_t * pBuffer, NAND_ADDRESS Address,
uint32_t NumSpareAreaTowrite)
{
uint32_t index = 0x00, numsparesreawritten = 0x00, addressstatus =
NAND_VALID_ADDRESS;
uint32_t status = NAND_READY, size = 0x00;
while ((NumSpareAreaTowrite != 0x00)
&& (addressstatus == NAND_VALID_ADDRESS)
&& (status == NAND_READY)) {
/*!< Page write Spare area command and address */
*(__IO uint8_t *) (Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_AREA_C;
*(__IO uint8_t *) (Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_WRITE0;
*(__IO uint8_t *) (Bank_NAND_ADDR | ADDR_AREA) = 0x00;
*(__IO uint8_t *) (Bank_NAND_ADDR | ADDR_AREA) =
ADDR_1st_CYCLE(ROW_ADDRESS);
*(__IO uint8_t *) (Bank_NAND_ADDR | ADDR_AREA) =
ADDR_2nd_CYCLE(ROW_ADDRESS);
*(__IO uint8_t *) (Bank_NAND_ADDR | ADDR_AREA) =
ADDR_3rd_CYCLE(ROW_ADDRESS);
/*!< Calculate the size */
size =
NAND_SPARE_AREA_SIZE +
(NAND_SPARE_AREA_SIZE * numsparesreawritten);
/*!< Write the data */
for (; index < size; index++) {
*(__IO uint8_t *) (Bank_NAND_ADDR | DATA_AREA) =
pBuffer[index];
}
*(__IO uint8_t *) (Bank_NAND_ADDR | CMD_AREA) =
NAND_CMD_WRITE_TRUE1;
/*!< Check status for successful operation */
status = NAND_GetStatus();
if (status == NAND_READY) {
numsparesreawritten++;
NumSpareAreaTowrite--;
/*!< Calculate Next page Address */
addressstatus = NAND_AddressIncrement(&Address);
}
}
return (status | addressstatus);
}
/**
* @brief This routine is for writing one or several 512 Bytes Page size.
* @param pBuffer: pointer on the Buffer containing data to be written
* @param Address: First page address
* @param NumPageToWrite: Number of page to write
* @retval New status of the NAND operation. This parameter can be:
* - NAND_TIMEOUT_ERROR: when the previous operation generate
* a Timeout error
* - NAND_READY: when memory is ready for the next operation
* And the new status of the increment address operation. It can be:
* - NAND_VALID_ADDRESS: When the new address is valid address
* - NAND_INVALID_ADDRESS: When the new address is invalid address
*/
uint32_t NAND_WriteSmallPage(uint8_t *pBuffer, NAND_ADDRESS Address, uint32_t NumPageToWrite)
{
uint32_t index = 0x00, numpagewritten = 0x00, addressstatus = NAND_VALID_ADDRESS;
uint32_t status = NAND_READY, size = 0x00;
while((NumPageToWrite != 0x00) && (addressstatus == NAND_VALID_ADDRESS) && (status == NAND_READY))
{
/*!< Page write command and address */
//*(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_AREA_A;
*(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_WRITE0;
*(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = 0x00;
*(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = 0x00;
*(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_1st_CYCLE(ROW_ADDRESS);
*(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_2nd_CYCLE(ROW_ADDRESS);
/*!< Calculate the size */
size = NAND_PAGE_SIZE + (NAND_PAGE_SIZE * numpagewritten);
/* 读忙脚, 等待直到空闲 */
while(NAND_FLASH_BUZY);
/*!< Write data */
for(; index < size; index++)
{
*(__IO uint8_t *)(Bank_NAND_ADDR | DATA_AREA) = pBuffer[index];
}
*(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_WRITE_TRUE1;
/*!< Check status for successful operation */
status = NAND_GetStatus();
if(status == NAND_READY)
{
numpagewritten++;
NumPageToWrite--;
/*!< Calculate Next small page Address */
addressstatus = NAND_AddressIncrement(&Address);
}
}
return (status | addressstatus);
}
/**
* @brief This routine read the spare area information from the specified
* pages addresses.
* @param pBuffer: pointer on the Buffer to fill
* @param Address: First page address
* @param NumSpareAreaToRead: Number of Spare Area to read
* @retval New status of the NAND operation. This parameter can be:
* - NAND_TIMEOUT_ERROR: when the previous operation generate
* a Timeout error
* - NAND_READY: when memory is ready for the next operation
* And the new status of the increment address operation. It can be:
* - NAND_VALID_ADDRESS: When the new address is valid address
* - NAND_INVALID_ADDRESS: When the new address is invalid address
*/
uint32_t NAND_ReadSpareArea(uint8_t * pBuffer, NAND_ADDRESS Address,
uint32_t NumSpareAreaToRead)
{
uint32_t numsparearearead = 0x00, index = 0x00, addressstatus =
NAND_VALID_ADDRESS;
uint32_t status = NAND_READY, size = 0x00;
while ((NumSpareAreaToRead != 0x0)
&& (addressstatus == NAND_VALID_ADDRESS)) {
/*!< Page Read command and page address */
*(__IO uint8_t *) (Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_AREA_C;
*(__IO uint8_t *) (Bank_NAND_ADDR | ADDR_AREA) = 0x00;
*(__IO uint8_t *) (Bank_NAND_ADDR | ADDR_AREA) =
ADDR_1st_CYCLE(ROW_ADDRESS);
*(__IO uint8_t *) (Bank_NAND_ADDR | ADDR_AREA) =
ADDR_2nd_CYCLE(ROW_ADDRESS);
*(__IO uint8_t *) (Bank_NAND_ADDR | ADDR_AREA) =
ADDR_3rd_CYCLE(ROW_ADDRESS);
/*!< Data Read */
size =
NAND_SPARE_AREA_SIZE +
(NAND_SPARE_AREA_SIZE * numsparearearead);
/*!< Get Data into Buffer */
for (; index < size; index++) {
pBuffer[index] =
*(__IO uint8_t *) (Bank_NAND_ADDR | DATA_AREA);
}
numsparearearead++;
NumSpareAreaToRead--;
/*!< Calculate page address */
addressstatus = NAND_AddressIncrement(&Address);
}
status = NAND_GetStatus();
return (status | addressstatus);
}
/**
* @brief This routine is for sequential read from one or several 512 Bytes Page size.
* @param pBuffer: pointer on the Buffer to fill
* @param Address: First page address
* @param NumPageToRead: Number of page to read
* @retval New status of the NAND operation. This parameter can be:
* - NAND_TIMEOUT_ERROR: when the previous operation generate
* a Timeout error
* - NAND_READY: when memory is ready for the next operation
* And the new status of the increment address operation. It can be:
* - NAND_VALID_ADDRESS: When the new address is valid address
* - NAND_INVALID_ADDRESS: When the new address is invalid address
*/
uint32_t NAND_ReadSmallPage(uint8_t *pBuffer, NAND_ADDRESS Address, uint32_t NumPageToRead)
{
uint32_t index = 0x00, numpageread = 0x00, addressstatus = NAND_VALID_ADDRESS;
uint32_t status = NAND_READY, size = 0x00;
while((NumPageToRead != 0x0) && (addressstatus == NAND_VALID_ADDRESS))
{
/*!< Page Read command and page address */
*(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_AREA_A;
*(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = 0x00;
*(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = 0x00;
*(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_1st_CYCLE(ROW_ADDRESS);
*(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_2nd_CYCLE(ROW_ADDRESS);
*(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_AREA_TRUE1;
/*!< Calculate the size */
size = NAND_PAGE_SIZE + (NAND_PAGE_SIZE * numpageread);
/* 读忙脚, 等待直到空闲 */
while(NAND_FLASH_BUZY);
/*!< Get Data into Buffer */
for(; index < size; index++)
{
pBuffer[index]= *(__IO uint8_t *)(Bank_NAND_ADDR | DATA_AREA);
}
numpageread++;
NumPageToRead--;
/*!< Calculate page address */
addressstatus = NAND_AddressIncrement(&Address);
}
status = NAND_GetStatus();
return (status | addressstatus);
}
/**
* @brief Write Spare area(s) to NAND memory.
* @param hnand: pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
* @param pAddress: pointer to NAND address structure
* @param pBuffer: pointer to source buffer to write
* @param NumSpareAreaTowrite: number of spare areas to write to block
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite)
{
__IO uint32_t index = 0;
uint32_t tickstart = 0;
uint32_t deviceaddress = 0, size = 0, num_spare_area_written = 0, addressstatus = NAND_VALID_ADDRESS;
NAND_AddressTypeDef nandaddress;
uint32_t addressoffset = 0;
/* Process Locked */
__HAL_LOCK(hnand);
/* Check the NAND controller state */
if(hnand->State == HAL_NAND_STATE_BUSY)
{
return HAL_BUSY;
}
/* Identify the device address */
deviceaddress = NAND_DEVICE;
/* Update the FMC_NAND controller state */
hnand->State = HAL_NAND_STATE_BUSY;
/* Save the content of pAddress as it will be modified */
nandaddress.Block = pAddress->Block;
nandaddress.Page = pAddress->Page;
nandaddress.Zone = pAddress->Zone;
/* Spare area(s) write loop */
while((NumSpareAreaTowrite != 0) && (addressstatus == NAND_VALID_ADDRESS))
{
/* update the buffer size */
size = (hnand->Info.SpareAreaSize) + ((hnand->Info.SpareAreaSize) * num_spare_area_written);
/* Get the address offset */
addressoffset = ARRAY_ADDRESS(&nandaddress, hnand);
/* Send write Spare area command sequence */
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(addressoffset);
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(addressoffset);
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(addressoffset);
/* for 512 and 1 GB devices, 4th cycle is required */
if(hnand->Info.BlockNbr >= 1024)
{
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(addressoffset);
}
/* Write data to memory */
for(; index < size; index++)
{
*(__IO uint8_t *)deviceaddress = *(uint8_t *)pBuffer++;
}
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
/* Get tick */
tickstart = HAL_GetTick();
/* Read status until NAND is ready */
while(HAL_NAND_Read_Status(hnand) != NAND_READY)
{
if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
{
return HAL_TIMEOUT;
}
}
/* Increment written spare areas number */
num_spare_area_written++;
/* Decrement spare areas to write */
NumSpareAreaTowrite--;
/* Increment the NAND address */
addressstatus = NAND_AddressIncrement(hnand, &nandaddress);
}
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hnand);
return HAL_OK;
}
/**
* @brief Read Page(s) from NAND memory block.
* @param hnand: pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
* @param pAddress: pointer to NAND address structure
* @param pBuffer: pointer to destination read buffer
* @param NumPageToRead: number of pages to read from block
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead)
{
__IO uint32_t index = 0;
uint32_t deviceaddress = 0, size = 0, numpagesread = 0, addressstatus = NAND_VALID_ADDRESS;
NAND_AddressTypeDef nandaddress;
uint32_t addressoffset = 0;
/* Process Locked */
__HAL_LOCK(hnand);
/* Check the NAND controller state */
if(hnand->State == HAL_NAND_STATE_BUSY)
{
return HAL_BUSY;
}
/* Identify the device address */
deviceaddress = NAND_DEVICE;
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_BUSY;
/* Save the content of pAddress as it will be modified */
nandaddress.Block = pAddress->Block;
nandaddress.Page = pAddress->Page;
nandaddress.Zone = pAddress->Zone;
/* Page(s) read loop */
while((NumPageToRead != 0) && (addressstatus == NAND_VALID_ADDRESS))
{
/* update the buffer size */
size = hnand->Info.PageSize + ((hnand->Info.PageSize) * numpagesread);
/* Get the address offset */
addressoffset = ARRAY_ADDRESS(&nandaddress, hnand);
/* Send read page command sequence */
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(addressoffset);
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(addressoffset);
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(addressoffset);
/* for 512 and 1 GB devices, 4th cycle is required */
if(hnand->Info.BlockNbr >= 1024)
{
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(addressoffset);
}
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
/* Get Data into Buffer */
for(; index < size; index++)
{
*(uint8_t *)pBuffer++ = *(uint8_t *)deviceaddress;
}
/* Increment read pages number */
numpagesread++;
/* Decrement pages to read */
NumPageToRead--;
/* Increment the NAND address */
addressstatus = NAND_AddressIncrement(hnand, &nandaddress);
}
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hnand);
return HAL_OK;
}
