void
nextdma_attach(struct device *parent, struct device *self, void *aux)
{
struct nextdma_softc *nsc = (struct nextdma_softc *)self;
struct intio_attach_args *ia = (struct intio_attach_args *)aux;
if (attached >= nnextdma_channels)
return;
nsc->sc_chan = &nextdma_channel[attached];
nsc->sc_dmat = ia->ia_dmat;
nsc->sc_bst = ia->ia_bst;
if (bus_space_map(nsc->sc_bst, nsc->sc_chan->nd_base,
nsc->sc_chan->nd_size, 0, &nsc->sc_bsh)) {
panic("%s: can't map DMA registers for channel %s",
nsc->sc_dev.dv_xname, nsc->sc_chan->nd_name);
}
nextdma_init (nsc);
isrlink_autovec(nsc->sc_chan->nd_intrfunc, nsc,
NEXT_I_IPL(nsc->sc_chan->nd_intr), 10, NULL);
INTR_ENABLE(nsc->sc_chan->nd_intr);
printf (": channel %d (%s)\n", attached,
nsc->sc_chan->nd_name);
attached++;
return;
}
void
nextdisplay_attach(device_t parent, device_t self, void *aux)
{
struct nextdisplay_softc *sc = device_private(self);
struct wsemuldisplaydev_attach_args waa;
int isconsole;
int iscolor;
paddr_t addr;
if (rom_machine_type == NeXT_WARP9C ||
rom_machine_type == NeXT_TURBO_COLOR) {
iscolor = 1;
addr = colorbase;
} else {
iscolor = 0;
addr = monobase;
}
isconsole = nextdisplay_is_console(addr);
if (isconsole) {
sc->sc_dc = &nextdisplay_console_dc;
sc->nscreens = 1;
} else {
sc->sc_dc = (struct nextdisplay_config *)
malloc(sizeof(struct nextdisplay_config), M_DEVBUF, M_WAITOK);
nextdisplay_init(sc->sc_dc, iscolor);
}
printf(": %d x %d, %dbpp\n", sc->sc_dc->dc_wid, sc->sc_dc->dc_ht,
sc->sc_dc->dc_depth);
if (iscolor) {
#if 0
uint8_t x;
x = *(volatile uint8_t *)IIOV(NEXT_P_C16_CMD_REG);
aprint_debug_dev(sc->sc_dev, "cmd=%02x\n", x);
#endif
*(volatile uint8_t *)IIOV(NEXT_P_C16_CMD_REG) = 0x05;
isrlink_autovec(nextdisplay_intr, sc, NEXT_I_IPL(NEXT_I_C16_VIDEO), 1, NULL);
INTR_ENABLE(NEXT_I_C16_VIDEO);
}
/* initialize the raster */
waa.console = isconsole;
waa.scrdata = iscolor ? &nextdisplay_screenlist_color : &nextdisplay_screenlist_mono;
waa.accessops = &nextdisplay_accessops;
waa.accesscookie = sc;
#if 0
printf("nextdisplay: access cookie is %p\n", sc);
#endif
config_found(self, &waa, wsemuldisplaydevprint);
}
void
nextdma_init(struct nextdma_softc *nsc)
{
#ifdef ND_DEBUG
if (NEXTDMA_DEBUG) {
char sbuf[256];
bitmask_snprintf(NEXT_I_BIT(nsc->sc_chan->nd_intr), NEXT_INTR_BITS,
sbuf, sizeof(sbuf));
printf("DMA init ipl (%ld) intr(0x%s)\n",
NEXT_I_IPL(nsc->sc_chan->nd_intr), sbuf);
}
#endif
nsc->sc_stat.nd_map = NULL;
nsc->sc_stat.nd_idx = 0;
nsc->sc_stat.nd_map_cont = NULL;
nsc->sc_stat.nd_idx_cont = 0;
nsc->sc_stat.nd_exception = 0;
nd_bsw4 (DD_CSR, DMACSR_RESET | DMACSR_CLRCOMPLETE);
nd_bsw4 (DD_CSR, 0);
#if 01
nextdma_setup_curr_regs(nsc);
nextdma_setup_cont_regs(nsc);
#endif
#if defined(DIAGNOSTIC)
{
u_long state;
state = nd_bsr4 (DD_CSR);
#if 1
/* mourning (a 25 MHz 68040 mono slab) appears to set BUSEXC
* milo (a 25 MHz 68040 mono cube) didn't have this problem
* Darrin B. Jewell <*****@*****.**> Mon May 25 07:53:05 1998
*/
state &= (DMACSR_COMPLETE | DMACSR_SUPDATE | DMACSR_ENABLE);
#else
state &= (DMACSR_BUSEXC | DMACSR_COMPLETE |
DMACSR_SUPDATE | DMACSR_ENABLE);
#endif
if (state) {
nextdma_print(nsc);
panic("DMA did not reset");
}
}
#endif
}
/*
* Set up the real-time and statistics clocks. Leave stathz 0 only
* if no alternative timer is available.
*
* The frequencies of these clocks must be an even number of microseconds.
*/
void
cpu_initclocks(void)
{
int s, cnt;
volatile struct timer_reg *timer;
rtc_init();
hz = 100;
s = splclock();
timer = (volatile struct timer_reg *)IIOV(NEXT_P_TIMER);
cnt = 1000000/hz; /* usec timer */
timer->csr = 0;
timer->msb = (cnt >> 8);
timer->lsb = cnt;
timer->csr = TIMER_REG_ENABLE|TIMER_REG_UPDATE;
isrlink_autovec(clock_intr, NULL, NEXT_I_IPL(NEXT_I_TIMER), 0, NULL);
INTR_ENABLE(NEXT_I_TIMER);
splx(s);
}