/*
* Set up the clock hardware
*/
void Clock_driver_support_initialize_hardware(void)
{
uint32_t period;
CLOCK_REGS->control = ALTERA_AVALON_TIMER_CONTROL_STOP_MSK;
period = (CLOCK_FREQ/1000000L)*rtems_configuration_get_microseconds_per_tick() - 1;
CLOCK_REGS->period_hi = period >> 16;
CLOCK_REGS->period_lo = period & 0xFFFF;
CLOCK_REGS->control = ALTERA_AVALON_TIMER_CONTROL_ITO_MSK |
ALTERA_AVALON_TIMER_CONTROL_CONT_MSK |
ALTERA_AVALON_TIMER_CONTROL_START_MSK;
NIOS2_IENABLE(1 << CLOCK_VECTOR);
}
void benchmark_timer_initialize( void )
{
/* Disable timer interrupt, stop timer */
TIMER_REGS->control = ALTERA_AVALON_TIMER_CONTROL_STOP_MSK;
set_vector((nios2_isr_entry *)timerisr, TIMER_VECTOR, 1);
/* Enable interrupt processing */
NIOS2_IENABLE(1 << TIMER_VECTOR);
#if TIMER_WRAPS_AFTER_1MS
/* Writing to periodl/h resets the counter and eventually
stops it. If the timer hasn't been configured with fixed
period, set it to 1 ms now */
TIMER_REGS->period_hi = (TIMER_FREQ/1000)>>16;
TIMER_REGS->period_lo = (TIMER_FREQ/1000)&0xFFFF;
#else
/* Writing to periodl/h resets the counter and eventually
stops it. Set max period */
TIMER_REGS->period_hi = 0xFFFF;
TIMER_REGS->period_lo = 0xFFFF;
#endif
/* For timers that can be stopped, writing to periodl/h
also stopped the timer and we have to manually start it. */
TIMER_REGS->control = ALTERA_AVALON_TIMER_CONTROL_ITO_MSK |
ALTERA_AVALON_TIMER_CONTROL_CONT_MSK |
ALTERA_AVALON_TIMER_CONTROL_START_MSK;
/* This is the most safe place for resetting the overflow
counter - just _after_ we reset the timer. Depending
on the SOPC configuration, the counter may not be
stoppable and it doesn't make sense to assume that
there is any "safe" period before resetting. */
Timer_interrupts = 0;
}
