int trigger_isr_start(void (*func)(void)) {
/* Check callback and set */
if (func == NULL) {
return -1;
}
callback = func;
/* Clear Pending ISR */
NVIC_ICPR(TRIGGER_ISR_BITREG) |= 1 << (TRIGGER_ISR_IRQ%32);
/* Enable ISR */
NVIC_ISER(TRIGGER_ISR_BITREG) |= 1 << (TRIGGER_ISR_IRQ%32);
/* NVIC_IP is 8 bits wide, upper half contains priority so we shift
* up by 4. The actual register is 32 bits, but the headers only expose 8.
* This is easier than doing the other bit messing.
*/
NVIC_IP(TRIGGER_ISR_IRQ) = (TRIGGER_ISR_PRI) << 4;
/* Set port to GPIO- Needed for interrupt for some reason */
TRIGGER_PCR &= ~PORT_PCR_MUX_MASK;
TRIGGER_PCR |= PORT_PCR_MUX(1);
/* Clear interrupt flag */
TRIGGER_PCR |= PORT_PCR_ISF_MASK;
/* Set interrupt to correct edge & enable */
TRIGGER_PCR &= ~PORT_PCR_IRQC_MASK;
TRIGGER_PCR |= ((TRIGGER_EDGE) ? (0b1001) : (0b1010)) << PORT_PCR_IRQC_SHIFT;
/* Success */
return 0;
}
void set_irq_priority (int irq, int prio)
{
/*irq priority pointer*/
uint8 *prio_reg;
uint8 err = 0;
uint8 div = 0;
/* Make sure that the IRQ is an allowable number. Right now up to 32 is
* used.
*
* NOTE: If you are using the interrupt definitions from the header
* file, you MUST SUBTRACT 16!!!
*/
if (irq > 32)
{
err = 1;
}
if (prio > 3)
{
err = 1;
}
if (err != 1)
{
/* Determine which of the NVICIPx corresponds to the irq */
div = irq / 4;
prio_reg = (uint8 *)((uint32)&NVIC_IP(div));
/* Assign priority to IRQ */
*prio_reg = ( (prio&0x3) << (8 - ARM_INTERRUPT_LEVEL_BITS) );
}
}
/*
* set the priority for a specified interrupt
*/
void int_init(IRQInterruptIndex p_vector, priority_t p_priority)
{
int IRQ = p_vector - 16;
NVIC_IP(IRQ / 4) &= ~(3 << ((8 * (IRQ % 4)) + 6));
NVIC_IP(IRQ / 4) |= (p_priority << ((8 * (IRQ % 4)) + 6));
}
