int trigger_isr_start(void (*func)(void)) { /* Check callback and set */ if (func == NULL) { return -1; } callback = func; /* Clear Pending ISR */ NVIC_ICPR(TRIGGER_ISR_BITREG) |= 1 << (TRIGGER_ISR_IRQ%32); /* Enable ISR */ NVIC_ISER(TRIGGER_ISR_BITREG) |= 1 << (TRIGGER_ISR_IRQ%32); /* NVIC_IP is 8 bits wide, upper half contains priority so we shift * up by 4. The actual register is 32 bits, but the headers only expose 8. * This is easier than doing the other bit messing. */ NVIC_IP(TRIGGER_ISR_IRQ) = (TRIGGER_ISR_PRI) << 4; /* Set port to GPIO- Needed for interrupt for some reason */ TRIGGER_PCR &= ~PORT_PCR_MUX_MASK; TRIGGER_PCR |= PORT_PCR_MUX(1); /* Clear interrupt flag */ TRIGGER_PCR |= PORT_PCR_ISF_MASK; /* Set interrupt to correct edge & enable */ TRIGGER_PCR &= ~PORT_PCR_IRQC_MASK; TRIGGER_PCR |= ((TRIGGER_EDGE) ? (0b1001) : (0b1010)) << PORT_PCR_IRQC_SHIFT; /* Success */ return 0; }
/* * Enable interrupt * Enables the interrupt specified in intvec. */ EXPORT void EnableInt( INTVEC intvec, INT intpri ) { UINT imask, shift; UW pri; DI(imask); /* Set interrupt priority level. */ shift = (intvec % 4) * 8; pri = *(_UW*)(NVIC_IPR(intvec)); pri &= ~(0xff << shift); pri |= (intpri & 0xff) << shift; *(_UW*)(NVIC_IPR(intvec)) = pri; /* Enables the specified interrupt. */ *(_UW*)(NVIC_ISER(intvec)) = (0x01U << (intvec % 32)); EI(imask); }
static void chx_enable_intr (uint8_t irq_num) { NVIC_ISER (irq_num) = 1 << (irq_num & 0x1f); }
void nvic_enable_irq(uint8_t irqn) { NVIC_ISER(irqn / 32) = (1 << (irqn % 32)); }
uint8_t nvic_get_irq_enabled(uint8_t irqn) { return NVIC_ISER(irqn / 32) & (1 << (irqn % 32)) ? 1 : 0; }