bool tegra_udc_charger_detection(void)
{
NvDdkUsbPhyIoctl_DedicatedChargerDetectionInputArgs Charger;
NvDdkUsbPhyIoctl_DedicatedChargerStatusOutputArgs Status;
/* clear the input args */
NvOsMemset(&Charger, 0, sizeof(Charger));
/* enable the charger detection logic */
Charger.EnableChargerDetection = NV_TRUE;
NV_ASSERT_SUCCESS(NvDdkUsbPhyIoctl(
s_hUsbPhy,
NvDdkUsbPhyIoctlType_DedicatedChargerDetection,
&Charger,
NULL));
/* get the charger detection status */
NV_ASSERT_SUCCESS(NvDdkUsbPhyIoctl(
s_hUsbPhy,
NvDdkUsbPhyIoctlType_DedicatedChargerStatus,
NULL,
&Status));
/* disable the charger detection */
Charger.EnableChargerDetection = NV_FALSE;
NV_ASSERT_SUCCESS(NvDdkUsbPhyIoctl(
s_hUsbPhy,
NvDdkUsbPhyIoctlType_DedicatedChargerDetection,
&Charger,
NULL));
return Status.ChargerDetected;
}
static void tegra_ehci_power_down(struct usb_hcd *hcd)
{
struct ehci_hcd *ehci = hcd_to_ehci(hcd);
struct tegra_hcd_platform_data *pdata;
pdata = hcd->self.controller->platform_data;
NV_ASSERT_SUCCESS(NvDdkUsbPhyPowerDown(pdata->hUsbPhy, true, 0));
ehci->host_resumed = 0;
}
int tegra_udc_clk_init(struct platform_device *pdev)
{
NvError nverr;
nverr = NvDdkUsbPhyOpen(s_hRmGlobal, pdev->id, &s_hUsbPhy);
if (nverr != NvSuccess)
return -ENODEV;
/* Power up the USB phy */
NV_ASSERT_SUCCESS(NvDdkUsbPhyPowerUp(s_hUsbPhy, NV_FALSE, 0));
wake_lock_init(&s_wake_lock, WAKE_LOCK_SUSPEND, "tegra-udc");
return 0;
}
static void
UsbPhyOpenHwInterface(
NvDdkUsbPhyHandle hUsbPhy)
{
static NvDdkUsbPhyCapabilities s_UsbPhyCap[] =
{
// AP15
{ NV_FALSE, NV_FALSE },
// AP16
{ NV_FALSE, NV_TRUE },
// AP20
{ NV_TRUE, NV_FALSE},
};
NvDdkUsbPhyCapabilities *pUsbfCap = NULL;
NvRmModuleCapability s_UsbPhyCaps[] =
{
{1, 0, 0, &s_UsbPhyCap[0]}, // AP15 A01
{1, 1, 0, &s_UsbPhyCap[0]}, // AP15 A02
{1, 2, 0, &s_UsbPhyCap[1]}, // AP16, USB1
{1, 3, 0, &s_UsbPhyCap[1]}, // AP16, USB2
{1, 5, 0, &s_UsbPhyCap[2]}, // AP20, USB1
{1, 6, 0, &s_UsbPhyCap[2]}, // AP20, USB2
{1, 7, 0, &s_UsbPhyCap[2]}, // AP20, USB3
};
NV_ASSERT_SUCCESS(
NvRmModuleGetCapabilities(hUsbPhy->hRmDevice,
NVRM_MODULE_ID(NvRmModuleID_Usb2Otg, hUsbPhy->Instance),
s_UsbPhyCaps, NV_ARRAY_SIZE(s_UsbPhyCaps),
(void**)&pUsbfCap));
// Fill the client capabilities structure.
NvOsMemcpy(&hUsbPhy->Caps, pUsbfCap, sizeof(NvDdkUsbPhyCapabilities));
//NvOsDebugPrintf("NvDdkUsbPhyCapabilities::\n");
//NvOsDebugPrintf("PhyRegInController::[%d] 0-FALSE 1-TRUE\n", hUsbPhy->Caps.PhyRegInController);
//NvOsDebugPrintf("CommonClockAndReset::[%d] 0-FALSE 1-TRUE\n", hUsbPhy->Caps.CommonClockAndReset);
if (hUsbPhy->Caps.PhyRegInController)
{
//NvOsDebugPrintf("AP20 USB Controllers\n");
Ap20UsbPhyOpenHwInterface(hUsbPhy);
}
}
void NvRmPwmClose(NvRmPwmHandle hPwm)
{
NvU32 i;
if (!hPwm)
return;
NV_ASSERT(hPwm->RefCount);
NvOsMutexLock(s_hPwmMutex);
hPwm->RefCount--;
if (hPwm->RefCount == 0)
{
// Unmap the pwm register virtual address space
for (i = 0; i < NvRmPwmOutputId_Num-2; i++)
{
NvRmPhysicalMemUnmap((void*)s_hPwm->VirtualAddress[i],
s_hPwm->PwmBankSize);
}
// Unmap the pmc register virtual address space
NvRmPhysicalMemUnmap(
(void*)s_hPwm->VirtualAddress[NvRmPwmOutputId_Num-2],
s_hPwm->PmcBankSize);
if (s_IsPwmFirstConfig)
{
// Disable power
PwmPowerConfigure(hPwm, NV_FALSE);
// Unregister with RM power
NvRmPowerUnRegister(hPwm->RmDeviceHandle, s_PwmPowerID);
// Tri-state the pin-mux pins
NV_ASSERT_SUCCESS(NvRmSetModuleTristate(hPwm->RmDeviceHandle,
NVRM_MODULE_ID(NvRmModuleID_Pwm, 0), NV_TRUE));
s_IsPwmFirstConfig = NV_FALSE;
}
NvOsFree(s_hPwm);
s_hPwm = NULL;
}
NvOsMutexUnlock(s_hPwmMutex);
}
static void
NvEcPrivThreadCreate(NvEcPrivState *ec)
{
int i;
#if ENABLE_FAKE_TIMEOUT_TEST
ec->lastTime = 0xFFFFFFF0;
#else
ec->lastTime = NvOsGetTimeMS();
#endif
ec->timeDiff = NV_WAIT_INFINITE;
for ( i = 0; i < NVEC_NUM; i++ )
{
ec->timeout[i] = NV_WAIT_INFINITE;
ec->timeoutBase[i] = ec->lastTime;
DISP_MESSAGE(("\r\nec->timeout[%d] is set to=%d", i,
ec->timeout[i]));
}
ec->exitThread = NV_FALSE;
NV_ASSERT_SUCCESS( NvOsThreadCreate( NvEcPrivThread, ec, &ec->thread ) );
// FIXME: handle thread create failure
}
void tegra_udc_clk_resume(void)
{
wake_lock_timeout(&s_wake_lock, msecs_to_jiffies(10*1000)); /* lock for 10 seconds */
NV_ASSERT_SUCCESS(NvDdkUsbPhyPowerUp(s_hUsbPhy, NV_FALSE, 0));
}
void tegra_udc_clk_suspend(void)
{
NV_ASSERT_SUCCESS(NvDdkUsbPhyPowerDown(s_hUsbPhy, NV_FALSE, 0));
}
NvError
NvRmPwmOpen(
NvRmDeviceHandle hDevice,
NvRmPwmHandle *phPwm)
{
NvError status = NvSuccess;
NvU32 PwmPhysAddr = 0, i = 0, PmcPhysAddr = 0;
NvRmModuleCapability caps[4];
NvRmModuleCapability *pCap = NULL;
NV_ASSERT(hDevice);
NV_ASSERT(phPwm);
NvOsMutexLock(s_hPwmMutex);
if (s_hPwm)
{
s_hPwm->RefCount++;
goto exit;
}
// Allcoate the memory for the pwm handle
s_hPwm = NvOsAlloc(sizeof(NvRmPwm));
if (!s_hPwm)
{
status = NvError_InsufficientMemory;
goto fail;
}
NvOsMemset(s_hPwm, 0, sizeof(NvRmPwm));
// Set the pwm handle parameters
s_hPwm->RmDeviceHandle = hDevice;
// Get the pwm physical and virtual base address
NvRmModuleGetBaseAddress(hDevice,
NVRM_MODULE_ID(NvRmModuleID_Pwm, 0),
&PwmPhysAddr, &(s_hPwm->PwmBankSize));
s_hPwm->PwmBankSize = PWM_BANK_SIZE;
for (i = 0; i < NvRmPwmOutputId_Num-2; i++)
{
status = NvRmPhysicalMemMap(
PwmPhysAddr + i*s_hPwm->PwmBankSize,
s_hPwm->PwmBankSize,
NVOS_MEM_READ_WRITE,
NvOsMemAttribute_Uncached,
(void**)&s_hPwm->VirtualAddress[i]);
if (status != NvSuccess)
{
NvOsFree(s_hPwm);
goto fail;
}
}
// Get the pmc physical and virtual base address
NvRmModuleGetBaseAddress(hDevice,
NVRM_MODULE_ID(NvRmModuleID_Pmif, 0),
&PmcPhysAddr, &(s_hPwm->PmcBankSize));
s_hPwm->PmcBankSize = PMC_BANK_SIZE;
status = NvRmPhysicalMemMap(
PmcPhysAddr,
s_hPwm->PmcBankSize,
NVOS_MEM_READ_WRITE,
NvOsMemAttribute_Uncached,
(void**)&s_hPwm->VirtualAddress[NvRmPwmOutputId_Num-2]);
if (status != NvSuccess)
{
NvOsFree(s_hPwm);
goto fail;
}
caps[0].MajorVersion = 1;
caps[0].MinorVersion = 0;
caps[0].EcoLevel = 0;
caps[0].Capability = &caps[0];
caps[1].MajorVersion = 1;
caps[1].MinorVersion = 1;
caps[1].EcoLevel = 0;
caps[1].Capability = &caps[1];
caps[2].MajorVersion = 1;
caps[2].MinorVersion = 2;
caps[2].EcoLevel = 0;
caps[2].Capability = &caps[2];
caps[3].MajorVersion = 2;
caps[3].MinorVersion = 0;
caps[3].EcoLevel = 0;
caps[3].Capability = &caps[3];
NV_ASSERT_SUCCESS(NvRmModuleGetCapabilities(
hDevice,
NvRmModuleID_Pwm,
caps,
sizeof(caps)/sizeof(caps[0]),
(void**)&pCap));
if ((pCap->MajorVersion > 1) ||
((pCap->MajorVersion == 1) && (pCap->MinorVersion > 0)))
s_IsFreqDividerSupported = NV_TRUE;
s_hPwm->RefCount++;
exit:
*phPwm = s_hPwm;
NvOsMutexUnlock(s_hPwmMutex);
return NvSuccess;
fail:
NvOsMutexUnlock(s_hPwmMutex);
return status;
}
void
NvDdkUsbPhyClose(
NvDdkUsbPhyHandle hUsbPhy)
{
if (!hUsbPhy)
return;
NvOsMutexLock(s_UsbPhyMutex);
if (!hUsbPhy->RefCount)
{
NvOsMutexUnlock(s_UsbPhyMutex);
return;
}
--hUsbPhy->RefCount;
if (hUsbPhy->RefCount)
{
NvOsMutexUnlock(s_UsbPhyMutex);
return;
}
NvRmSetModuleTristate(
hUsbPhy->hRmDevice,
NVRM_MODULE_ID(NvRmModuleID_Usb2Otg, hUsbPhy->Instance),
NV_TRUE);
NvOsMutexLock(hUsbPhy->ThreadSafetyMutex);
if (hUsbPhy->RmPowerClientId)
{
if (hUsbPhy->IsPhyPoweredUp)
{
NV_ASSERT_SUCCESS(
NvRmPowerModuleClockControl(hUsbPhy->hRmDevice,
NVRM_MODULE_ID(NvRmModuleID_Usb2Otg, hUsbPhy->Instance),
hUsbPhy->RmPowerClientId,
NV_FALSE));
//NvOsDebugPrintf("NvDdkUsbPhyClose::VOLTAGE OFF\n");
NV_ASSERT_SUCCESS(
NvRmPowerVoltageControl(hUsbPhy->hRmDevice,
NVRM_MODULE_ID(NvRmModuleID_Usb2Otg, hUsbPhy->Instance),
hUsbPhy->RmPowerClientId,
NvRmVoltsOff, NvRmVoltsOff,
NULL, 0, NULL));
hUsbPhy->IsPhyPoweredUp = NV_FALSE;
}
// Unregister driver from Power Manager
NvRmPowerUnRegister(hUsbPhy->hRmDevice, hUsbPhy->RmPowerClientId);
NvOsSemaphoreDestroy(hUsbPhy->hPwrEventSem);
}
NvOsMutexUnlock(hUsbPhy->ThreadSafetyMutex);
NvOsMutexDestroy(hUsbPhy->ThreadSafetyMutex);
if (hUsbPhy->CloseHwInterface)
{
hUsbPhy->CloseHwInterface(hUsbPhy);
}
if ((hUsbPhy->pProperty->UsbMode == NvOdmUsbModeType_Host) ||
(hUsbPhy->pProperty->UsbMode == NvOdmUsbModeType_OTG))
{
UsbPrivEnableVbus(hUsbPhy, NV_FALSE);
}
NvOdmEnableUsbPhyPowerRail(NV_FALSE);
NvRmPhysicalMemUnmap(
(void*)hUsbPhy->UsbVirAdr, hUsbPhy->UsbBankSize);
NvRmPhysicalMemUnmap(
(void*)hUsbPhy->MiscVirAdr, hUsbPhy->MiscBankSize);
NvOsMemset(hUsbPhy, 0, sizeof(NvDdkUsbPhy));
NvOsMutexUnlock(s_UsbPhyMutex);
}
