void tegra_dc_sor_set_dp_linkctl(struct tegra_dc_sor_data *sor, int ena,
u8 training_pattern, const struct tegra_dc_dp_link_config *cfg)
{
u32 reg_val;
reg_val = tegra_sor_readl(sor, NV_SOR_DP_LINKCTL(sor->portnum));
if (ena)
reg_val |= NV_SOR_DP_LINKCTL_ENABLE_YES;
else
reg_val &= NV_SOR_DP_LINKCTL_ENABLE_NO;
reg_val &= ~NV_SOR_DP_LINKCTL_TUSIZE_MASK;
reg_val |= (cfg->tu_size << NV_SOR_DP_LINKCTL_TUSIZE_SHIFT);
if (cfg->enhanced_framing)
reg_val |= NV_SOR_DP_LINKCTL_ENHANCEDFRAME_ENABLE;
tegra_sor_writel(sor, NV_SOR_DP_LINKCTL(sor->portnum), reg_val);
switch (training_pattern) {
case trainingPattern_1:
tegra_sor_writel(sor, NV_SOR_DP_TPG, 0x41414141);
break;
case trainingPattern_2:
case trainingPattern_3:
reg_val = (cfg->link_bw == NV_SOR_LINK_SPEED_G5_4) ?
0x43434343 : 0x42424242;
tegra_sor_writel(sor, NV_SOR_DP_TPG, reg_val);
break;
default:
tegra_sor_writel(sor, NV_SOR_DP_TPG, 0x50505050);
break;
}
}
void tegra_dc_sor_set_lane_count(struct tegra_dc_sor_data *sor, u8 lane_count)
{
u32 reg_val;
reg_val = tegra_sor_readl(sor, NV_SOR_DP_LINKCTL(sor->portnum));
reg_val &= ~NV_SOR_DP_LINKCTL_LANECOUNT_MASK;
switch (lane_count) {
case 0:
break;
case 1:
reg_val |= NV_SOR_DP_LINKCTL_LANECOUNT_ONE;
break;
case 2:
reg_val |= NV_SOR_DP_LINKCTL_LANECOUNT_TWO;
break;
case 4:
reg_val |= NV_SOR_DP_LINKCTL_LANECOUNT_FOUR;
break;
default:
/* 0 should be handled earlier. */
printk(BIOS_ERR, "dp: Invalid lane count %d\n",
lane_count);
return;
}
tegra_sor_writel(sor, NV_SOR_DP_LINKCTL(sor->portnum), reg_val);
}
void tegra_dc_sor_read_link_config(struct tegra_dc_sor_data *sor, u8 *link_bw,
u8 *lane_count)
{
u32 reg_val;
reg_val = tegra_sor_readl(sor, NV_SOR_CLK_CNTRL);
*link_bw = (reg_val & NV_SOR_CLK_CNTRL_DP_LINK_SPEED_MASK)
>> NV_SOR_CLK_CNTRL_DP_LINK_SPEED_SHIFT;
reg_val = tegra_sor_readl(sor,
NV_SOR_DP_LINKCTL(sor->portnum));
switch (reg_val & NV_SOR_DP_LINKCTL_LANECOUNT_MASK) {
case NV_SOR_DP_LINKCTL_LANECOUNT_ZERO:
*lane_count = 0;
break;
case NV_SOR_DP_LINKCTL_LANECOUNT_ONE:
*lane_count = 1;
break;
case NV_SOR_DP_LINKCTL_LANECOUNT_TWO:
*lane_count = 2;
break;
case NV_SOR_DP_LINKCTL_LANECOUNT_FOUR:
*lane_count = 4;
break;
default:
printk(BIOS_ERR, "Unknown lane count\n");
}
}
void tegra_dc_sor_set_dp_lanedata(struct tegra_dc_sor_data *sor,
u32 lane, u32 pre_emphasis, u32 drive_current, u32 tx_pu)
{
u32 d_cur;
u32 p_emp;
d_cur = tegra_sor_readl(sor, NV_SOR_DC(sor->portnum));
p_emp = tegra_sor_readl(sor, NV_SOR_PR(sor->portnum));
switch (lane) {
case 0:
p_emp &= ~NV_SOR_PR_LANE2_DP_LANE0_MASK;
p_emp |= (pre_emphasis <<
NV_SOR_PR_LANE2_DP_LANE0_SHIFT);
d_cur &= ~NV_SOR_DC_LANE2_DP_LANE0_MASK;
d_cur |= (drive_current <<
NV_SOR_DC_LANE2_DP_LANE0_SHIFT);
break;
case 1:
p_emp &= ~NV_SOR_PR_LANE1_DP_LANE1_MASK;
p_emp |= (pre_emphasis <<
NV_SOR_PR_LANE1_DP_LANE1_SHIFT);
d_cur &= ~NV_SOR_DC_LANE1_DP_LANE1_MASK;
d_cur |= (drive_current <<
NV_SOR_DC_LANE1_DP_LANE1_SHIFT);
break;
case 2:
p_emp &= ~NV_SOR_PR_LANE0_DP_LANE2_MASK;
p_emp |= (pre_emphasis <<
NV_SOR_PR_LANE0_DP_LANE2_SHIFT);
d_cur &= ~NV_SOR_DC_LANE0_DP_LANE2_MASK;
d_cur |= (drive_current <<
NV_SOR_DC_LANE0_DP_LANE2_SHIFT);
break;
case 3:
p_emp &= ~NV_SOR_PR_LANE3_DP_LANE3_MASK;
p_emp |= (pre_emphasis <<
NV_SOR_PR_LANE3_DP_LANE3_SHIFT);
d_cur &= ~NV_SOR_DC_LANE3_DP_LANE3_MASK;
d_cur |= (drive_current <<
NV_SOR_DC_LANE3_DP_LANE3_SHIFT);
break;
default:
printk(BIOS_SPEW, "dp: sor lane count %d is invalid\n", lane);
}
tegra_sor_write_field(sor, NV_SOR_DP_LINKCTL(sor->portnum),
NV_SOR_DP_PADCTL_TX_PU_VALUE_DEFAULT_MASK,
tx_pu << NV_SOR_DP_PADCTL_TX_PU_VALUE_SHIFT);
tegra_sor_writel(sor, NV_SOR_DC(sor->portnum), d_cur);
tegra_sor_writel(sor, NV_SOR_PR(sor->portnum), p_emp);
}
static void dump_sor_reg(struct tegra_dc_sor_data *sor)
{
#define DUMP_REG(a) printk(BIOS_INFO, "%-32s %03x %08x\n", \
#a, a, tegra_sor_readl(sor, a));
DUMP_REG(NV_SOR_SUPER_STATE0);
DUMP_REG(NV_SOR_SUPER_STATE1);
DUMP_REG(NV_SOR_STATE0);
DUMP_REG(NV_SOR_STATE1);
DUMP_REG(NV_HEAD_STATE0(0));
DUMP_REG(NV_HEAD_STATE0(1));
DUMP_REG(NV_HEAD_STATE1(0));
DUMP_REG(NV_HEAD_STATE1(1));
DUMP_REG(NV_HEAD_STATE2(0));
DUMP_REG(NV_HEAD_STATE2(1));
DUMP_REG(NV_HEAD_STATE3(0));
DUMP_REG(NV_HEAD_STATE3(1));
DUMP_REG(NV_HEAD_STATE4(0));
DUMP_REG(NV_HEAD_STATE4(1));
DUMP_REG(NV_HEAD_STATE5(0));
DUMP_REG(NV_HEAD_STATE5(1));
DUMP_REG(NV_SOR_CRC_CNTRL);
DUMP_REG(NV_SOR_CLK_CNTRL);
DUMP_REG(NV_SOR_CAP);
DUMP_REG(NV_SOR_PWR);
DUMP_REG(NV_SOR_TEST);
DUMP_REG(NV_SOR_PLL0);
DUMP_REG(NV_SOR_PLL1);
DUMP_REG(NV_SOR_PLL2);
DUMP_REG(NV_SOR_PLL3);
DUMP_REG(NV_SOR_CSTM);
DUMP_REG(NV_SOR_LVDS);
DUMP_REG(NV_SOR_CRCA);
DUMP_REG(NV_SOR_CRCB);
DUMP_REG(NV_SOR_SEQ_CTL);
DUMP_REG(NV_SOR_LANE_SEQ_CTL);
DUMP_REG(NV_SOR_SEQ_INST(0));
DUMP_REG(NV_SOR_SEQ_INST(1));
DUMP_REG(NV_SOR_SEQ_INST(2));
DUMP_REG(NV_SOR_SEQ_INST(3));
DUMP_REG(NV_SOR_SEQ_INST(4));
DUMP_REG(NV_SOR_SEQ_INST(5));
DUMP_REG(NV_SOR_SEQ_INST(6));
DUMP_REG(NV_SOR_SEQ_INST(7));
DUMP_REG(NV_SOR_SEQ_INST(8));
DUMP_REG(NV_SOR_PWM_DIV);
DUMP_REG(NV_SOR_PWM_CTL);
DUMP_REG(NV_SOR_MSCHECK);
DUMP_REG(NV_SOR_XBAR_CTRL);
DUMP_REG(NV_SOR_DP_LINKCTL(0));
DUMP_REG(NV_SOR_DP_LINKCTL(1));
DUMP_REG(NV_SOR_DC(0));
DUMP_REG(NV_SOR_DC(1));
DUMP_REG(NV_SOR_LANE_DRIVE_CURRENT(0));
DUMP_REG(NV_SOR_PR(0));
DUMP_REG(NV_SOR_LANE4_PREEMPHASIS(0));
DUMP_REG(NV_SOR_POSTCURSOR(0));
DUMP_REG(NV_SOR_DP_CONFIG(0));
DUMP_REG(NV_SOR_DP_CONFIG(1));
DUMP_REG(NV_SOR_DP_MN(0));
DUMP_REG(NV_SOR_DP_MN(1));
DUMP_REG(NV_SOR_DP_PADCTL(0));
DUMP_REG(NV_SOR_DP_PADCTL(1));
DUMP_REG(NV_SOR_DP_DEBUG(0));
DUMP_REG(NV_SOR_DP_DEBUG(1));
DUMP_REG(NV_SOR_DP_SPARE(0));
DUMP_REG(NV_SOR_DP_SPARE(1));
DUMP_REG(NV_SOR_DP_TPG);
return;
}
