//common case, except Win2K
static void DebugPrint(const char *fmt, ...)
{
va_list list;
va_start(list, fmt);
PrintProcedure(DPFLTR_DEFAULT_ID, 9 | DPFLTR_MASK, fmt, list);
#if defined(VIRTIO_DBG_USE_IOPORT)
{
NTSTATUS status;
// use this way of output only for DISPATCH_LEVEL,
// higher requires more protection
if (KeGetCurrentIrql() <= DISPATCH_LEVEL)
{
char buf[256];
size_t len, i;
buf[0] = 0;
status = RtlStringCbVPrintfA(buf, sizeof(buf), fmt, list);
if (status == STATUS_SUCCESS) len = strlen(buf);
else if (status == STATUS_BUFFER_OVERFLOW) len = sizeof(buf);
else { memcpy(buf, "Can't print", 11); len = 11; }
NdisAcquireSpinLock(&CrashLock);
for (i = 0; i < len; ++i)
{
NdisRawWritePortUchar(VIRTIO_DBG_USE_IOPORT, buf[i]);
}
NdisRawWritePortUchar(VIRTIO_DBG_USE_IOPORT, '\n');
NdisReleaseSpinLock(&CrashLock);
}
}
#endif
}
BOOLEAN
LtInitGetAddressSetPoll(
IN PLT_ADAPTER Adapter,
IN UCHAR SuggestedNodeId
)
/*++
Routine Description:
This gets the node id from the card (starts it off actually) and
sets the card to be in polling mode.
Arguments:
Adapter : Pointer to the adapter structure
SuggestedNodeId : Pram node id or 0
Return Value:
TRUE : if success, FALSE otherwise
--*/
{
ULONG Seed, Random;
DBGPRINT(DBG_COMP_INIT, DBG_LEVEL_INFO,
("LtGetAddress: Getting a node address for lt adapter...\n"));
if (SuggestedNodeId == 0)
{
Seed = (ULONG)Adapter;
Random = RtlRandom(&Seed);
SuggestedNodeId =
(UCHAR)((Random % LT_MAX_CLIENT_NODE_ID) + LT_MIN_SERVER_NODE_ID);
}
DBGPRINT(DBG_COMP_INIT, DBG_LEVEL_INFO,
("LtGetAddress: Suggested Node Id = %lx\n", SuggestedNodeId));
// Command Length LSB
NdisRawWritePortUchar(XFER_PORT, 2);
// Command Length MSB
NdisRawWritePortUchar(XFER_PORT, 0);
NdisRawWritePortUchar(XFER_PORT, (UCHAR)LT_CMD_LAP_INIT);
NdisRawWritePortUchar(XFER_PORT, SuggestedNodeId);
// Use 0xFF for the interrupt if this card is to be polled.
// We *ONLY* support polling.
NdisRawWritePortUchar(XFER_PORT, LT_ADAPTER_POLLED_MODE);
return TRUE;
}
void cf_write8(struct intf_hdl *pintfhdl, u32 addr, u8 val)
{
_irqL irqL;
uint res;
struct _SyncContext synccontext;
struct intf_priv *pintfpriv = pintfhdl->pintfpriv;
//u8 *rwmem = pintfpriv->io_rwmem;
struct dvobj_priv * pcfiodev = (struct dvobj_priv * )(pintfpriv->intf_dev);
u32 iobase_addr = pcfiodev->io_base_address;
// Please remember, you just can't only use lock/unlock to
// protect the rw functions...
// since, i/o is quite common in call-back and isr routines...
_func_enter_;
_enter_hwio_critical(&pintfpriv->rwlock, &irqL);
#ifdef PLATFORM_WINDOWS
if( addr >= RTL8711_HCICTRL_ && addr <= (RTL8711_HCICTRL_+0x1FFFF) )
{ //the address is in HCI local register
addr = (addr&0x00003FFF);
NdisRawWritePortUchar((u32)(iobase_addr+addr), val);
}else{
synccontext.pintfpriv = pintfpriv;
synccontext.lbusaddr = addr;
synccontext.bytecnt = 1; // 1-byte
synccontext.pdata=(u8 *)&val;
//NdisMoveMemory(rwmem ,&val, pintfpriv->len);
irqL = KeGetCurrentIrql();
if ( irqL <= DISPATCH_LEVEL )
res = NdisMSynchronizeWithInterrupt(&pcfiodev->interrupt, cfbus_write, (void *)&synccontext);
else//IRQL > DISPATCH_LEVEL
res = cfbus_write((void *)&synccontext);
}
#endif
_exit_hwio_critical(&pintfpriv->rwlock, &irqL);
_func_exit_;
}
void
PlatformDisableHostL0s(struct net_device *dev)
{
struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
u32 PciCfgAddrPort=0;
u8 Num4Bytes;
u8 uPciBridgeASPMSetting = 0;
if( (priv->NdisAdapter.BusNumber == 0xff &&
priv->NdisAdapter.DevNumber == 0xff &&
priv->NdisAdapter.FuncNumber == 0xff) ||
(priv->NdisAdapter.PciBridgeBusNum == 0xff &&
priv->NdisAdapter.PciBridgeDevNum == 0xff &&
priv->NdisAdapter.PciBridgeFuncNum == 0xff) )
{
printk("PlatformDisableHostL0s(): Fail to enable ASPM. "
"Cannot find the Bus of PCI(Bridge).\n");
return;
}
PciCfgAddrPort= (priv->NdisAdapter.PciBridgeBusNum << 16)|
(priv->NdisAdapter.PciBridgeDevNum<< 11)|
(priv->NdisAdapter.PciBridgeFuncNum << 8)|(1 << 31);
Num4Bytes = (priv->NdisAdapter.PciBridgePCIeHdrOffset+0x10)/4;
NdisRawWritePortUlong(PCI_CONF_ADDRESS , PciCfgAddrPort+(Num4Bytes << 2));
NdisRawReadPortUchar(PCI_CONF_DATA, &uPciBridgeASPMSetting);
if(uPciBridgeASPMSetting & BIT0)
uPciBridgeASPMSetting &= ~(BIT0);
NdisRawWritePortUlong(PCI_CONF_ADDRESS , PciCfgAddrPort+(Num4Bytes << 2));
NdisRawWritePortUchar(PCI_CONF_DATA, uPciBridgeASPMSetting);
udelay(50);
printk("PlatformDisableHostL0s():PciBridge BusNumber[%x], "
"DevNumbe[%x], FuncNumber[%x], Write reg[%x] = %x\n",
priv->NdisAdapter.PciBridgeBusNum,
priv->NdisAdapter.PciBridgeDevNum,
priv->NdisAdapter.PciBridgeFuncNum,
(priv->NdisAdapter.PciBridgePCIeHdrOffset+0x10),
(priv->NdisAdapter.PciBridgeLinkCtrlReg |
(priv->RegDevicePciASPMSetting&~BIT0)));
}
U32 C_DM9000::DeviceWritePort(
U32 uPort,
U32 uValue)
{
ENTER_CRITICAL_SECTION
VALIDATE_ADDR_PORT(uPort);
NdisRawWritePortUchar(
m_szCurrentSettings[SID_PORT_BASE_ADDRESS] + DM9000_DATA_OFFSET,
(U8)uValue);
LEAVE_CRITICAL_SECTION
return uValue;
}
void PlatformEnableASPM(struct net_device *dev)
{
struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
PRT_POWER_SAVE_CONTROL pPSC =
(PRT_POWER_SAVE_CONTROL)(&(priv->rtllib->PowerSaveControl));
u16 ASPMLevel = 0;
u32 PciCfgAddrPort=0;
u8 Num4Bytes;
u8 uPciBridgeASPMSetting = 0;
u8 uDeviceASPMSetting = 0;
if( (priv->NdisAdapter.BusNumber == 0xff &&
priv->NdisAdapter.DevNumber == 0xff &&
priv->NdisAdapter.FuncNumber == 0xff) ||
(priv->NdisAdapter.PciBridgeBusNum == 0xff &&
priv->NdisAdapter.PciBridgeDevNum == 0xff &&
priv->NdisAdapter.PciBridgeFuncNum == 0xff) ) {
RT_TRACE(COMP_INIT, "PlatformEnableASPM(): Fail to enable ASPM."
" Cannot find the Bus of PCI(Bridge).\n");
return;
}
#ifdef RTL8192SE
if(priv->NdisAdapter.PciBridgeVendor != PCI_BRIDGE_VENDOR_INTEL) {
RT_TRACE(COMP_POWER, "%s(): Dont modify ASPM for non intel "
"chipset. For Bridge Vendor %d.\n"
,__func__,priv->NdisAdapter.PciBridgeVendor);
return;
}
#endif
#ifdef RTL8192CE
PciCfgAddrPort= (priv->NdisAdapter.PciBridgeBusNum << 16)|
(priv->NdisAdapter.PciBridgeDevNum<< 11) |
(priv->NdisAdapter.PciBridgeFuncNum << 8)|(1 << 31);
Num4Bytes = (priv->NdisAdapter.PciBridgePCIeHdrOffset+0x10)/4;
NdisRawWritePortUlong(PCI_CONF_ADDRESS , PciCfgAddrPort+(Num4Bytes << 2));
uPciBridgeASPMSetting = priv->NdisAdapter.PciBridgeLinkCtrlReg |
priv->RegHostPciASPMSetting;
if(priv->NdisAdapter.PciBridgeVendor == PCI_BRIDGE_VENDOR_INTEL)
uPciBridgeASPMSetting &= ~ BIT0;
NdisRawWritePortUchar(PCI_CONF_DATA, uPciBridgeASPMSetting);
RT_TRACE(COMP_INIT, "PlatformEnableASPM():PciBridge BusNumber[%x], "
"DevNumbe[%x], FuncNumber[%x], Write reg[%x] = %x\n",
priv->NdisAdapter.PciBridgeBusNum,
priv->NdisAdapter.PciBridgeDevNum,
priv->NdisAdapter.PciBridgeFuncNum,
(priv->NdisAdapter.PciBridgePCIeHdrOffset+0x10),
uPciBridgeASPMSetting);
udelay(50);
#endif
ASPMLevel |= priv->RegDevicePciASPMSetting;
uDeviceASPMSetting = priv->NdisAdapter.LinkCtrlReg;
#ifdef RTL8192SE
if(priv->CustomerID == RT_CID_TOSHIBA &&
priv->NdisAdapter.PciBridgeVendor == PCI_BRIDGE_VENDOR_AMD) {
if(priv->NdisAdapter.LinkCtrlReg & BIT1)
uDeviceASPMSetting |= BIT0;
else
uDeviceASPMSetting |= ASPMLevel;
}
else
#endif
uDeviceASPMSetting |= ASPMLevel;
PlatformSwitchDevicePciASPM(dev, uDeviceASPMSetting);
if (pPSC->RegRfPsLevel & RT_RF_OFF_LEVL_CLK_REQ) {
PlatformSwitchClkReq(dev,(pPSC->RegRfPsLevel & RT_RF_OFF_LEVL_CLK_REQ) ? 1 : 0);
RT_SET_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_CLK_REQ);
}
udelay(100);
#ifdef RTL8192SE
PciCfgAddrPort= (priv->NdisAdapter.PciBridgeBusNum << 16)|
(priv->NdisAdapter.PciBridgeDevNum<< 11)|
(priv->NdisAdapter.PciBridgeFuncNum << 8)|(1 << 31);
Num4Bytes = (priv->NdisAdapter.PciBridgePCIeHdrOffset+0x10)/4;
NdisRawWritePortUlong(PCI_CONF_ADDRESS , PciCfgAddrPort+(Num4Bytes << 2));
uPciBridgeASPMSetting = priv->NdisAdapter.PciBridgeLinkCtrlReg |
priv->RegHostPciASPMSetting;
if(priv->CustomerID == RT_CID_TOSHIBA &&
priv->NdisAdapter.PciBridgeVendor == PCI_BRIDGE_VENDOR_AMD
&& pPSC->RegAMDPciASPM) {
if(priv->NdisAdapter.PciBridgeLinkCtrlReg & BIT1)
uPciBridgeASPMSetting |= BIT0;
} else if(priv->NdisAdapter.PciBridgeVendor == PCI_BRIDGE_VENDOR_INTEL ) {
uPciBridgeASPMSetting &= ~ BIT0;
}
NdisRawWritePortUchar(PCI_CONF_DATA, uPciBridgeASPMSetting);
RT_TRACE(COMP_INIT, "%s:PciBridge BusNumber[%x], DevNumbe[%x], "
"FuncNumber[%x], Write reg[%x] = %x\n",__func__,
priv->NdisAdapter.PciBridgeBusNum,
priv->NdisAdapter.PciBridgeDevNum,
priv->NdisAdapter.PciBridgeFuncNum,
(priv->NdisAdapter.PciBridgePCIeHdrOffset+0x10),
uPciBridgeASPMSetting);
#endif
udelay(100);
}
void PlatformDisableASPM(struct net_device *dev)
{
struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
PRT_POWER_SAVE_CONTROL pPSC =
(PRT_POWER_SAVE_CONTROL)(&(priv->rtllib->PowerSaveControl));
u32 PciCfgAddrPort=0;
u8 Num4Bytes;
u8 LinkCtrlReg;
u16 PciBridgeLinkCtrlReg, ASPMLevel=0;
if( (priv->NdisAdapter.BusNumber == 0xff &&
priv->NdisAdapter.DevNumber == 0xff &&
priv->NdisAdapter.FuncNumber == 0xff) ||
(priv->NdisAdapter.PciBridgeBusNum == 0xff &&
priv->NdisAdapter.PciBridgeDevNum == 0xff &&
priv->NdisAdapter.PciBridgeFuncNum == 0xff) ) {
RT_TRACE(COMP_INIT, "PlatformEnableASPM(): Fail to enable ASPM."
" Cannot find the Bus of PCI(Bridge).\n");
return;
}
#ifdef RTL8192SE
if(priv->NdisAdapter.PciBridgeVendor != PCI_BRIDGE_VENDOR_INTEL) {
RT_TRACE(COMP_POWER, "%s(): Dont modify ASPM for non intel "
"chipset. For Bridge Vendor %d.\n"
,__func__,priv->NdisAdapter.PciBridgeVendor);
return;
}
#endif
#ifdef RTL8192CE
if(pPSC->RegRfPsLevel & RT_RF_OFF_LEVL_CLK_REQ) {
RT_CLEAR_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_CLK_REQ);
PlatformSwitchClkReq(dev, 0x0);
}
{
u8 tmpU1b;
pci_read_config_byte(priv->pdev, 0x80, &tmpU1b);
}
#endif
LinkCtrlReg = priv->NdisAdapter.LinkCtrlReg;
PciBridgeLinkCtrlReg = priv->NdisAdapter.PciBridgeLinkCtrlReg;
ASPMLevel |= BIT0|BIT1;
LinkCtrlReg &=~ASPMLevel;
PciBridgeLinkCtrlReg &=~(BIT0|BIT1);
#ifdef RTL8192CE
PlatformSwitchDevicePciASPM(dev, LinkCtrlReg);
udelay( 50);
#endif
PciCfgAddrPort= (priv->NdisAdapter.PciBridgeBusNum << 16)|
(priv->NdisAdapter.PciBridgeDevNum<< 11)|
(priv->NdisAdapter.PciBridgeFuncNum << 8)|(1 << 31);
Num4Bytes = (priv->NdisAdapter.PciBridgePCIeHdrOffset+0x10)/4;
NdisRawWritePortUlong(PCI_CONF_ADDRESS , PciCfgAddrPort+(Num4Bytes << 2));
NdisRawWritePortUchar(PCI_CONF_DATA, PciBridgeLinkCtrlReg);
RT_TRACE(COMP_POWER, "%s:PciBridge BusNumber[%x], "
"DevNumbe[%x], FuncNumber[%x], Write reg[%x] = %x\n", __func__,
priv->NdisAdapter.PciBridgeBusNum,
priv->NdisAdapter.PciBridgeDevNum,
priv->NdisAdapter.PciBridgeFuncNum,
(priv->NdisAdapter.PciBridgePCIeHdrOffset+0x10),
PciBridgeLinkCtrlReg);
udelay(50);
#ifdef RTL8192SE
PlatformSwitchDevicePciASPM(dev, LinkCtrlReg);
PlatformSwitchClkReq(dev, 0x0);
if (pPSC->RegRfPsLevel & RT_RF_OFF_LEVL_CLK_REQ)
RT_CLEAR_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_CLK_REQ);
udelay(100);
#endif
}
BOOLEAN
LanceHardwareDetails(
IN PLANCE_ADAPTER Adapter
)
/*++
Routine Description:
This routine gets the network address from the hardware.
Arguments:
Adapter - Where to store the network address.
Return Value:
TRUE - if successful.
--*/
{
UCHAR Signature[] = { 0xff, 0x00, 0x55, 0xaa, 0xff, 0x00, 0x55, 0xaa};
UCHAR BytesRead[8];
UINT ReadCount;
UINT Place;
//
// Reset E-PROM state
//
// To do this we first read from the E-PROM address until the
// specific signature is reached (then the next bytes read from
// the E-PROM address will be the ethernet address of the card).
//
//
// Read first part of the signature
//
for (Place=0; Place < 8; Place++){
NdisRawReadPortUchar((ULONG)(Adapter->NetworkHardwareAddress),
&(BytesRead[Place]));
}
ReadCount = 8;
//
// This advances to the front of the circular buffer.
//
while (ReadCount < 40) {
//
// Check if we have read the signature.
//
for (Place = 0; Place < 8; Place++){
if (BytesRead[Place] != Signature[Place]){
Place = 10;
break;
}
}
//
// If we have read the signature, stop.
//
if (Place != 10){
break;
}
//
// else, move all the bytes down one and read then
// next byte.
//
for (Place = 0; Place < 7; Place++){
BytesRead[Place] = BytesRead[Place+1];
}
NdisRawReadPortUchar((ULONG)(Adapter->NetworkHardwareAddress),
&(BytesRead[7]));
ReadCount++;
}
if (ReadCount == 40){
return(FALSE);
}
//
// Now read the ethernet address of the card.
//
NdisRawReadPortUchar(
(ULONG)(Adapter->NetworkHardwareAddress),
&(Adapter->NetworkAddress[0])
);
NdisRawReadPortUchar(
(ULONG)(Adapter->NetworkHardwareAddress),
&(Adapter->NetworkAddress[1])
);
NdisRawReadPortUchar(
(ULONG)(Adapter->NetworkHardwareAddress),
&(Adapter->NetworkAddress[2])
);
NdisRawReadPortUchar(
(ULONG)(Adapter->NetworkHardwareAddress),
&(Adapter->NetworkAddress[3])
);
NdisRawReadPortUchar(
(ULONG)(Adapter->NetworkHardwareAddress),
&(Adapter->NetworkAddress[4])
);
NdisRawReadPortUchar(
(ULONG)(Adapter->NetworkHardwareAddress),
&(Adapter->NetworkAddress[5])
);
if (!(Adapter->LanceCard & (LANCE_DE201 | LANCE_DE422))) {
if (Adapter->LanceCard == LANCE_DEPCA){
//
// Reset Lan Interface port.
//
NdisRawWritePortUchar(
(ULONG)(LANCE_DEPCA_LAN_CFG_OFFSET +
Adapter->Nicsr),
0x00);
//
// Reset Network Interface Control Status Register
//
NdisRawWritePortUshort((ULONG)(Adapter->Nicsr), 0x00);
}
return(TRUE);
}
//
// Now do the EPROM Hardware check as outlined in the tech ref.
//
//
// Check for NULL address.
//
for (Place = 0; Place < 6; Place++) {
if (Adapter->NetworkAddress[Place] != 0) {
Place = 10;
break;
}
}
if (Place != 10) {
return(FALSE);
}
//
// Check that bit 0 is not a 1
//
if (Adapter->NetworkAddress[0] & 0x1) {
return(FALSE);
}
//
// Check that octet[0]->octet[7] == octet[15]->octet[8]
//
NdisRawReadPortUchar(
(ULONG)(Adapter->NetworkHardwareAddress),
&(BytesRead[6])
);
NdisRawReadPortUchar(
(ULONG)(Adapter->NetworkHardwareAddress),
&(BytesRead[7])
);
NdisRawReadPortUchar(
(ULONG)(Adapter->NetworkHardwareAddress),
&(BytesRead[0])
);
NdisRawReadPortUchar(
(ULONG)(Adapter->NetworkHardwareAddress),
&(BytesRead[1])
);
if ((BytesRead[7] != BytesRead[0]) ||
(BytesRead[6] != BytesRead[1])) {
return(FALSE);
}
NdisRawReadPortUchar(
(ULONG)(Adapter->NetworkHardwareAddress),
&(BytesRead[5])
);
NdisRawReadPortUchar(
(ULONG)(Adapter->NetworkHardwareAddress),
&(BytesRead[4])
);
NdisRawReadPortUchar(
(ULONG)(Adapter->NetworkHardwareAddress),
&(BytesRead[3])
);
NdisRawReadPortUchar(
(ULONG)(Adapter->NetworkHardwareAddress),
&(BytesRead[2])
);
NdisRawReadPortUchar(
(ULONG)(Adapter->NetworkHardwareAddress),
&(BytesRead[1])
);
NdisRawReadPortUchar(
(ULONG)(Adapter->NetworkHardwareAddress),
&(BytesRead[0])
);
for (Place = 0; Place < 6; Place++) {
if (BytesRead[Place] != (UCHAR)(Adapter->NetworkAddress[Place])) {
return(FALSE);
}
}
//
// Check that octet[0]->octet[8] == octet[16]->octet[23]
//
NdisRawReadPortUchar(
(ULONG)(Adapter->NetworkHardwareAddress),
&(BytesRead[0])
);
NdisRawReadPortUchar(
(ULONG)(Adapter->NetworkHardwareAddress),
&(BytesRead[1])
);
NdisRawReadPortUchar(
(ULONG)(Adapter->NetworkHardwareAddress),
&(BytesRead[2])
);
NdisRawReadPortUchar(
(ULONG)(Adapter->NetworkHardwareAddress),
&(BytesRead[3])
);
NdisRawReadPortUchar(
(ULONG)(Adapter->NetworkHardwareAddress),
&(BytesRead[4])
);
NdisRawReadPortUchar(
(ULONG)(Adapter->NetworkHardwareAddress),
&(BytesRead[5])
);
for (Place = 0; Place < 6; Place++) {
if (BytesRead[Place] != (UCHAR)(Adapter->NetworkAddress[Place])) {
return(FALSE);
}
}
NdisRawReadPortUchar(
(ULONG)(Adapter->NetworkHardwareAddress),
&(BytesRead[0])
);
NdisRawReadPortUchar(
(ULONG)(Adapter->NetworkHardwareAddress),
&(BytesRead[1])
);
if ((BytesRead[6] != BytesRead[0]) ||
(BytesRead[7] != BytesRead[1])) {
return(FALSE);
}
//
// Check that octet[24] -> octet[31] == signature bytes
//
for (Place = 0; Place < 8; Place++){
NdisRawReadPortUchar(
(ULONG)(Adapter->NetworkHardwareAddress),
&(BytesRead[Place])
);
if (BytesRead[Place] != Signature[Place]){
#if DBG
DbgPrint("Lance: Hardware failure\n");
#endif
return(FALSE);
}
}
if (Adapter->LanceCard == LANCE_DEPCA){
//
// Reset Lan Interface port.
//
NdisRawWritePortUchar(
(ULONG)(LANCE_DEPCA_LAN_CFG_OFFSET +
Adapter->Nicsr),
0x00);
//
// Reset Network Interface Control Status Register
//
NdisRawWritePortUshort((ULONG)(Adapter->Nicsr), 0x00);
}
if (Adapter->LanceCard & (LANCE_DE201 | LANCE_DE422)) {
//
// Reset Network Interface Control Status Register
//
NdisRawWritePortUshort((ULONG)(Adapter->Nicsr), 0x00);
}
return(TRUE);
}
BOOLEAN
LtFirmInitialize(
IN PLT_ADAPTER Adapter,
IN UCHAR SuggestedNodeId
)
/*++
Routine Description:
This routine initializes the card, downloads the firmware to it.
Arguments:
Adapter : Pointer to the adapter structure.
Return Value:
TRUE : If successful, false otherwise
--*/
{
PUCHAR Firmware;
UINT FirmwareLen;
UINT RetryCount;
UCHAR Data;
BOOLEAN Result = FALSE;
// Clear the request Latch
NdisRawReadPortUchar(XFER_PORT, &Data);
// Clear the TX_READY FLOP
NdisRawWritePortUchar(XFER_PORT, (UCHAR)0);
// Reset the card.
NdisRawWritePortUchar(RESET_PORT, (UCHAR)0);
NdisStallExecution(LT_FIRM_INIT_STALL_TIME*5);
for (RetryCount = 0; RetryCount < MAX_READ_RETRY_COUNT; RetryCount++)
{
// Get Card Status.
NdisRawReadPortUchar(SC_PORT, &Data);
if (Data & TX_READY)
{
break;
}
else DBGPRINT(DBG_COMP_INIT, DBG_LEVEL_WARN,
("LtFirmInitialize: Waiting for card ready SC_PORT %x\n", Data));
NdisStallExecution(LT_FIRM_INIT_STALL_TIME);
}
// BUGBUG:
// !!!!!!
// For DAYNA, it will not be ready at this point. DCH is going to
// send information to fix this.
do
{
if (RetryCount == MAX_READ_RETRY_COUNT)
{
LOGERROR(
Adapter->NdisAdapterHandle,
NDIS_ERROR_CODE_HARDWARE_FAILURE);
DBGPRINT(DBG_COMP_INIT, DBG_LEVEL_FATAL,
("LtFirmInitialize: Card Not Ready after Reset\n"));
break;
}
// Copy the firmware to the card.
Firmware = LtMicroCode;
FirmwareLen = sizeof(LtMicroCode);
DBGPRINT(DBG_COMP_INIT, DBG_LEVEL_INFO,
("LtFirmInitialize: DownLoad %d bytes of firmware\n", FirmwareLen));
// Well... the card is alive and well and in a reset state.
// Next we need to output the first byte of the firmware and
// check for TX_READY.
NdisRawWritePortUchar(XFER_PORT, *Firmware);
DBGPRINT(DBG_COMP_INIT, DBG_LEVEL_INFO,
("LtFirmInitialize: First byte of Firmware on card\n"));
NdisRawReadPortUchar(SC_PORT, &Data);
if (Data & TX_READY)
{
DBGPRINT(DBG_COMP_INIT, DBG_LEVEL_FATAL,
("LtFirmInitialize: Card Not Ready During Download\n"));
LOGERROR(
Adapter->NdisAdapterHandle,
NDIS_ERROR_CODE_HARDWARE_FAILURE);
break;
}
// Skip over the first byte because it already out there.
Firmware ++;
FirmwareLen --;
NdisRawWritePortBufferUchar(XFER_PORT,
Firmware,
FirmwareLen);
// Tell the card to start
NdisRawReadPortUchar(XFER_PORT, &Data);
// Wait for the card to start
for (RetryCount = 0; RetryCount < MAX_START_RETRY_COUNT; RetryCount++)
{
NdisStallExecution(LT_FIRM_INIT_STALL_TIME);
// Get Status
NdisRawReadPortUchar(SC_PORT, &Data);
DBGPRINT(DBG_COMP_INIT, DBG_LEVEL_WARN,
("LtFirmInitialize: Waiting for start - SC_PORT Data %x\n",
(UCHAR)Data));
if (Data & RX_READY)
{
break;
}
}
// !!! This seems to be the only way the MCA card works according to
// !!! Dave Hornbaker. It seems that the MCA card doesnt get ready at
// !!! this point, but works later on.
if (RetryCount == MAX_START_RETRY_COUNT)
{
ASSERT(Adapter->BusType != NdisInterfaceMca);
DBGPRINT(DBG_COMP_INIT, DBG_LEVEL_FATAL,
("LtFirmInitialize: Card Not Ready, could not get status\n"));
LOGERROR(
Adapter->NdisAdapterHandle,
NDIS_ERROR_CODE_INVALID_VALUE_FROM_ADAPTER);
break;
}
// Clear the initial ready signal.
NdisRawReadPortUchar(XFER_PORT, &Data);
// Now loop here for a finite time till the card acquires a node id.
// If it fails to do so in the specified time, fail the load.
if (!LtInitGetAddressSetPoll(Adapter, SuggestedNodeId))
{
break;
}
// We need to catch the card fast after it acquire the node id and before it
// receives any packets. If it does receive any packets, then ask it acquire
// the node id again. The stall happens ONLY IF A PACKET IS RECVD.
for (RetryCount = 0; RetryCount < MAX_START_RETRY_COUNT*200; RetryCount++)
{
USHORT ResponseLength;
UCHAR ResponseType;
LT_INIT_RESPONSE InitPacket;
// Check for receive data
NdisRawReadPortUchar(SC_PORT, &Data);
if (Data & RX_READY)
{
// Get the length of the response on the card
NdisRawReadPortUchar(XFER_PORT, &Data);
ResponseLength = (USHORT)(Data & 0xFF);
NdisRawReadPortUchar(XFER_PORT, &Data);
ResponseLength |= (Data << 8);
// Now get the IO code.
NdisRawReadPortUchar(XFER_PORT, &ResponseType);
DBGPRINT(DBG_COMP_INIT, DBG_LEVEL_INFO,
("LtFirmInitialize: RespType = %x, RespLength = %d\n",
ResponseType, ResponseLength));
if ((ResponseType == LT_RSP_LAP_INIT) &&
(ResponseLength == sizeof(LT_INIT_RESPONSE)))
{
NdisRawReadPortBufferUchar(XFER_PORT,
(PUCHAR)&InitPacket,
ResponseLength);
Adapter->NodeId = InitPacket.NodeId;
Adapter->Flags |= ADAPTER_NODE_ID_VALID;
// This should start off a worker thread to write the
// node id into the pram.
// BUGBUG: Implement using worker threads.
// LtRegWritePramNodeId(Adapter);
DBGPRINT(DBG_COMP_INIT, DBG_LEVEL_INFO,
("LtFirmInitailize: Node id acquired %x\n", InitPacket.NodeId));
break;
}
DBGPRINT(DBG_COMP_INIT, DBG_LEVEL_WARN,
("LtFirmInitailize: Node id not valid yet !!\n"));
// Suck in the packet and throw it away
while (ResponseLength-- > 0)
{
NdisRawReadPortUchar(XFER_PORT, &Data);
}
// The response was probably over-written by incoming packet.
// Try again.
NdisStallExecution(LT_FIRM_INIT_STALL_TIME);
DBGPRINT(DBG_COMP_INIT, DBG_LEVEL_WARN,
("LtFirmInitailize: Re-acquire node after packet recv\n"));
if (!LtInitGetAddressSetPoll(Adapter, SuggestedNodeId))
{
break;
}
}
else
{
DBGPRINT(DBG_COMP_INIT, DBG_LEVEL_WARN,
("LtFirmInitialize: Waiting for node - SC_PORT Data %x\n",
(UCHAR)Data));
}
NdisStallExecution(500); // 500us
}
Result = ((Adapter->Flags & ADAPTER_NODE_ID_VALID) != 0);
} while (FALSE);
return(Result);
}
PU8 C_DM9000::DeviceWriteString(
PU8 ptrBuffer,
int nLength)
{
int count;
count = (nLength + m_nIoMaxPad) / m_nIoMode;
#if defined(PREEMPTIVE_TX_WRITE)
switch (m_nIoMode)
{
case BYTE_MODE:
{
PU8 pcurr=(PU8)ptrBuffer;
for(;count--;pcurr++)
{
ENTER_CRITICAL_SECTION
VALIDATE_ADDR_PORT(DM9_MWCMD);
NdisRawWritePortUchar(
m_szCurrentSettings[SID_PORT_BASE_ADDRESS]
+ DM9000_DATA_OFFSET, *pcurr);
LEAVE_CRITICAL_SECTION
}
}
break;
case WORD_MODE:
{
PU16 pcurr=(PU16)ptrBuffer;
for(;count--;pcurr++)
{
ENTER_CRITICAL_SECTION
VALIDATE_ADDR_PORT(DM9_MWCMD);
NdisRawWritePortUshort(
m_szCurrentSettings[SID_PORT_BASE_ADDRESS]
+ DM9000_DATA_OFFSET, *pcurr);
LEAVE_CRITICAL_SECTION
}
}
break;
case DWORD_MODE:
{
PU32 pcurr=(PU32)ptrBuffer;
for(;count--;pcurr++)
{
ENTER_CRITICAL_SECTION
VALIDATE_ADDR_PORT(DM9_MWCMD);
NdisRawWritePortUlong(
m_szCurrentSettings[SID_PORT_BASE_ADDRESS]
+ DM9000_DATA_OFFSET, *pcurr);
LEAVE_CRITICAL_SECTION
}
}
break;
default:
break;
} // of switch
#else // !PREEMPTIVE_TX_WRITE
// select port to be read from
ENTER_CRITICAL_SECTION
VALIDATE_ADDR_PORT(DM9_MWCMD);
switch (m_nIoMode)
{
case BYTE_MODE:
NdisRawWritePortBufferUchar(
m_szCurrentSettings[SID_PORT_BASE_ADDRESS] + DM9000_DATA_OFFSET,
ptrBuffer,count);
break;
case WORD_MODE:
NdisRawWritePortBufferUshort(
m_szCurrentSettings[SID_PORT_BASE_ADDRESS] + DM9000_DATA_OFFSET,
(PU16)ptrBuffer,count);
break;
case DWORD_MODE:
NdisRawWritePortBufferUlong(
m_szCurrentSettings[SID_PORT_BASE_ADDRESS] + DM9000_DATA_OFFSET,
(PU32)ptrBuffer,count);
break;
default:
break;
} // of switch
LEAVE_CRITICAL_SECTION
#endif
return ptrBuffer;
}
