static void
UsbPhyOpenHwInterface(
NvDdkUsbPhyHandle hUsbPhy)
{
static NvDdkUsbPhyCapabilities s_UsbPhyCap[] =
{
// AP15
{ NV_FALSE, NV_FALSE },
// AP16
{ NV_FALSE, NV_TRUE },
// AP20
{ NV_TRUE, NV_FALSE},
};
NvDdkUsbPhyCapabilities *pUsbfCap = NULL;
NvRmModuleCapability s_UsbPhyCaps[] =
{
{1, 0, 0, &s_UsbPhyCap[0]}, // AP15 A01
{1, 1, 0, &s_UsbPhyCap[0]}, // AP15 A02
{1, 2, 0, &s_UsbPhyCap[1]}, // AP16, USB1
{1, 3, 0, &s_UsbPhyCap[1]}, // AP16, USB2
{1, 5, 0, &s_UsbPhyCap[2]}, // AP20, USB1
{1, 6, 0, &s_UsbPhyCap[2]}, // AP20, USB2
{1, 7, 0, &s_UsbPhyCap[2]}, // AP20, USB3
};
NV_ASSERT_SUCCESS(
NvRmModuleGetCapabilities(hUsbPhy->hRmDevice,
NVRM_MODULE_ID(NvRmModuleID_Usb2Otg, hUsbPhy->Instance),
s_UsbPhyCaps, NV_ARRAY_SIZE(s_UsbPhyCaps),
(void**)&pUsbfCap));
// Fill the client capabilities structure.
NvOsMemcpy(&hUsbPhy->Caps, pUsbfCap, sizeof(NvDdkUsbPhyCapabilities));
//NvOsDebugPrintf("NvDdkUsbPhyCapabilities::\n");
//NvOsDebugPrintf("PhyRegInController::[%d] 0-FALSE 1-TRUE\n", hUsbPhy->Caps.PhyRegInController);
//NvOsDebugPrintf("CommonClockAndReset::[%d] 0-FALSE 1-TRUE\n", hUsbPhy->Caps.CommonClockAndReset);
if (hUsbPhy->Caps.PhyRegInController)
{
//NvOsDebugPrintf("AP20 USB Controllers\n");
Ap20UsbPhyOpenHwInterface(hUsbPhy);
}
}
NvError
NvRmPwmOpen(
NvRmDeviceHandle hDevice,
NvRmPwmHandle *phPwm)
{
NvError status = NvSuccess;
NvU32 PwmPhysAddr = 0, i = 0, PmcPhysAddr = 0;
NvRmModuleCapability caps[4];
NvRmModuleCapability *pCap = NULL;
NV_ASSERT(hDevice);
NV_ASSERT(phPwm);
NvOsMutexLock(s_hPwmMutex);
if (s_hPwm)
{
s_hPwm->RefCount++;
goto exit;
}
// Allcoate the memory for the pwm handle
s_hPwm = NvOsAlloc(sizeof(NvRmPwm));
if (!s_hPwm)
{
status = NvError_InsufficientMemory;
goto fail;
}
NvOsMemset(s_hPwm, 0, sizeof(NvRmPwm));
// Set the pwm handle parameters
s_hPwm->RmDeviceHandle = hDevice;
// Get the pwm physical and virtual base address
NvRmModuleGetBaseAddress(hDevice,
NVRM_MODULE_ID(NvRmModuleID_Pwm, 0),
&PwmPhysAddr, &(s_hPwm->PwmBankSize));
s_hPwm->PwmBankSize = PWM_BANK_SIZE;
for (i = 0; i < NvRmPwmOutputId_Num-2; i++)
{
status = NvRmPhysicalMemMap(
PwmPhysAddr + i*s_hPwm->PwmBankSize,
s_hPwm->PwmBankSize,
NVOS_MEM_READ_WRITE,
NvOsMemAttribute_Uncached,
(void**)&s_hPwm->VirtualAddress[i]);
if (status != NvSuccess)
{
NvOsFree(s_hPwm);
goto fail;
}
}
// Get the pmc physical and virtual base address
NvRmModuleGetBaseAddress(hDevice,
NVRM_MODULE_ID(NvRmModuleID_Pmif, 0),
&PmcPhysAddr, &(s_hPwm->PmcBankSize));
s_hPwm->PmcBankSize = PMC_BANK_SIZE;
status = NvRmPhysicalMemMap(
PmcPhysAddr,
s_hPwm->PmcBankSize,
NVOS_MEM_READ_WRITE,
NvOsMemAttribute_Uncached,
(void**)&s_hPwm->VirtualAddress[NvRmPwmOutputId_Num-2]);
if (status != NvSuccess)
{
NvOsFree(s_hPwm);
goto fail;
}
caps[0].MajorVersion = 1;
caps[0].MinorVersion = 0;
caps[0].EcoLevel = 0;
caps[0].Capability = &caps[0];
caps[1].MajorVersion = 1;
caps[1].MinorVersion = 1;
caps[1].EcoLevel = 0;
caps[1].Capability = &caps[1];
caps[2].MajorVersion = 1;
caps[2].MinorVersion = 2;
caps[2].EcoLevel = 0;
caps[2].Capability = &caps[2];
caps[3].MajorVersion = 2;
caps[3].MinorVersion = 0;
caps[3].EcoLevel = 0;
caps[3].Capability = &caps[3];
NV_ASSERT_SUCCESS(NvRmModuleGetCapabilities(
hDevice,
NvRmModuleID_Pwm,
caps,
sizeof(caps)/sizeof(caps[0]),
(void**)&pCap));
if ((pCap->MajorVersion > 1) ||
((pCap->MajorVersion == 1) && (pCap->MinorVersion > 0)))
s_IsFreqDividerSupported = NV_TRUE;
s_hPwm->RefCount++;
exit:
*phPwm = s_hPwm;
NvOsMutexUnlock(s_hPwmMutex);
return NvSuccess;
fail:
NvOsMutexUnlock(s_hPwmMutex);
return status;
}
