static void apic_common_realize(DeviceState *dev, Error **errp)
{
APICCommonState *s = APIC_COMMON(dev);
APICCommonClass *info;
static DeviceState *vapic;
static int apic_no;
static bool mmio_registered;
if (apic_no >= MAX_APICS) {
error_setg(errp, "%s initialization failed.",
object_get_typename(OBJECT(dev)));
return;
}
s->idx = apic_no++;
info = APIC_COMMON_GET_CLASS(s);
info->realize(dev, errp);
if (!mmio_registered) {
ICCBus *b = ICC_BUS(qdev_get_parent_bus(dev));
memory_region_add_subregion(b->apic_address_space, 0, &s->io_memory);
mmio_registered = true;
}
#ifndef CONFIG_HAX
/* Note: We need at least 1M to map the VAPIC option ROM */
if (!vapic && s->vapic_control & VAPIC_ENABLE_MASK &&
ram_size >= 1024 * 1024) {
vapic = sysbus_create_simple("kvmvapic", -1, NULL);
}
#endif
s->vapic = vapic;
if (apic_report_tpr_access && info->enable_tpr_reporting) {
info->enable_tpr_reporting(s, true);
}
}
static void detach(sPAPRDRConnector *drc, DeviceState *d,
spapr_drc_detach_cb *detach_cb,
void *detach_cb_opaque, Error **errp)
{
DPRINTFN("drc: %x, detach", get_index(drc));
drc->detach_cb = detach_cb;
drc->detach_cb_opaque = detach_cb_opaque;
if (drc->isolation_state != SPAPR_DR_ISOLATION_STATE_ISOLATED) {
DPRINTFN("awaiting transition to isolated state before removal");
drc->awaiting_release = true;
return;
}
if (drc->type != SPAPR_DR_CONNECTOR_TYPE_PCI &&
drc->allocation_state != SPAPR_DR_ALLOCATION_STATE_UNUSABLE) {
DPRINTFN("awaiting transition to unusable state before removal");
drc->awaiting_release = true;
return;
}
drc->indicator_state = SPAPR_DR_INDICATOR_STATE_INACTIVE;
if (drc->detach_cb) {
drc->detach_cb(drc->dev, drc->detach_cb_opaque);
}
drc->awaiting_release = false;
g_free(drc->fdt);
drc->fdt = NULL;
drc->fdt_start_offset = 0;
object_property_del(OBJECT(drc), "device", NULL);
drc->dev = NULL;
drc->detach_cb = NULL;
drc->detach_cb_opaque = NULL;
}
static int goldfish_fb_init(SysBusDevice *sbdev)
{
DeviceState *dev = DEVICE(sbdev);
struct goldfish_fb_state *s = GOLDFISH_FB(dev);
dev->id = g_strdup(TYPE_GOLDFISH_FB);
sysbus_init_irq(sbdev, &s->irq);
s->con = graphic_console_init(dev, 0, &goldfish_fb_ops, s);
s->dpi = 165; /* TODO: Find better way to get actual value ! */
s->format = HAL_PIXEL_FORMAT_RGB_565;
memory_region_init_io(&s->iomem, OBJECT(s), &goldfish_fb_iomem_ops, s,
"goldfish_fb", 0x100);
sysbus_init_mmio(sbdev, &s->iomem);
register_savevm(dev, "goldfish_fb", 0, GOLDFISH_FB_SAVE_VERSION,
goldfish_fb_save, goldfish_fb_load, s);
return 0;
}
static int tnetw1130_init(PCIDevice *pci_dev)
{
TNETW1130State *d = DO_UPCAST(TNETW1130State, dev, pci_dev);
tnetw1130_t *s = &d->tnetw1130;
/* TI TNETW1130 */
tnetw1130_pci_config(d->dev.config);
/* Handler for memory-mapped I/O */
memory_region_init_io(&d->mmio_bar0, &tnetw1130_ops0, s, "tnetw1130_mmio0",
TNETW1130_MEM0_SIZE);
memory_region_init_io(&d->mmio_bar1, &tnetw1130_ops1, s, "tnetw1130_mmio1",
TNETW1130_MEM1_SIZE);
pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio_bar0);
pci_register_bar(&d->dev, 1, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio_bar1);
#if 0
static const char macaddr[6] = {
0x00, 0x60, 0x65, 0x02, 0x4a, 0x8e
};
memcpy(s->conf.macaddr.a, macaddr, 6);
#endif
qemu_macaddr_default_if_unset(&s->conf.macaddr);
tnetw1130_reset(s);
s->nic = qemu_new_nic(&net_info, &s->conf,
object_get_typename(OBJECT(pci_dev)),
pci_dev->qdev.id, s);
qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
qemu_register_reset(nic_reset, d);
return 0;
}
static int scsi_hot_add(Monitor *mon, DeviceState *adapter,
DriveInfo *dinfo, int printinfo)
{
SCSIBus *scsibus;
SCSIDevice *scsidev;
scsibus = (SCSIBus *)
object_dynamic_cast(OBJECT(QLIST_FIRST(&adapter->child_bus)),
TYPE_SCSI_BUS);
if (!scsibus) {
error_report("Device is not a SCSI adapter");
return -1;
}
/*
* drive_init() tries to find a default for dinfo->unit. Doesn't
* work at all for hotplug though as we assign the device to a
* specific bus instead of the first bus with spare scsi ids.
*
* Ditch the calculated value and reload from option string (if
* specified).
*/
dinfo->unit = qemu_opt_get_number(dinfo->opts, "unit", -1);
dinfo->bus = scsibus->busnr;
scsidev = scsi_bus_legacy_add_drive(scsibus, dinfo->bdrv, dinfo->unit,
false, -1);
if (!scsidev) {
return -1;
}
dinfo->unit = scsidev->id;
if (printinfo)
monitor_printf(mon, "OK bus %d, unit %d\n",
scsibus->busnr, scsidev->id);
return 0;
}
XenBlockDataPlane *xen_block_dataplane_create(XenDevice *xendev,
BlockConf *conf,
IOThread *iothread)
{
XenBlockDataPlane *dataplane = g_new0(XenBlockDataPlane, 1);
dataplane->xendev = xendev;
dataplane->blk = conf->blk;
QLIST_INIT(&dataplane->inflight);
QLIST_INIT(&dataplane->freelist);
if (iothread) {
dataplane->iothread = iothread;
object_ref(OBJECT(dataplane->iothread));
dataplane->ctx = iothread_get_aio_context(dataplane->iothread);
} else {
dataplane->ctx = qemu_get_aio_context();
}
dataplane->bh = aio_bh_new(dataplane->ctx, xen_block_dataplane_bh,
dataplane);
return dataplane;
}
static void ipi_realize(DeviceState *dev, Error **errp)
{
IPI *s = XILINX_IPI(dev);
const char *prefix = object_get_canonical_path(OBJECT(dev));
unsigned int i;
for (i = 0; i < ARRAY_SIZE(ipi_regs_info); ++i) {
DepRegisterInfo *r = &s->regs_info[ipi_regs_info[i].decode.addr/4];
*r = (DepRegisterInfo) {
.data = (uint8_t *)&s->regs[
ipi_regs_info[i].decode.addr/4],
.data_size = sizeof(uint32_t),
.access = &ipi_regs_info[i],
.debug = XILINX_IPI_ERR_DEBUG,
.prefix = prefix,
.opaque = s,
};
dep_register_init(r);
qdev_pass_all_gpios(DEVICE(r), dev);
}
qdev_init_gpio_in_named(dev, ipi_handler, "IPI_INPUTS", 32);
qdev_init_gpio_in_named(dev, obs_handler, "OBS_INPUTS", 32);
}
static void ipi_init(Object *obj)
{
IPI *s = XILINX_IPI(obj);
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
memory_region_init_io(&s->iomem, obj, &ipi_ops, s,
TYPE_XILINX_IPI, R_MAX * 4);
sysbus_init_mmio(sbd, &s->iomem);
sysbus_init_irq(sbd, &s->irq);
}
void cgraphics_label_widget_create( widget_t *widget )
{
object_t *object = (object_t *)widget;
widget_t *parent = (widget_t *)object->parent;
HWND hwnd, hwnd_parent = widget_get_container(OBJECT(parent));
/* FIXME: bad default */
if ( widget->size_req->h == -1 )
widget->size_req->h = 25;
if ( !( hwnd = CreateWindowEx( 0, "STATIC",
"",
WS_CHILD | SS_LEFTNOWORDWRAP,
widget->size_req->x, widget->size_req->y,
widget->size_req->w, widget->size_req->h,
hwnd_parent,
NULL, (HINSTANCE) GetModuleHandle( NULL ), NULL ) ) )
MessageBox( 0, "Could not create label HWND.", "Claro error", 0 );
widget->native = hwnd;
ShowWindow( hwnd, SW_SHOW );
UpdateWindow( hwnd );
}
static void sysbus_esp_realize(DeviceState *dev, Error **errp)
{
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
SysBusESPState *sysbus = ESP(dev);
ESPState *s = &sysbus->esp;
Error *err = NULL;
sysbus_init_irq(sbd, &s->irq);
assert(sysbus->it_shift != -1);
s->chip_id = TCHI_FAS100A;
memory_region_init_io(&sysbus->iomem, OBJECT(sysbus), &sysbus_esp_mem_ops,
sysbus, "esp", ESP_REGS << sysbus->it_shift);
sysbus_init_mmio(sbd, &sysbus->iomem);
qdev_init_gpio_in(dev, sysbus_esp_gpio_demux, 2);
scsi_bus_new(&s->bus, sizeof(s->bus), dev, &esp_scsi_info, NULL);
scsi_bus_legacy_handle_cmdline(&s->bus, &err);
if (err != NULL) {
error_propagate(errp, err);
return;
}
}
static void tcp_chr_tls_init(Chardev *chr)
{
SocketChardev *s = SOCKET_CHARDEV(chr);
QIOChannelTLS *tioc;
Error *err = NULL;
gchar *name;
if (s->is_listen) {
tioc = qio_channel_tls_new_server(
s->ioc, s->tls_creds,
NULL, /* XXX Use an ACL */
&err);
} else {
tioc = qio_channel_tls_new_client(
s->ioc, s->tls_creds,
s->addr->u.inet.data->host,
&err);
}
if (tioc == NULL) {
error_free(err);
tcp_chr_disconnect(chr);
return;
}
name = g_strdup_printf("chardev-tls-%s-%s",
s->is_listen ? "server" : "client",
chr->label);
qio_channel_set_name(QIO_CHANNEL(tioc), name);
g_free(name);
object_unref(OBJECT(s->ioc));
s->ioc = QIO_CHANNEL(tioc);
qio_channel_tls_handshake(tioc,
tcp_chr_tls_handshake,
chr,
NULL);
}
static void spapr_cpu_core_realize_child(Object *child,
sPAPRMachineState *spapr, Error **errp)
{
Error *local_err = NULL;
CPUState *cs = CPU(child);
PowerPCCPU *cpu = POWERPC_CPU(cs);
Object *obj;
object_property_set_bool(child, true, "realized", &local_err);
if (local_err) {
goto error;
}
spapr_cpu_init(spapr, cpu, &local_err);
if (local_err) {
goto error;
}
obj = object_new(spapr->icp_type);
object_property_add_child(child, "icp", obj, &error_abort);
object_unref(obj);
object_property_add_const_link(obj, ICP_PROP_XICS, OBJECT(spapr),
&error_abort);
object_property_add_const_link(obj, ICP_PROP_CPU, child, &error_abort);
object_property_set_bool(obj, true, "realized", &local_err);
if (local_err) {
goto free_icp;
}
return;
free_icp:
object_unparent(obj);
error:
error_propagate(errp, local_err);
}
int main(int argc, char *argv[])
{
image_t * img;
object_t * menu;
list_item_t * quit_item;
claro_base_init();
claro_graphics_init();
log_fd_set_level(CL_DEBUG, stderr);
clog(CL_INFO, "%s running using Claro!", __FILE__);
w = window_widget_create(0, new_bounds(100, 100, 230, 230), 0);
object_addhandler(w, "destroy", window_closed);
window_set_title(w, "Status Icon");
menu = menu_widget_create(w, 0);
quit_item = menu_append_item(menu, NULL, stock_get_image("system-log-out"), "Quit");
object_addhandler(OBJECT(quit_item), "pushed", window_closed);
img = image_load(w, "icon.png");
s = status_icon_create(w, img, 0);
status_icon_set_tooltip(s, "Claro - Status Icon");
status_icon_set_menu(s, menu);
object_addhandler(s, "pushed", status_icon_pushed);
window_show(w);
window_focus(w);
block_heap_loginfo();
claro_loop();
return 0;
}
/* Version of DispatchOrEval for "[" and friends that speeds up simple cases.
Also defined in subassign.c */
static R_INLINE
int R_DispatchOrEvalSP(SEXP call, SEXP op, const char *generic, SEXP args,
SEXP rho, SEXP *ans)
{
SEXP prom = NULL;
if (args != R_NilValue && CAR(args) != R_DotsSymbol) {
SEXP x = eval(CAR(args), rho);
PROTECT(x);
if (! OBJECT(x)) {
*ans = CONS_NR(x, evalListKeepMissing(CDR(args), rho));
UNPROTECT(1);
return FALSE;
}
prom = mkPROMISE(CAR(args), R_GlobalEnv);
SET_PRVALUE(prom, x);
args = CONS(prom, CDR(args));
UNPROTECT(1);
}
PROTECT(args);
int disp = DispatchOrEval(call, op, generic, args, rho, ans, 0, 0);
if (prom) DECREMENT_REFCNT(PRVALUE(prom));
UNPROTECT(1);
return disp;
}
static int nvram_sysbus_initfn(SysBusDevice *dev)
{
NvRamState *s = &FROM_SYSBUS(SysBusNvRamState, dev)->nvram;
FILE *file;
s->contents = g_malloc0(s->chip_size);
memory_region_init_io(&s->iomem, OBJECT(s), &nvram_ops, s,
"nvram", s->chip_size);
sysbus_init_mmio(dev, &s->iomem);
/* Read current file */
file = fopen(s->filename, "rb");
if (file) {
/* Read nvram contents */
if (fread(s->contents, s->chip_size, 1, file) != 1) {
printf("nvram_sysbus_initfn: short read\n");
}
fclose(file);
}
nvram_post_load(s, 0);
return 0;
}
/*
* Implementation of an interface to adjust firmware path
* for the bootindex property handling.
*/
static char *heathrow_fw_dev_path(FWPathProvider *p, BusState *bus,
DeviceState *dev)
{
PCIDevice *pci;
IDEBus *ide_bus;
IDEState *ide_s;
MACIOIDEState *macio_ide;
if (!strcmp(object_get_typename(OBJECT(dev)), "macio-oldworld")) {
pci = PCI_DEVICE(dev);
return g_strdup_printf("mac-io@%x", PCI_SLOT(pci->devfn));
}
if (!strcmp(object_get_typename(OBJECT(dev)), "macio-ide")) {
macio_ide = MACIO_IDE(dev);
return g_strdup_printf("ata-3@%x", macio_ide->addr);
}
if (!strcmp(object_get_typename(OBJECT(dev)), "ide-drive")) {
ide_bus = IDE_BUS(qdev_get_parent_bus(dev));
ide_s = idebus_active_if(ide_bus);
if (ide_s->drive_kind == IDE_CD) {
return g_strdup("cdrom");
}
return g_strdup("disk");
}
if (!strcmp(object_get_typename(OBJECT(dev)), "ide-hd")) {
return g_strdup("disk");
}
if (!strcmp(object_get_typename(OBJECT(dev)), "ide-cd")) {
return g_strdup("cdrom");
}
if (!strcmp(object_get_typename(OBJECT(dev)), "virtio-blk-device")) {
return g_strdup("disk");
}
return NULL;
}
static int ppc440_pcix_initfn(SysBusDevice *dev)
{
PPC440PCIXState *s;
PCIHostState *h;
int i;
h = PCI_HOST_BRIDGE(dev);
s = PPC440_PCIX_HOST_BRIDGE(dev);
for (i = 0; i < ARRAY_SIZE(s->irq); i++) {
sysbus_init_irq(dev, &s->irq[i]);
}
memory_region_init(&s->busmem, OBJECT(dev), "pci bus memory", UINT64_MAX);
h->bus = pci_register_root_bus(DEVICE(dev), NULL, ppc440_pcix_set_irq,
ppc440_pcix_map_irq, s->irq, &s->busmem,
get_system_io(), PCI_DEVFN(0, 0), 4, TYPE_PCI_BUS);
s->dev = pci_create_simple(h->bus, PCI_DEVFN(0, 0), "ppc4xx-host-bridge");
memory_region_init(&s->bm, OBJECT(s), "bm-ppc440-pcix", UINT64_MAX);
memory_region_add_subregion(&s->bm, 0x0, &s->busmem);
address_space_init(&s->bm_as, &s->bm, "pci-bm");
pci_setup_iommu(h->bus, ppc440_pcix_set_iommu, s);
memory_region_init(&s->container, OBJECT(s), "pci-container", PCI_ALL_SIZE);
memory_region_init_io(&h->conf_mem, OBJECT(s), &pci_host_conf_le_ops,
h, "pci-conf-idx", 4);
memory_region_init_io(&h->data_mem, OBJECT(s), &ppc440_pcix_host_data_ops,
h, "pci-conf-data", 4);
memory_region_init_io(&s->iomem, OBJECT(s), &pci_reg_ops, s,
"pci.reg", PPC440_REG_SIZE);
memory_region_add_subregion(&s->container, PCIC0_CFGADDR, &h->conf_mem);
memory_region_add_subregion(&s->container, PCIC0_CFGDATA, &h->data_mem);
memory_region_add_subregion(&s->container, PPC440_REG_BASE, &s->iomem);
sysbus_init_mmio(dev, &s->container);
return 0;
}
static void ppc_heathrow_init(QEMUMachineInitArgs *args)
{
ram_addr_t ram_size = args->ram_size;
const char *cpu_model = args->cpu_model;
const char *kernel_filename = args->kernel_filename;
const char *kernel_cmdline = args->kernel_cmdline;
const char *initrd_filename = args->initrd_filename;
const char *boot_device = args->boot_device;
MemoryRegion *sysmem = get_system_memory();
PowerPCCPU *cpu = NULL;
CPUPPCState *env = NULL;
char *filename;
qemu_irq *pic, **heathrow_irqs;
int linux_boot, i;
MemoryRegion *ram = g_new(MemoryRegion, 1);
MemoryRegion *bios = g_new(MemoryRegion, 1);
uint32_t kernel_base, initrd_base, cmdline_base = 0;
int32_t kernel_size, initrd_size;
PCIBus *pci_bus;
PCIDevice *macio;
MACIOIDEState *macio_ide;
DeviceState *dev;
BusState *adb_bus;
int bios_size;
MemoryRegion *pic_mem;
MemoryRegion *escc_mem, *escc_bar = g_new(MemoryRegion, 1);
uint16_t ppc_boot_device;
DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
void *fw_cfg;
linux_boot = (kernel_filename != NULL);
/* init CPUs */
if (cpu_model == NULL)
cpu_model = "G3";
for (i = 0; i < smp_cpus; i++) {
cpu = cpu_ppc_init(cpu_model);
if (cpu == NULL) {
fprintf(stderr, "Unable to find PowerPC CPU definition\n");
exit(1);
}
env = &cpu->env;
/* Set time-base frequency to 16.6 Mhz */
cpu_ppc_tb_init(env, 16600000UL);
qemu_register_reset(ppc_heathrow_reset, cpu);
}
/* allocate RAM */
if (ram_size > (2047 << 20)) {
fprintf(stderr,
"qemu: Too much memory for this machine: %d MB, maximum 2047 MB\n",
((unsigned int)ram_size / (1 << 20)));
exit(1);
}
memory_region_init_ram(ram, "ppc_heathrow.ram", ram_size);
vmstate_register_ram_global(ram);
memory_region_add_subregion(sysmem, 0, ram);
/* allocate and load BIOS */
memory_region_init_ram(bios, "ppc_heathrow.bios", BIOS_SIZE);
vmstate_register_ram_global(bios);
if (bios_name == NULL)
bios_name = PROM_FILENAME;
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
memory_region_set_readonly(bios, true);
memory_region_add_subregion(sysmem, PROM_ADDR, bios);
/* Load OpenBIOS (ELF) */
if (filename) {
bios_size = load_elf(filename, 0, NULL, NULL, NULL, NULL,
1, ELF_MACHINE, 0);
g_free(filename);
} else {
bios_size = -1;
}
if (bios_size < 0 || bios_size > BIOS_SIZE) {
hw_error("qemu: could not load PowerPC bios '%s'\n", bios_name);
exit(1);
}
if (linux_boot) {
uint64_t lowaddr = 0;
int bswap_needed;
#ifdef BSWAP_NEEDED
bswap_needed = 1;
#else
bswap_needed = 0;
#endif
kernel_base = KERNEL_LOAD_ADDR;
kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
NULL, &lowaddr, NULL, 1, ELF_MACHINE, 0);
if (kernel_size < 0)
kernel_size = load_aout(kernel_filename, kernel_base,
ram_size - kernel_base, bswap_needed,
TARGET_PAGE_SIZE);
if (kernel_size < 0)
kernel_size = load_image_targphys(kernel_filename,
kernel_base,
ram_size - kernel_base);
if (kernel_size < 0) {
hw_error("qemu: could not load kernel '%s'\n",
kernel_filename);
exit(1);
}
/* load initrd */
if (initrd_filename) {
initrd_base = round_page(kernel_base + kernel_size + KERNEL_GAP);
initrd_size = load_image_targphys(initrd_filename, initrd_base,
ram_size - initrd_base);
if (initrd_size < 0) {
hw_error("qemu: could not load initial ram disk '%s'\n",
initrd_filename);
exit(1);
}
cmdline_base = round_page(initrd_base + initrd_size);
} else {
initrd_base = 0;
initrd_size = 0;
cmdline_base = round_page(kernel_base + kernel_size + KERNEL_GAP);
}
ppc_boot_device = 'm';
} else {
kernel_base = 0;
kernel_size = 0;
initrd_base = 0;
initrd_size = 0;
ppc_boot_device = '\0';
for (i = 0; boot_device[i] != '\0'; i++) {
/* TOFIX: for now, the second IDE channel is not properly
* used by OHW. The Mac floppy disk are not emulated.
* For now, OHW cannot boot from the network.
*/
#if 0
if (boot_device[i] >= 'a' && boot_device[i] <= 'f') {
ppc_boot_device = boot_device[i];
break;
}
#else
if (boot_device[i] >= 'c' && boot_device[i] <= 'd') {
ppc_boot_device = boot_device[i];
break;
}
#endif
}
if (ppc_boot_device == '\0') {
fprintf(stderr, "No valid boot device for G3 Beige machine\n");
exit(1);
}
}
/* Register 2 MB of ISA IO space */
isa_mmio_init(0xfe000000, 0x00200000);
/* XXX: we register only 1 output pin for heathrow PIC */
heathrow_irqs = g_malloc0(smp_cpus * sizeof(qemu_irq *));
heathrow_irqs[0] =
g_malloc0(smp_cpus * sizeof(qemu_irq) * 1);
/* Connect the heathrow PIC outputs to the 6xx bus */
for (i = 0; i < smp_cpus; i++) {
switch (PPC_INPUT(env)) {
case PPC_FLAGS_INPUT_6xx:
heathrow_irqs[i] = heathrow_irqs[0] + (i * 1);
heathrow_irqs[i][0] =
((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT];
break;
default:
hw_error("Bus model not supported on OldWorld Mac machine\n");
}
}
/* init basic PC hardware */
if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
hw_error("Only 6xx bus is supported on heathrow machine\n");
}
pic = heathrow_pic_init(&pic_mem, 1, heathrow_irqs);
pci_bus = pci_grackle_init(0xfec00000, pic,
get_system_memory(),
get_system_io());
pci_vga_init(pci_bus);
escc_mem = escc_init(0, pic[0x0f], pic[0x10], serial_hds[0],
serial_hds[1], ESCC_CLOCK, 4);
memory_region_init_alias(escc_bar, "escc-bar",
escc_mem, 0, memory_region_size(escc_mem));
for(i = 0; i < nb_nics; i++)
pci_nic_init_nofail(&nd_table[i], "ne2k_pci", NULL);
ide_drive_get(hd, MAX_IDE_BUS);
macio = pci_create(pci_bus, -1, TYPE_OLDWORLD_MACIO);
dev = DEVICE(macio);
qdev_connect_gpio_out(dev, 0, pic[0x12]); /* CUDA */
qdev_connect_gpio_out(dev, 1, pic[0x0D]); /* IDE */
qdev_connect_gpio_out(dev, 2, pic[0x02]); /* IDE DMA */
macio_init(macio, pic_mem, escc_bar);
/* First IDE channel is a MAC IDE on the MacIO bus */
macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio),
"ide"));
macio_ide_init_drives(macio_ide, hd);
/* Second IDE channel is a CMD646 on the PCI bus */
hd[0] = hd[MAX_IDE_DEVS];
hd[1] = hd[MAX_IDE_DEVS + 1];
hd[3] = hd[2] = NULL;
pci_cmd646_ide_init(pci_bus, hd, 0);
dev = DEVICE(object_resolve_path_component(OBJECT(macio), "cuda"));
adb_bus = qdev_get_child_bus(dev, "adb.0");
dev = qdev_create(adb_bus, TYPE_ADB_KEYBOARD);
qdev_init_nofail(dev);
dev = qdev_create(adb_bus, TYPE_ADB_MOUSE);
qdev_init_nofail(dev);
if (usb_enabled(false)) {
pci_create_simple(pci_bus, -1, "pci-ohci");
}
if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8)
graphic_depth = 15;
/* No PCI init: the BIOS will do it */
fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, ARCH_HEATHROW);
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base);
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
if (kernel_cmdline) {
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, cmdline_base);
pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE, kernel_cmdline);
} else {
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
}
fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base);
fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ppc_boot_device);
fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width);
fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height);
fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth);
fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled());
if (kvm_enabled()) {
#ifdef CONFIG_KVM
uint8_t *hypercall;
fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, kvmppc_get_tbfreq());
hypercall = g_malloc(16);
kvmppc_get_hypercall(env, hypercall, 16);
fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16);
fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid());
#endif
} else {
fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, get_ticks_per_sec());
}
qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
}
void HrcDumper_destroy(HrcDumper_ptr self)
{
HRC_DUMPER_CHECK_INSTANCE(self);
Object_destroy(OBJECT(self), NULL);
}
static void
petalogix_ml605_init(MachineState *machine)
{
ram_addr_t ram_size = machine->ram_size;
MemoryRegion *address_space_mem = get_system_memory();
DeviceState *dev, *dma, *eth0;
Object *ds, *cs;
MicroBlazeCPU *cpu;
SysBusDevice *busdev;
DriveInfo *dinfo;
int i;
MemoryRegion *phys_lmb_bram = g_new(MemoryRegion, 1);
MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
qemu_irq irq[32];
/* init CPUs */
cpu = MICROBLAZE_CPU(object_new(TYPE_MICROBLAZE_CPU));
object_property_set_str(OBJECT(cpu), "8.10.a", "version", &error_abort);
/* Use FPU but don't use floating point conversion and square
* root instructions
*/
object_property_set_int(OBJECT(cpu), 1, "use-fpu", &error_abort);
object_property_set_bool(OBJECT(cpu), true, "dcache-writeback",
&error_abort);
object_property_set_bool(OBJECT(cpu), true, "endianness", &error_abort);
object_property_set_bool(OBJECT(cpu), true, "realized", &error_abort);
/* Attach emulated BRAM through the LMB. */
memory_region_init_ram(phys_lmb_bram, NULL, "petalogix_ml605.lmb_bram",
LMB_BRAM_SIZE, &error_fatal);
vmstate_register_ram_global(phys_lmb_bram);
memory_region_add_subregion(address_space_mem, 0x00000000, phys_lmb_bram);
memory_region_init_ram(phys_ram, NULL, "petalogix_ml605.ram", ram_size,
&error_fatal);
vmstate_register_ram_global(phys_ram);
memory_region_add_subregion(address_space_mem, MEMORY_BASEADDR, phys_ram);
dinfo = drive_get(IF_PFLASH, 0, 0);
/* 5th parameter 2 means bank-width
* 10th paremeter 0 means little-endian */
pflash_cfi01_register(FLASH_BASEADDR,
NULL, "petalogix_ml605.flash", FLASH_SIZE,
dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
(64 * 1024), FLASH_SIZE >> 16,
2, 0x89, 0x18, 0x0000, 0x0, 0);
dev = qdev_create(NULL, "xlnx.xps-intc");
qdev_prop_set_uint32(dev, "kind-of-intr", 1 << TIMER_IRQ);
qdev_init_nofail(dev);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, INTC_BASEADDR);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,
qdev_get_gpio_in(DEVICE(cpu), MB_CPU_IRQ));
for (i = 0; i < 32; i++) {
irq[i] = qdev_get_gpio_in(dev, i);
}
serial_mm_init(address_space_mem, UART16550_BASEADDR + 0x1000, 2,
irq[UART16550_IRQ], 115200, serial_hds[0],
DEVICE_LITTLE_ENDIAN);
/* 2 timers at irq 2 @ 100 Mhz. */
dev = qdev_create(NULL, "xlnx.xps-timer");
qdev_prop_set_uint32(dev, "one-timer-only", 0);
qdev_prop_set_uint32(dev, "clock-frequency", 100 * 1000000);
qdev_init_nofail(dev);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, TIMER_BASEADDR);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[TIMER_IRQ]);
/* axi ethernet and dma initialization. */
qemu_check_nic_model(&nd_table[0], "xlnx.axi-ethernet");
eth0 = qdev_create(NULL, "xlnx.axi-ethernet");
dma = qdev_create(NULL, "xlnx.axi-dma");
/* FIXME: attach to the sysbus instead */
object_property_add_child(qdev_get_machine(), "xilinx-eth", OBJECT(eth0),
NULL);
object_property_add_child(qdev_get_machine(), "xilinx-dma", OBJECT(dma),
NULL);
ds = object_property_get_link(OBJECT(dma),
"axistream-connected-target", NULL);
cs = object_property_get_link(OBJECT(dma),
"axistream-control-connected-target", NULL);
qdev_set_nic_properties(eth0, &nd_table[0]);
qdev_prop_set_uint32(eth0, "rxmem", 0x1000);
qdev_prop_set_uint32(eth0, "txmem", 0x1000);
object_property_set_link(OBJECT(eth0), OBJECT(ds),
"axistream-connected", &error_abort);
object_property_set_link(OBJECT(eth0), OBJECT(cs),
"axistream-control-connected", &error_abort);
qdev_init_nofail(eth0);
sysbus_mmio_map(SYS_BUS_DEVICE(eth0), 0, AXIENET_BASEADDR);
sysbus_connect_irq(SYS_BUS_DEVICE(eth0), 0, irq[AXIENET_IRQ]);
ds = object_property_get_link(OBJECT(eth0),
"axistream-connected-target", NULL);
cs = object_property_get_link(OBJECT(eth0),
"axistream-control-connected-target", NULL);
qdev_prop_set_uint32(dma, "freqhz", 100 * 1000000);
object_property_set_link(OBJECT(dma), OBJECT(ds),
"axistream-connected", &error_abort);
object_property_set_link(OBJECT(dma), OBJECT(cs),
"axistream-control-connected", &error_abort);
qdev_init_nofail(dma);
sysbus_mmio_map(SYS_BUS_DEVICE(dma), 0, AXIDMA_BASEADDR);
sysbus_connect_irq(SYS_BUS_DEVICE(dma), 0, irq[AXIDMA_IRQ0]);
sysbus_connect_irq(SYS_BUS_DEVICE(dma), 1, irq[AXIDMA_IRQ1]);
{
SSIBus *spi;
dev = qdev_create(NULL, "xlnx.xps-spi");
qdev_prop_set_uint8(dev, "num-ss-bits", NUM_SPI_FLASHES);
qdev_init_nofail(dev);
busdev = SYS_BUS_DEVICE(dev);
sysbus_mmio_map(busdev, 0, SPI_BASEADDR);
sysbus_connect_irq(busdev, 0, irq[SPI_IRQ]);
spi = (SSIBus *)qdev_get_child_bus(dev, "spi");
for (i = 0; i < NUM_SPI_FLASHES; i++) {
qemu_irq cs_line;
dev = ssi_create_slave(spi, "n25q128");
cs_line = qdev_get_gpio_in_named(dev, SSI_GPIO_CS, 0);
sysbus_connect_irq(busdev, i+1, cs_line);
}
}
/* setup PVR to match kernel settings */
cpu->env.pvr.regs[4] = 0xc56b8000;
cpu->env.pvr.regs[5] = 0xc56be000;
cpu->env.pvr.regs[10] = 0x0e000000; /* virtex 6 */
microblaze_load_kernel(cpu, MEMORY_BASEADDR, ram_size,
machine->initrd_filename,
BINARY_DEVICE_TREE_FILE,
NULL);
}
/* PC hardware initialisation */
static void pc_init1(QEMUMachineInitArgs *args,
int pci_enabled,
int kvmclock_enabled)
{
MemoryRegion *system_memory = get_system_memory();
MemoryRegion *system_io = get_system_io();
int i;
ram_addr_t below_4g_mem_size, above_4g_mem_size;
PCIBus *pci_bus;
ISABus *isa_bus;
PCII440FXState *i440fx_state;
int piix3_devfn = -1;
qemu_irq *cpu_irq;
qemu_irq *gsi;
qemu_irq *i8259;
qemu_irq *smi_irq;
GSIState *gsi_state;
DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
BusState *idebus[MAX_IDE_BUS];
ISADevice *rtc_state;
ISADevice *floppy;
MemoryRegion *ram_memory;
MemoryRegion *pci_memory;
MemoryRegion *rom_memory;
DeviceState *icc_bridge;
FWCfgState *fw_cfg = NULL;
PcGuestInfo *guest_info;
if (xen_enabled() && xen_hvm_init(&ram_memory) != 0) {
fprintf(stderr, "xen hardware virtual machine initialisation failed\n");
exit(1);
}
icc_bridge = qdev_create(NULL, TYPE_ICC_BRIDGE);
object_property_add_child(qdev_get_machine(), "icc-bridge",
OBJECT(icc_bridge), NULL);
pc_cpus_init(args->cpu_model, icc_bridge);
if (kvm_enabled() && kvmclock_enabled) {
kvmclock_create();
}
/* Check whether RAM fits below 4G (leaving 1/2 GByte for IO memory).
* If it doesn't, we need to split it in chunks below and above 4G.
* In any case, try to make sure that guest addresses aligned at
* 1G boundaries get mapped to host addresses aligned at 1G boundaries.
* For old machine types, use whatever split we used historically to avoid
* breaking migration.
*/
if (args->ram_size >= 0xe0000000) {
ram_addr_t lowmem = gigabyte_align ? 0xc0000000 : 0xe0000000;
above_4g_mem_size = args->ram_size - lowmem;
below_4g_mem_size = lowmem;
} else {
above_4g_mem_size = 0;
below_4g_mem_size = args->ram_size;
}
if (pci_enabled) {
pci_memory = g_new(MemoryRegion, 1);
memory_region_init(pci_memory, NULL, "pci", UINT64_MAX);
rom_memory = pci_memory;
} else {
pci_memory = NULL;
rom_memory = system_memory;
}
guest_info = pc_guest_info_init(below_4g_mem_size, above_4g_mem_size);
guest_info->has_acpi_build = has_acpi_build;
guest_info->has_pci_info = has_pci_info;
guest_info->isapc_ram_fw = !pci_enabled;
if (smbios_type1_defaults) {
/* These values are guest ABI, do not change */
smbios_set_type1_defaults("QEMU", "Standard PC (i440FX + PIIX, 1996)",
args->machine->name);
}
/* allocate ram and load rom/bios */
if (!xen_enabled()) {
fw_cfg = pc_memory_init(system_memory,
args->kernel_filename, args->kernel_cmdline,
args->initrd_filename,
below_4g_mem_size, above_4g_mem_size,
rom_memory, &ram_memory, guest_info);
}
gsi_state = g_malloc0(sizeof(*gsi_state));
if (kvm_irqchip_in_kernel()) {
kvm_pc_setup_irq_routing(pci_enabled);
gsi = qemu_allocate_irqs(kvm_pc_gsi_handler, gsi_state,
GSI_NUM_PINS);
} else {
gsi = qemu_allocate_irqs(gsi_handler, gsi_state, GSI_NUM_PINS);
}
if (pci_enabled) {
pci_bus = i440fx_init(&i440fx_state, &piix3_devfn, &isa_bus, gsi,
system_memory, system_io, args->ram_size,
below_4g_mem_size,
above_4g_mem_size,
pci_memory, ram_memory);
} else {
pci_bus = NULL;
i440fx_state = NULL;
isa_bus = isa_bus_new(NULL, system_io);
no_hpet = 1;
}
isa_bus_irqs(isa_bus, gsi);
if (kvm_irqchip_in_kernel()) {
i8259 = kvm_i8259_init(isa_bus);
} else if (xen_enabled()) {
i8259 = xen_interrupt_controller_init();
} else {
cpu_irq = pc_allocate_cpu_irq();
i8259 = i8259_init(isa_bus, cpu_irq[0]);
}
for (i = 0; i < ISA_NUM_IRQS; i++) {
gsi_state->i8259_irq[i] = i8259[i];
}
if (pci_enabled) {
ioapic_init_gsi(gsi_state, "i440fx");
}
qdev_init_nofail(icc_bridge);
pc_register_ferr_irq(gsi[13]);
pc_vga_init(isa_bus, pci_enabled ? pci_bus : NULL);
/* init basic PC hardware */
pc_basic_device_init(isa_bus, gsi, &rtc_state, &floppy, xen_enabled(),
0x4);
pc_nic_init(isa_bus, pci_bus);
ide_drive_get(hd, MAX_IDE_BUS);
if (pci_enabled) {
PCIDevice *dev;
if (xen_enabled()) {
dev = pci_piix3_xen_ide_init(pci_bus, hd, piix3_devfn + 1);
} else {
dev = pci_piix3_ide_init(pci_bus, hd, piix3_devfn + 1);
}
idebus[0] = qdev_get_child_bus(&dev->qdev, "ide.0");
idebus[1] = qdev_get_child_bus(&dev->qdev, "ide.1");
} else {
for(i = 0; i < MAX_IDE_BUS; i++) {
ISADevice *dev;
dev = isa_ide_init(isa_bus, ide_iobase[i], ide_iobase2[i],
ide_irq[i],
hd[MAX_IDE_DEVS * i], hd[MAX_IDE_DEVS * i + 1]);
idebus[i] = qdev_get_child_bus(DEVICE(dev), "ide.0");
}
}
pc_cmos_init(below_4g_mem_size, above_4g_mem_size, args->boot_order,
floppy, idebus[0], idebus[1], rtc_state);
if (pci_enabled && usb_enabled(false)) {
pci_create_simple(pci_bus, piix3_devfn + 2, "piix3-usb-uhci");
}
if (pci_enabled && acpi_enabled) {
I2CBus *smbus;
smi_irq = qemu_allocate_irqs(pc_acpi_smi_interrupt, first_cpu, 1);
/* TODO: Populate SPD eeprom data. */
smbus = piix4_pm_init(pci_bus, piix3_devfn + 3, 0xb100,
gsi[9], *smi_irq,
kvm_enabled(), fw_cfg);
smbus_eeprom_init(smbus, 8, NULL, 0);
}
if (pci_enabled) {
pc_pci_device_init(pci_bus);
}
}
void pc_dimm_memory_plug(DeviceState *dev, MemoryHotplugState *hpms,
MemoryRegion *mr, uint64_t align, Error **errp)
{
int slot;
MachineState *machine = MACHINE(qdev_get_machine());
PCDIMMDevice *dimm = PC_DIMM(dev);
PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
MemoryRegion *vmstate_mr = ddc->get_vmstate_memory_region(dimm);
Error *local_err = NULL;
uint64_t existing_dimms_capacity = 0;
uint64_t addr;
addr = object_property_get_uint(OBJECT(dimm),
PC_DIMM_ADDR_PROP, &local_err);
if (local_err) {
goto out;
}
addr = pc_dimm_get_free_addr(hpms->base,
memory_region_size(&hpms->mr),
!addr ? NULL : &addr, align,
memory_region_size(mr), &local_err);
if (local_err) {
goto out;
}
existing_dimms_capacity = pc_existing_dimms_capacity(&local_err);
if (local_err) {
goto out;
}
if (existing_dimms_capacity + memory_region_size(mr) >
machine->maxram_size - machine->ram_size) {
error_setg(&local_err, "not enough space, currently 0x%" PRIx64
" in use of total hot pluggable 0x" RAM_ADDR_FMT,
existing_dimms_capacity,
machine->maxram_size - machine->ram_size);
goto out;
}
object_property_set_uint(OBJECT(dev), addr, PC_DIMM_ADDR_PROP, &local_err);
if (local_err) {
goto out;
}
trace_mhp_pc_dimm_assigned_address(addr);
slot = object_property_get_int(OBJECT(dev), PC_DIMM_SLOT_PROP, &local_err);
if (local_err) {
goto out;
}
slot = pc_dimm_get_free_slot(slot == PC_DIMM_UNASSIGNED_SLOT ? NULL : &slot,
machine->ram_slots, &local_err);
if (local_err) {
goto out;
}
object_property_set_int(OBJECT(dev), slot, PC_DIMM_SLOT_PROP, &local_err);
if (local_err) {
goto out;
}
trace_mhp_pc_dimm_assigned_slot(slot);
if (kvm_enabled() && !kvm_has_free_slot(machine)) {
error_setg(&local_err, "hypervisor has no free memory slots left");
goto out;
}
if (!vhost_has_free_slot()) {
error_setg(&local_err, "a used vhost backend has no free"
" memory slots left");
goto out;
}
memory_region_add_subregion(&hpms->mr, addr - hpms->base, mr);
vmstate_register_ram(vmstate_mr, dev);
numa_set_mem_node_id(addr, memory_region_size(mr), dimm->node);
out:
error_propagate(errp, local_err);
}
static int error_on_sysbus_device(SysBusDevice *sbdev, void *opaque)
{
error_report("Option '-device %s' cannot be handled by this machine",
object_class_get_name(object_get_class(OBJECT(sbdev))));
exit(1);
}
static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
{
STM32F205State *s = STM32F205_SOC(dev_soc);
DeviceState *syscfgdev, *usartdev, *timerdev, *nvic;
SysBusDevice *syscfgbusdev, *usartbusdev, *timerbusdev;
Error *err = NULL;
int i;
MemoryRegion *system_memory = get_system_memory();
MemoryRegion *sram = g_new(MemoryRegion, 1);
MemoryRegion *flash = g_new(MemoryRegion, 1);
MemoryRegion *flash_alias = g_new(MemoryRegion, 1);
memory_region_init_ram(flash, NULL, "STM32F205.flash", FLASH_SIZE,
&error_fatal);
memory_region_init_alias(flash_alias, NULL, "STM32F205.flash.alias",
flash, 0, FLASH_SIZE);
vmstate_register_ram_global(flash);
memory_region_set_readonly(flash, true);
memory_region_set_readonly(flash_alias, true);
memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, flash);
memory_region_add_subregion(system_memory, 0, flash_alias);
memory_region_init_ram(sram, NULL, "STM32F205.sram", SRAM_SIZE,
&error_fatal);
vmstate_register_ram_global(sram);
memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram);
nvic = armv7m_init(get_system_memory(), FLASH_SIZE, 96,
s->kernel_filename, s->cpu_model);
/* System configuration controller */
syscfgdev = DEVICE(&s->syscfg);
object_property_set_bool(OBJECT(&s->syscfg), true, "realized", &err);
if (err != NULL) {
error_propagate(errp, err);
return;
}
syscfgbusdev = SYS_BUS_DEVICE(syscfgdev);
sysbus_mmio_map(syscfgbusdev, 0, 0x40013800);
sysbus_connect_irq(syscfgbusdev, 0, qdev_get_gpio_in(nvic, 71));
/* Attach UART (uses USART registers) and USART controllers */
for (i = 0; i < STM_NUM_USARTS; i++) {
usartdev = DEVICE(&(s->usart[i]));
object_property_set_bool(OBJECT(&s->usart[i]), true, "realized", &err);
if (err != NULL) {
error_propagate(errp, err);
return;
}
usartbusdev = SYS_BUS_DEVICE(usartdev);
sysbus_mmio_map(usartbusdev, 0, usart_addr[i]);
sysbus_connect_irq(usartbusdev, 0,
qdev_get_gpio_in(nvic, usart_irq[i]));
}
/* Timer 2 to 5 */
for (i = 0; i < STM_NUM_TIMERS; i++) {
timerdev = DEVICE(&(s->timer[i]));
qdev_prop_set_uint64(timerdev, "clock-frequency", 1000000000);
object_property_set_bool(OBJECT(&s->timer[i]), true, "realized", &err);
if (err != NULL) {
error_propagate(errp, err);
return;
}
timerbusdev = SYS_BUS_DEVICE(timerdev);
sysbus_mmio_map(timerbusdev, 0, timer_addr[i]);
sysbus_connect_irq(timerbusdev, 0,
qdev_get_gpio_in(nvic, timer_irq[i]));
}
}
/* PowerPC Mac99 hardware initialisation */
static void ppc_core99_init(MachineState *machine)
{
ram_addr_t ram_size = machine->ram_size;
const char *kernel_filename = machine->kernel_filename;
const char *kernel_cmdline = machine->kernel_cmdline;
const char *initrd_filename = machine->initrd_filename;
const char *boot_device = machine->boot_order;
PowerPCCPU *cpu = NULL;
CPUPPCState *env = NULL;
char *filename;
qemu_irq *pic, **openpic_irqs;
MemoryRegion *isa = g_new(MemoryRegion, 1);
MemoryRegion *unin_memory = g_new(MemoryRegion, 1);
MemoryRegion *unin2_memory = g_new(MemoryRegion, 1);
int linux_boot, i, j, k;
MemoryRegion *ram = g_new(MemoryRegion, 1), *bios = g_new(MemoryRegion, 1);
hwaddr kernel_base, initrd_base, cmdline_base = 0;
long kernel_size, initrd_size;
PCIBus *pci_bus;
PCIDevice *macio;
MACIOIDEState *macio_ide;
BusState *adb_bus;
MacIONVRAMState *nvr;
int bios_size;
MemoryRegion *pic_mem, *escc_mem;
MemoryRegion *escc_bar = g_new(MemoryRegion, 1);
int ppc_boot_device;
DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
void *fw_cfg;
int machine_arch;
SysBusDevice *s;
DeviceState *dev;
int *token = g_new(int, 1);
hwaddr nvram_addr = 0xFFF04000;
uint64_t tbfreq;
linux_boot = (kernel_filename != NULL);
/* init CPUs */
if (machine->cpu_model == NULL) {
#ifdef TARGET_PPC64
machine->cpu_model = "970fx";
#else
machine->cpu_model = "G4";
#endif
}
for (i = 0; i < smp_cpus; i++) {
cpu = cpu_ppc_init(machine->cpu_model);
if (cpu == NULL) {
fprintf(stderr, "Unable to find PowerPC CPU definition\n");
exit(1);
}
env = &cpu->env;
/* Set time-base frequency to 100 Mhz */
cpu_ppc_tb_init(env, TBFREQ);
qemu_register_reset(ppc_core99_reset, cpu);
}
/* allocate RAM */
memory_region_allocate_system_memory(ram, NULL, "ppc_core99.ram", ram_size);
memory_region_add_subregion(get_system_memory(), 0, ram);
/* allocate and load BIOS */
memory_region_init_ram(bios, NULL, "ppc_core99.bios", BIOS_SIZE,
&error_fatal);
vmstate_register_ram_global(bios);
if (bios_name == NULL)
bios_name = PROM_FILENAME;
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
memory_region_set_readonly(bios, true);
memory_region_add_subregion(get_system_memory(), PROM_ADDR, bios);
/* Load OpenBIOS (ELF) */
if (filename) {
bios_size = load_elf(filename, NULL, NULL, NULL,
NULL, NULL, 1, PPC_ELF_MACHINE, 0);
g_free(filename);
} else {
bios_size = -1;
}
if (bios_size < 0 || bios_size > BIOS_SIZE) {
error_report("could not load PowerPC bios '%s'", bios_name);
exit(1);
}
if (linux_boot) {
uint64_t lowaddr = 0;
int bswap_needed;
#ifdef BSWAP_NEEDED
bswap_needed = 1;
#else
bswap_needed = 0;
#endif
kernel_base = KERNEL_LOAD_ADDR;
kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
NULL, &lowaddr, NULL, 1, PPC_ELF_MACHINE, 0);
if (kernel_size < 0)
kernel_size = load_aout(kernel_filename, kernel_base,
ram_size - kernel_base, bswap_needed,
TARGET_PAGE_SIZE);
if (kernel_size < 0)
kernel_size = load_image_targphys(kernel_filename,
kernel_base,
ram_size - kernel_base);
if (kernel_size < 0) {
error_report("could not load kernel '%s'", kernel_filename);
exit(1);
}
/* load initrd */
if (initrd_filename) {
initrd_base = round_page(kernel_base + kernel_size + KERNEL_GAP);
initrd_size = load_image_targphys(initrd_filename, initrd_base,
ram_size - initrd_base);
if (initrd_size < 0) {
error_report("could not load initial ram disk '%s'",
initrd_filename);
exit(1);
}
cmdline_base = round_page(initrd_base + initrd_size);
} else {
initrd_base = 0;
initrd_size = 0;
cmdline_base = round_page(kernel_base + kernel_size + KERNEL_GAP);
}
ppc_boot_device = 'm';
} else {
kernel_base = 0;
kernel_size = 0;
initrd_base = 0;
initrd_size = 0;
ppc_boot_device = '\0';
/* We consider that NewWorld PowerMac never have any floppy drive
* For now, OHW cannot boot from the network.
*/
for (i = 0; boot_device[i] != '\0'; i++) {
if (boot_device[i] >= 'c' && boot_device[i] <= 'f') {
ppc_boot_device = boot_device[i];
break;
}
}
if (ppc_boot_device == '\0') {
fprintf(stderr, "No valid boot device for Mac99 machine\n");
exit(1);
}
}
/* Register 8 MB of ISA IO space */
memory_region_init_alias(isa, NULL, "isa_mmio",
get_system_io(), 0, 0x00800000);
memory_region_add_subregion(get_system_memory(), 0xf2000000, isa);
/* UniN init: XXX should be a real device */
memory_region_init_io(unin_memory, NULL, &unin_ops, token, "unin", 0x1000);
memory_region_add_subregion(get_system_memory(), 0xf8000000, unin_memory);
memory_region_init_io(unin2_memory, NULL, &unin_ops, token, "unin", 0x1000);
memory_region_add_subregion(get_system_memory(), 0xf3000000, unin2_memory);
openpic_irqs = g_malloc0(smp_cpus * sizeof(qemu_irq *));
openpic_irqs[0] =
g_malloc0(smp_cpus * sizeof(qemu_irq) * OPENPIC_OUTPUT_NB);
for (i = 0; i < smp_cpus; i++) {
/* Mac99 IRQ connection between OpenPIC outputs pins
* and PowerPC input pins
*/
switch (PPC_INPUT(env)) {
case PPC_FLAGS_INPUT_6xx:
openpic_irqs[i] = openpic_irqs[0] + (i * OPENPIC_OUTPUT_NB);
openpic_irqs[i][OPENPIC_OUTPUT_INT] =
((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT];
openpic_irqs[i][OPENPIC_OUTPUT_CINT] =
((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT];
openpic_irqs[i][OPENPIC_OUTPUT_MCK] =
((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_MCP];
/* Not connected ? */
openpic_irqs[i][OPENPIC_OUTPUT_DEBUG] = NULL;
/* Check this */
openpic_irqs[i][OPENPIC_OUTPUT_RESET] =
((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_HRESET];
break;
#if defined(TARGET_PPC64)
case PPC_FLAGS_INPUT_970:
openpic_irqs[i] = openpic_irqs[0] + (i * OPENPIC_OUTPUT_NB);
openpic_irqs[i][OPENPIC_OUTPUT_INT] =
((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT];
openpic_irqs[i][OPENPIC_OUTPUT_CINT] =
((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT];
openpic_irqs[i][OPENPIC_OUTPUT_MCK] =
((qemu_irq *)env->irq_inputs)[PPC970_INPUT_MCP];
/* Not connected ? */
openpic_irqs[i][OPENPIC_OUTPUT_DEBUG] = NULL;
/* Check this */
openpic_irqs[i][OPENPIC_OUTPUT_RESET] =
((qemu_irq *)env->irq_inputs)[PPC970_INPUT_HRESET];
break;
#endif /* defined(TARGET_PPC64) */
default:
error_report("Bus model not supported on mac99 machine");
exit(1);
}
}
pic = g_new0(qemu_irq, 64);
dev = qdev_create(NULL, TYPE_OPENPIC);
qdev_prop_set_uint32(dev, "model", OPENPIC_MODEL_RAVEN);
qdev_init_nofail(dev);
s = SYS_BUS_DEVICE(dev);
pic_mem = s->mmio[0].memory;
k = 0;
for (i = 0; i < smp_cpus; i++) {
for (j = 0; j < OPENPIC_OUTPUT_NB; j++) {
sysbus_connect_irq(s, k++, openpic_irqs[i][j]);
}
}
for (i = 0; i < 64; i++) {
pic[i] = qdev_get_gpio_in(dev, i);
}
if (PPC_INPUT(env) == PPC_FLAGS_INPUT_970) {
/* 970 gets a U3 bus */
pci_bus = pci_pmac_u3_init(pic, get_system_memory(), get_system_io());
machine_arch = ARCH_MAC99_U3;
} else {
pci_bus = pci_pmac_init(pic, get_system_memory(), get_system_io());
machine_arch = ARCH_MAC99;
}
machine->usb |= defaults_enabled() && !machine->usb_disabled;
/* Timebase Frequency */
if (kvm_enabled()) {
tbfreq = kvmppc_get_tbfreq();
} else {
tbfreq = TBFREQ;
}
/* init basic PC hardware */
escc_mem = escc_init(0, pic[0x25], pic[0x24],
serial_hds[0], serial_hds[1], ESCC_CLOCK, 4);
memory_region_init_alias(escc_bar, NULL, "escc-bar",
escc_mem, 0, memory_region_size(escc_mem));
macio = pci_create(pci_bus, -1, TYPE_NEWWORLD_MACIO);
dev = DEVICE(macio);
qdev_connect_gpio_out(dev, 0, pic[0x19]); /* CUDA */
qdev_connect_gpio_out(dev, 1, pic[0x0d]); /* IDE */
qdev_connect_gpio_out(dev, 2, pic[0x02]); /* IDE DMA */
qdev_connect_gpio_out(dev, 3, pic[0x0e]); /* IDE */
qdev_connect_gpio_out(dev, 4, pic[0x03]); /* IDE DMA */
qdev_prop_set_uint64(dev, "frequency", tbfreq);
macio_init(macio, pic_mem, escc_bar);
/* We only emulate 2 out of 3 IDE controllers for now */
ide_drive_get(hd, ARRAY_SIZE(hd));
macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio),
"ide[0]"));
macio_ide_init_drives(macio_ide, hd);
macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio),
"ide[1]"));
macio_ide_init_drives(macio_ide, &hd[MAX_IDE_DEVS]);
dev = DEVICE(object_resolve_path_component(OBJECT(macio), "cuda"));
adb_bus = qdev_get_child_bus(dev, "adb.0");
dev = qdev_create(adb_bus, TYPE_ADB_KEYBOARD);
qdev_init_nofail(dev);
dev = qdev_create(adb_bus, TYPE_ADB_MOUSE);
qdev_init_nofail(dev);
if (machine->usb) {
pci_create_simple(pci_bus, -1, "pci-ohci");
/* U3 needs to use USB for input because Linux doesn't support via-cuda
on PPC64 */
if (machine_arch == ARCH_MAC99_U3) {
USBBus *usb_bus = usb_bus_find(-1);
usb_create_simple(usb_bus, "usb-kbd");
usb_create_simple(usb_bus, "usb-mouse");
}
}
pci_vga_init(pci_bus);
if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8) {
graphic_depth = 15;
}
for (i = 0; i < nb_nics; i++) {
pci_nic_init_nofail(&nd_table[i], pci_bus, "ne2k_pci", NULL);
}
/* The NewWorld NVRAM is not located in the MacIO device */
#ifdef CONFIG_KVM
if (kvm_enabled() && getpagesize() > 4096) {
/* We can't combine read-write and read-only in a single page, so
move the NVRAM out of ROM again for KVM */
nvram_addr = 0xFFE00000;
}
#endif
dev = qdev_create(NULL, TYPE_MACIO_NVRAM);
qdev_prop_set_uint32(dev, "size", 0x2000);
qdev_prop_set_uint32(dev, "it_shift", 1);
qdev_init_nofail(dev);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, nvram_addr);
nvr = MACIO_NVRAM(dev);
pmac_format_nvram_partition(nvr, 0x2000);
/* No PCI init: the BIOS will do it */
fw_cfg = fw_cfg_init_mem(CFG_ADDR, CFG_ADDR + 2);
fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, machine_arch);
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base);
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
if (kernel_cmdline) {
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, cmdline_base);
pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE, kernel_cmdline);
} else {
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
}
fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base);
fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ppc_boot_device);
fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width);
fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height);
fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth);
fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled());
if (kvm_enabled()) {
#ifdef CONFIG_KVM
uint8_t *hypercall;
hypercall = g_malloc(16);
kvmppc_get_hypercall(env, hypercall, 16);
fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16);
fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid());
#endif
}
fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, tbfreq);
/* Mac OS X requires a "known good" clock-frequency value; pass it one. */
fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_CLOCKFREQ, CLOCKFREQ);
fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_BUSFREQ, BUSFREQ);
fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_NVRAM_ADDR, nvram_addr);
qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
}
static void aw_a10_realize(DeviceState *dev, Error **errp)
{
AwA10State *s = AW_A10(dev);
SysBusDevice *sysbusdev;
uint8_t i;
qemu_irq fiq, irq;
Error *err = NULL;
object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err);
if (err != NULL) {
error_propagate(errp, err);
return;
}
irq = qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ);
fiq = qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ);
object_property_set_bool(OBJECT(&s->intc), true, "realized", &err);
if (err != NULL) {
error_propagate(errp, err);
return;
}
sysbusdev = SYS_BUS_DEVICE(&s->intc);
sysbus_mmio_map(sysbusdev, 0, AW_A10_PIC_REG_BASE);
sysbus_connect_irq(sysbusdev, 0, irq);
sysbus_connect_irq(sysbusdev, 1, fiq);
for (i = 0; i < AW_A10_PIC_INT_NR; i++) {
s->irq[i] = qdev_get_gpio_in(DEVICE(&s->intc), i);
}
object_property_set_bool(OBJECT(&s->timer), true, "realized", &err);
if (err != NULL) {
error_propagate(errp, err);
return;
}
sysbusdev = SYS_BUS_DEVICE(&s->timer);
sysbus_mmio_map(sysbusdev, 0, AW_A10_PIT_REG_BASE);
sysbus_connect_irq(sysbusdev, 0, s->irq[22]);
sysbus_connect_irq(sysbusdev, 1, s->irq[23]);
sysbus_connect_irq(sysbusdev, 2, s->irq[24]);
sysbus_connect_irq(sysbusdev, 3, s->irq[25]);
sysbus_connect_irq(sysbusdev, 4, s->irq[67]);
sysbus_connect_irq(sysbusdev, 5, s->irq[68]);
memory_region_init_ram(&s->sram_a, OBJECT(dev), "sram A", 48 * KiB,
&error_fatal);
memory_region_add_subregion(get_system_memory(), 0x00000000, &s->sram_a);
create_unimplemented_device("a10-sram-ctrl", 0x01c00000, 4 * KiB);
/* FIXME use qdev NIC properties instead of nd_table[] */
if (nd_table[0].used) {
qemu_check_nic_model(&nd_table[0], TYPE_AW_EMAC);
qdev_set_nic_properties(DEVICE(&s->emac), &nd_table[0]);
}
object_property_set_bool(OBJECT(&s->emac), true, "realized", &err);
if (err != NULL) {
error_propagate(errp, err);
return;
}
sysbusdev = SYS_BUS_DEVICE(&s->emac);
sysbus_mmio_map(sysbusdev, 0, AW_A10_EMAC_BASE);
sysbus_connect_irq(sysbusdev, 0, s->irq[55]);
object_property_set_bool(OBJECT(&s->sata), true, "realized", &err);
if (err) {
error_propagate(errp, err);
return;
}
sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, AW_A10_SATA_BASE);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, s->irq[56]);
/* FIXME use a qdev chardev prop instead of serial_hd() */
serial_mm_init(get_system_memory(), AW_A10_UART0_REG_BASE, 2, s->irq[1],
115200, serial_hd(0), DEVICE_NATIVE_ENDIAN);
}
static void test_io_channel(bool async,
SocketAddress *listen_addr,
SocketAddress *connect_addr,
bool passFD)
{
QIOChannel *src, *dst;
QIOChannelTest *test;
if (async) {
test_io_channel_setup_async(listen_addr, connect_addr, &src, &dst);
g_assert(!passFD ||
qio_channel_has_feature(src, QIO_CHANNEL_FEATURE_FD_PASS));
g_assert(!passFD ||
qio_channel_has_feature(dst, QIO_CHANNEL_FEATURE_FD_PASS));
g_assert(qio_channel_has_feature(src, QIO_CHANNEL_FEATURE_SHUTDOWN));
g_assert(qio_channel_has_feature(dst, QIO_CHANNEL_FEATURE_SHUTDOWN));
test = qio_channel_test_new();
qio_channel_test_run_threads(test, true, src, dst);
qio_channel_test_validate(test);
object_unref(OBJECT(src));
object_unref(OBJECT(dst));
test_io_channel_setup_async(listen_addr, connect_addr, &src, &dst);
g_assert(!passFD ||
qio_channel_has_feature(src, QIO_CHANNEL_FEATURE_FD_PASS));
g_assert(!passFD ||
qio_channel_has_feature(dst, QIO_CHANNEL_FEATURE_FD_PASS));
g_assert(qio_channel_has_feature(src, QIO_CHANNEL_FEATURE_SHUTDOWN));
g_assert(qio_channel_has_feature(dst, QIO_CHANNEL_FEATURE_SHUTDOWN));
test = qio_channel_test_new();
qio_channel_test_run_threads(test, false, src, dst);
qio_channel_test_validate(test);
object_unref(OBJECT(src));
object_unref(OBJECT(dst));
} else {
test_io_channel_setup_sync(listen_addr, connect_addr, &src, &dst);
g_assert(!passFD ||
qio_channel_has_feature(src, QIO_CHANNEL_FEATURE_FD_PASS));
g_assert(!passFD ||
qio_channel_has_feature(dst, QIO_CHANNEL_FEATURE_FD_PASS));
g_assert(qio_channel_has_feature(src, QIO_CHANNEL_FEATURE_SHUTDOWN));
g_assert(qio_channel_has_feature(dst, QIO_CHANNEL_FEATURE_SHUTDOWN));
test = qio_channel_test_new();
qio_channel_test_run_threads(test, true, src, dst);
qio_channel_test_validate(test);
object_unref(OBJECT(src));
object_unref(OBJECT(dst));
test_io_channel_setup_sync(listen_addr, connect_addr, &src, &dst);
g_assert(!passFD ||
qio_channel_has_feature(src, QIO_CHANNEL_FEATURE_FD_PASS));
g_assert(!passFD ||
qio_channel_has_feature(dst, QIO_CHANNEL_FEATURE_FD_PASS));
g_assert(qio_channel_has_feature(src, QIO_CHANNEL_FEATURE_SHUTDOWN));
g_assert(qio_channel_has_feature(dst, QIO_CHANNEL_FEATURE_SHUTDOWN));
test = qio_channel_test_new();
qio_channel_test_run_threads(test, false, src, dst);
qio_channel_test_validate(test);
object_unref(OBJECT(src));
object_unref(OBJECT(dst));
}
}
static void pci_bridge_dev_realize(PCIDevice *dev, Error **errp)
{
PCIBridge *br = PCI_BRIDGE(dev);
PCIBridgeDev *bridge_dev = PCI_BRIDGE_DEV(dev);
int err;
Error *local_err = NULL;
pci_bridge_initfn(dev, TYPE_PCI_BUS);
if (bridge_dev->flags & (1 << PCI_BRIDGE_DEV_F_SHPC_REQ)) {
dev->config[PCI_INTERRUPT_PIN] = 0x1;
memory_region_init(&bridge_dev->bar, OBJECT(dev), "shpc-bar",
shpc_bar_size(dev));
err = shpc_init(dev, &br->sec_bus, &bridge_dev->bar, 0, errp);
if (err) {
goto shpc_error;
}
} else {
/* MSI is not applicable without SHPC */
bridge_dev->msi = ON_OFF_AUTO_OFF;
}
err = slotid_cap_init(dev, 0, bridge_dev->chassis_nr, 0, errp);
if (err) {
goto slotid_error;
}
if (bridge_dev->msi != ON_OFF_AUTO_OFF) {
/* it means SHPC exists, because MSI is needed by SHPC */
err = msi_init(dev, 0, 1, true, true, &local_err);
/* Any error other than -ENOTSUP(board's MSI support is broken)
* is a programming error */
assert(!err || err == -ENOTSUP);
if (err && bridge_dev->msi == ON_OFF_AUTO_ON) {
/* Can't satisfy user's explicit msi=on request, fail */
error_append_hint(&local_err, "You have to use msi=auto (default) "
"or msi=off with this machine type.\n");
error_propagate(errp, local_err);
goto msi_error;
}
assert(!local_err || bridge_dev->msi == ON_OFF_AUTO_AUTO);
/* With msi=auto, we fall back to MSI off silently */
error_free(local_err);
}
if (shpc_present(dev)) {
/* TODO: spec recommends using 64 bit prefetcheable BAR.
* Check whether that works well. */
pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY |
PCI_BASE_ADDRESS_MEM_TYPE_64, &bridge_dev->bar);
}
return;
msi_error:
slotid_cap_cleanup(dev);
slotid_error:
if (shpc_present(dev)) {
shpc_cleanup(dev, &bridge_dev->bar);
}
shpc_error:
pci_bridge_exitfn(dev);
}
static void test_io_channel_ipv4(bool async)
{
SocketAddress *listen_addr = g_new0(SocketAddress, 1);
SocketAddress *connect_addr = g_new0(SocketAddress, 1);
listen_addr->type = SOCKET_ADDRESS_TYPE_INET;
listen_addr->u.inet = (InetSocketAddress) {
.host = g_strdup("127.0.0.1"),
.port = NULL, /* Auto-select */
};
connect_addr->type = SOCKET_ADDRESS_TYPE_INET;
connect_addr->u.inet = (InetSocketAddress) {
.host = g_strdup("127.0.0.1"),
.port = NULL, /* Filled in later */
};
test_io_channel(async, listen_addr, connect_addr, false);
qapi_free_SocketAddress(listen_addr);
qapi_free_SocketAddress(connect_addr);
}
static void test_io_channel_ipv4_sync(void)
{
return test_io_channel_ipv4(false);
}
static void test_io_channel_ipv4_async(void)
{
return test_io_channel_ipv4(true);
}
static void test_io_channel_ipv6(bool async)
{
SocketAddress *listen_addr = g_new0(SocketAddress, 1);
SocketAddress *connect_addr = g_new0(SocketAddress, 1);
listen_addr->type = SOCKET_ADDRESS_TYPE_INET;
listen_addr->u.inet = (InetSocketAddress) {
.host = g_strdup("::1"),
.port = NULL, /* Auto-select */
};
connect_addr->type = SOCKET_ADDRESS_TYPE_INET;
connect_addr->u.inet = (InetSocketAddress) {
.host = g_strdup("::1"),
.port = NULL, /* Filled in later */
};
test_io_channel(async, listen_addr, connect_addr, false);
qapi_free_SocketAddress(listen_addr);
qapi_free_SocketAddress(connect_addr);
}
static void test_io_channel_ipv6_sync(void)
{
return test_io_channel_ipv6(false);
}
static void test_io_channel_ipv6_async(void)
{
return test_io_channel_ipv6(true);
}
#ifndef _WIN32
static void test_io_channel_unix(bool async)
{
SocketAddress *listen_addr = g_new0(SocketAddress, 1);
SocketAddress *connect_addr = g_new0(SocketAddress, 1);
#define TEST_SOCKET "test-io-channel-socket.sock"
listen_addr->type = SOCKET_ADDRESS_TYPE_UNIX;
listen_addr->u.q_unix.path = g_strdup(TEST_SOCKET);
connect_addr->type = SOCKET_ADDRESS_TYPE_UNIX;
connect_addr->u.q_unix.path = g_strdup(TEST_SOCKET);
test_io_channel(async, listen_addr, connect_addr, true);
qapi_free_SocketAddress(listen_addr);
qapi_free_SocketAddress(connect_addr);
g_assert(g_file_test(TEST_SOCKET, G_FILE_TEST_EXISTS) == FALSE);
}
static void test_io_channel_unix_sync(void)
{
return test_io_channel_unix(false);
}
static void test_io_channel_unix_async(void)
{
return test_io_channel_unix(true);
}
static void test_io_channel_unix_fd_pass(void)
{
SocketAddress *listen_addr = g_new0(SocketAddress, 1);
SocketAddress *connect_addr = g_new0(SocketAddress, 1);
QIOChannel *src, *dst;
int testfd;
int fdsend[3];
int *fdrecv = NULL;
size_t nfdrecv = 0;
size_t i;
char bufsend[12], bufrecv[12];
struct iovec iosend[1], iorecv[1];
#define TEST_SOCKET "test-io-channel-socket.sock"
#define TEST_FILE "test-io-channel-socket.txt"
testfd = open(TEST_FILE, O_RDWR|O_TRUNC|O_CREAT, 0700);
g_assert(testfd != -1);
fdsend[0] = testfd;
fdsend[1] = testfd;
fdsend[2] = testfd;
listen_addr->type = SOCKET_ADDRESS_TYPE_UNIX;
listen_addr->u.q_unix.path = g_strdup(TEST_SOCKET);
connect_addr->type = SOCKET_ADDRESS_TYPE_UNIX;
connect_addr->u.q_unix.path = g_strdup(TEST_SOCKET);
test_io_channel_setup_sync(listen_addr, connect_addr, &src, &dst);
memcpy(bufsend, "Hello World", G_N_ELEMENTS(bufsend));
iosend[0].iov_base = bufsend;
iosend[0].iov_len = G_N_ELEMENTS(bufsend);
iorecv[0].iov_base = bufrecv;
iorecv[0].iov_len = G_N_ELEMENTS(bufrecv);
g_assert(qio_channel_has_feature(src, QIO_CHANNEL_FEATURE_FD_PASS));
g_assert(qio_channel_has_feature(dst, QIO_CHANNEL_FEATURE_FD_PASS));
qio_channel_writev_full(src,
iosend,
G_N_ELEMENTS(iosend),
fdsend,
G_N_ELEMENTS(fdsend),
&error_abort);
qio_channel_readv_full(dst,
iorecv,
G_N_ELEMENTS(iorecv),
&fdrecv,
&nfdrecv,
&error_abort);
g_assert(nfdrecv == G_N_ELEMENTS(fdsend));
/* Each recvd FD should be different from sent FD */
for (i = 0; i < nfdrecv; i++) {
g_assert_cmpint(fdrecv[i], !=, testfd);
}
/* Each recvd FD should be different from each other */
g_assert_cmpint(fdrecv[0], !=, fdrecv[1]);
g_assert_cmpint(fdrecv[0], !=, fdrecv[2]);
g_assert_cmpint(fdrecv[1], !=, fdrecv[2]);
/* Check the I/O buf we sent at the same time matches */
g_assert(memcmp(bufsend, bufrecv, G_N_ELEMENTS(bufsend)) == 0);
/* Write some data into the FD we received */
g_assert(write(fdrecv[0], bufsend, G_N_ELEMENTS(bufsend)) ==
G_N_ELEMENTS(bufsend));
/* Read data from the original FD and make sure it matches */
memset(bufrecv, 0, G_N_ELEMENTS(bufrecv));
g_assert(lseek(testfd, 0, SEEK_SET) == 0);
g_assert(read(testfd, bufrecv, G_N_ELEMENTS(bufrecv)) ==
G_N_ELEMENTS(bufrecv));
g_assert(memcmp(bufsend, bufrecv, G_N_ELEMENTS(bufsend)) == 0);
object_unref(OBJECT(src));
object_unref(OBJECT(dst));
qapi_free_SocketAddress(listen_addr);
qapi_free_SocketAddress(connect_addr);
unlink(TEST_SOCKET);
unlink(TEST_FILE);
close(testfd);
for (i = 0; i < nfdrecv; i++) {
close(fdrecv[i]);
}
g_free(fdrecv);
}
static void test_io_channel_unix_listen_cleanup(void)
{
QIOChannelSocket *ioc;
struct sockaddr_un un;
int sock;
#define TEST_SOCKET "test-io-channel-socket.sock"
ioc = qio_channel_socket_new();
/* Manually bind ioc without calling the qio api to avoid setting
* the LISTEN feature */
sock = qemu_socket(PF_UNIX, SOCK_STREAM, 0);
memset(&un, 0, sizeof(un));
un.sun_family = AF_UNIX;
snprintf(un.sun_path, sizeof(un.sun_path), "%s", TEST_SOCKET);
unlink(TEST_SOCKET);
bind(sock, (struct sockaddr *)&un, sizeof(un));
ioc->fd = sock;
ioc->localAddrLen = sizeof(ioc->localAddr);
getsockname(sock, (struct sockaddr *)&ioc->localAddr,
&ioc->localAddrLen);
g_assert(g_file_test(TEST_SOCKET, G_FILE_TEST_EXISTS));
object_unref(OBJECT(ioc));
g_assert(g_file_test(TEST_SOCKET, G_FILE_TEST_EXISTS));
unlink(TEST_SOCKET);
}
}
/* CPU address corresponds to the core_id and the index */
if (cpu_addr >= ms->possible_cpus->len) {
return NULL;
}
return S390_CPU(ms->possible_cpus->cpus[cpu_addr].cpu);
}
static S390CPU *s390x_new_cpu(const char *typename, uint32_t core_id,
Error **errp)
{
S390CPU *cpu = S390_CPU(object_new(typename));
Error *err = NULL;
object_property_set_int(OBJECT(cpu), core_id, "core-id", &err);
if (err != NULL) {
goto out;
}
object_property_set_bool(OBJECT(cpu), true, "realized", &err);
out:
object_unref(OBJECT(cpu));
if (err) {
error_propagate(errp, err);
cpu = NULL;
}
return cpu;
}
static void s390_init_cpus(MachineState *machine)
uint64_t pc_dimm_get_free_addr(uint64_t address_space_start,
uint64_t address_space_size,
uint64_t *hint, uint64_t align, uint64_t size,
Error **errp)
{
GSList *list = NULL, *item;
uint64_t new_addr, ret = 0;
uint64_t address_space_end = address_space_start + address_space_size;
g_assert(QEMU_ALIGN_UP(address_space_start, align) == address_space_start);
if (!address_space_size) {
error_setg(errp, "memory hotplug is not enabled, "
"please add maxmem option");
goto out;
}
if (hint && QEMU_ALIGN_UP(*hint, align) != *hint) {
error_setg(errp, "address must be aligned to 0x%" PRIx64 " bytes",
align);
goto out;
}
if (QEMU_ALIGN_UP(size, align) != size) {
error_setg(errp, "backend memory size must be multiple of 0x%"
PRIx64, align);
goto out;
}
assert(address_space_end > address_space_start);
object_child_foreach(qdev_get_machine(), pc_dimm_built_list, &list);
if (hint) {
new_addr = *hint;
} else {
new_addr = address_space_start;
}
/* find address range that will fit new DIMM */
for (item = list; item; item = g_slist_next(item)) {
PCDIMMDevice *dimm = item->data;
uint64_t dimm_size = object_property_get_uint(OBJECT(dimm),
PC_DIMM_SIZE_PROP,
errp);
if (errp && *errp) {
goto out;
}
if (ranges_overlap(dimm->addr, dimm_size, new_addr, size)) {
if (hint) {
DeviceState *d = DEVICE(dimm);
error_setg(errp, "address range conflicts with '%s'", d->id);
goto out;
}
new_addr = QEMU_ALIGN_UP(dimm->addr + dimm_size, align);
}
}
ret = new_addr;
if (new_addr < address_space_start) {
error_setg(errp, "can't add memory [0x%" PRIx64 ":0x%" PRIx64
"] at 0x%" PRIx64, new_addr, size, address_space_start);
} else if ((new_addr + size) > address_space_end) {
error_setg(errp, "can't add memory [0x%" PRIx64 ":0x%" PRIx64
"] beyond 0x%" PRIx64, new_addr, size, address_space_end);
}
out:
g_slist_free(list);
return ret;
}