void
odm_ConfigRFReg_8821A(
IN PDM_ODM_T pDM_Odm,
IN u4Byte Addr,
IN u4Byte Data,
IN ODM_RF_RADIO_PATH_E RF_PATH,
IN u4Byte RegAddr
)
{
if(Addr == 0xfe || Addr == 0xffe) {
#ifdef CONFIG_LONG_DELAY_ISSUE
ODM_sleep_ms(50);
#else
ODM_delay_ms(50);
#endif
} else if (Addr == 0xfd) {
ODM_delay_ms(5);
} else if (Addr == 0xfc) {
ODM_delay_ms(1);
} else if (Addr == 0xfb) {
ODM_delay_us(50);
} else if (Addr == 0xfa) {
ODM_delay_us(5);
} else if (Addr == 0xf9) {
ODM_delay_us(1);
} else {
ODM_SetRFReg(pDM_Odm, RF_PATH, RegAddr, bRFRegOffsetMask, Data);
// Add 1us delay between BB/RF register setting.
ODM_delay_us(1);
}
}
void odm_ConfigBB_PHY_8188E(struct odm_dm_struct *pDM_Odm, u32 Addr, u32 Bitmask, u32 Data)
{
if (Addr == 0xfe) {
ODM_sleep_ms(50);
} else if (Addr == 0xfd) {
ODM_delay_ms(5);
} else if (Addr == 0xfc) {
ODM_delay_ms(1);
} else if (Addr == 0xfb) {
ODM_delay_us(50);
} else if (Addr == 0xfa) {
ODM_delay_us(5);
} else if (Addr == 0xf9) {
ODM_delay_us(1);
} else {
if (Addr == 0xa24)
pDM_Odm->RFCalibrateInfo.RegA24 = Data;
ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data);
/* Add 1us delay between BB/RF register setting. */
ODM_delay_us(1);
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE,
("===> ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X\n",
Addr, Data));
}
}
void
odm_ConfigBB_PHY_8812A(
IN PDM_ODM_T pDM_Odm,
IN u4Byte Addr,
IN u4Byte Bitmask,
IN u4Byte Data
)
{
if (Addr == 0xfe) {
#ifdef CONFIG_LONG_DELAY_ISSUE
ODM_sleep_ms(50);
#else
ODM_delay_ms(50);
#endif
} else if (Addr == 0xfd) {
ODM_delay_ms(5);
} else if (Addr == 0xfc) {
ODM_delay_ms(1);
} else if (Addr == 0xfb) {
ODM_delay_us(50);
} else if (Addr == 0xfa) {
ODM_delay_us(5);
} else if (Addr == 0xf9) {
ODM_delay_us(1);
} else {
ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data);
// Add 1us delay between BB/RF register setting.
ODM_delay_us(1);
}
ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X\n", Addr, Data));
}
void
odm_ConfigBB_PHY_REG_PG_8188E(
PDM_ODM_T pDM_Odm,
u4Byte Addr,
u4Byte Bitmask,
u4Byte Data
)
{
if (Addr == 0xfe){
ODM_sleep_ms(50);
}
else if (Addr == 0xfd){
ODM_delay_ms(5);
}
else if (Addr == 0xfc){
ODM_delay_ms(1);
}
else if (Addr == 0xfb){
ODM_delay_us(50);
}
else if (Addr == 0xfa){
ODM_delay_us(5);
}
else if (Addr == 0xf9){
ODM_delay_us(1);
}
else{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_LOUD, ("===> @@@@@@@ ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X %08X\n", Addr, Bitmask, Data));
storePwrIndexDiffRateOffset(pDM_Odm->Adapter, Addr, Bitmask, Data);
}
}
void odm_ConfigBB_AGC_8188E(struct odm_dm_struct *pDM_Odm, u32 Addr, u32 Bitmask, u32 Data)
{
ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data);
/* Add 1us delay between BB/RF register setting. */
ODM_delay_us(1);
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE,
("===> ODM_ConfigBBWithHeaderFile: [AGC_TAB] %08X %08X\n",
Addr, Data));
}
void
odm_ConfigRFReg_8188E(
PDM_ODM_T pDM_Odm,
u4Byte Addr,
u4Byte Data,
ODM_RF_RADIO_PATH_E RF_PATH,
u4Byte RegAddr
)
{
if (Addr == 0xffe)
{
ODM_sleep_ms(50);
}
else if (Addr == 0xfd)
{
ODM_delay_ms(5);
}
else if (Addr == 0xfc)
{
ODM_delay_ms(1);
}
else if (Addr == 0xfb)
{
ODM_delay_us(50);
}
else if (Addr == 0xfa)
{
ODM_delay_us(5);
}
else if (Addr == 0xf9)
{
ODM_delay_us(1);
}
else
{
ODM_SetRFReg(pDM_Odm, RF_PATH, RegAddr, bRFRegOffsetMask, Data);
/* Add 1us delay between BB/RF register setting. */
ODM_delay_us(1);
}
}
void odm_ConfigRFReg_8188E(struct odm_dm_struct *pDM_Odm, u32 Addr,
u32 Data, enum rf_radio_path RF_PATH,
u32 RegAddr)
{
if (Addr == 0xffe) {
ODM_sleep_ms(50);
} else if (Addr == 0xfd) {
ODM_delay_ms(5);
} else if (Addr == 0xfc) {
ODM_delay_ms(1);
} else if (Addr == 0xfb) {
ODM_delay_us(50);
} else if (Addr == 0xfa) {
ODM_delay_us(5);
} else if (Addr == 0xf9) {
ODM_delay_us(1);
} else {
ODM_SetRFReg(pDM_Odm, RF_PATH, RegAddr, bRFRegOffsetMask, Data);
/* Add 1us delay between BB/RF register setting. */
ODM_delay_us(1);
}
}
void
odm_ConfigBB_PHY_REG_PG_8188E(
IN PDM_ODM_T pDM_Odm,
IN u4Byte Addr,
IN u4Byte Bitmask,
IN u4Byte Data
)
{
if (Addr == 0xfe){
#ifdef CONFIG_LONG_DELAY_ISSUE
ODM_sleep_ms(50);
#else
ODM_delay_ms(50);
#endif
}
else if (Addr == 0xfd){
ODM_delay_ms(5);
}
else if (Addr == 0xfc){
ODM_delay_ms(1);
}
else if (Addr == 0xfb){
ODM_delay_us(50);
}
else if (Addr == 0xfa){
ODM_delay_us(5);
}
else if (Addr == 0xf9){
ODM_delay_us(1);
}
else{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_LOUD, ("===> @@@@@@@ ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X %08X\n", Addr, Bitmask, Data));
#if !(DM_ODM_SUPPORT_TYPE&ODM_AP)
storePwrIndexDiffRateOffset(pDM_Odm->Adapter, Addr, Bitmask, Data);
#endif
}
}
void
odm_ConfigBB_AGC_8812A(
IN PDM_ODM_T pDM_Odm,
IN u4Byte Addr,
IN u4Byte Bitmask,
IN u4Byte Data
)
{
ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data);
// Add 1us delay between BB/RF register setting.
ODM_delay_us(1);
ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigBBWithHeaderFile: [AGC_TAB] %08X %08X\n", Addr, Data));
}
void
odm_ConfigBB_AGC_8723A(
PDM_ODM_T pDM_Odm,
u32 Addr,
u32 Bitmask,
u32 Data
)
{
ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data);
// Add 1us delay between BB/RF register setting.
ODM_delay_us(1);
ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ConfigBBWithHeaderFile: [AGC_TAB] %08X %08X\n", Addr, Data));
}
void
odm_ConfigRFReg_8192E(
IN PDM_ODM_T pDM_Odm,
IN u4Byte Addr,
IN u4Byte Data,
IN ODM_RF_RADIO_PATH_E RF_PATH,
IN u4Byte RegAddr
)
{
if(Addr == 0xfe || Addr == 0xffe)
{
#ifdef CONFIG_LONG_DELAY_ISSUE
ODM_sleep_ms(50);
#else
ODM_delay_ms(50);
#endif
}
else
{
ODM_SetRFReg(pDM_Odm, RF_PATH, RegAddr, bRFRegOffsetMask, Data);
// Add 1us delay between BB/RF register setting.
ODM_delay_us(1);
//For disable/enable test in high temperature, the B6 value will fail to fill. Suggestion by Ed 20130.
if(Addr == 0xb6)
{
u4Byte getvalue=0;
u1Byte count =0;
getvalue = ODM_GetRFReg(pDM_Odm, RF_PATH, Addr, bMaskDWord);
ODM_delay_us(1);
while((getvalue>>8)!=(Data>>8))
{
count++;
ODM_SetRFReg(pDM_Odm, RF_PATH, RegAddr, bRFRegOffsetMask, Data);
ODM_delay_us(1);
getvalue = ODM_GetRFReg(pDM_Odm, RF_PATH, Addr, bMaskDWord);
ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [B6] getvalue 0x%x, Data 0x%x, count %d\n", getvalue, Data,count));
if(count>5)
break;
}
}
if(Addr == 0xb2)
{
u4Byte getvalue=0;
u1Byte count =0;
getvalue = ODM_GetRFReg(pDM_Odm, RF_PATH, Addr, bMaskDWord);
ODM_delay_us(1);
while(getvalue!=Data)
{
count++;
ODM_SetRFReg(pDM_Odm, RF_PATH, RegAddr, bRFRegOffsetMask, Data);
ODM_delay_us(1);
//Do LCK againg
ODM_SetRFReg(pDM_Odm, RF_PATH, 0x18, bRFRegOffsetMask, 0x0fc07);
ODM_delay_us(1);
getvalue = ODM_GetRFReg(pDM_Odm, RF_PATH, Addr, bMaskDWord);
ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [B2] getvalue 0x%x, Data 0x%x, count %d\n", getvalue, Data,count));
if(count>5)
break;
}
}
}
VOID
halTxbf8192E_DownloadNDPA(
IN PVOID pDM_VOID,
IN u1Byte Idx
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
u1Byte u1bTmp = 0, tmpReg422 = 0, Head_Page;
u1Byte BcnValidReg = 0, count = 0, DLBcnCount = 0;
BOOLEAN bSendBeacon = FALSE;
PADAPTER Adapter = pDM_Odm->Adapter;
u1Byte TxPageBndy = LAST_ENTRY_OF_TX_PKT_BUFFER_8812;
/*default reseved 1 page for the IC type which is undefined.*/
PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo;
PRT_BEAMFORMEE_ENTRY pBeamEntry = pBeamInfo->BeamformeeEntry + Idx;
ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__));
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
*pDM_Odm->pbFwDwRsvdPageInProgress = TRUE;
#endif
if (Idx == 0)
Head_Page = 0xFE;
else
Head_Page = 0xFE;
Adapter->HalFunc.GetHalDefVarHandler(Adapter, HAL_DEF_TX_PAGE_BOUNDARY, (pu1Byte)&TxPageBndy);
/*Set REG_CR bit 8. DMA beacon by SW.*/
u1bTmp = ODM_Read1Byte(pDM_Odm, REG_CR_8192E+1);
ODM_Write1Byte(pDM_Odm, REG_CR_8192E+1, (u1bTmp | BIT0));
/*Set FWHW_TXQ_CTRL 0x422[6]=0 to tell Hw the packet is not a real beacon frame.*/
tmpReg422 = ODM_Read1Byte(pDM_Odm, REG_FWHW_TXQ_CTRL_8192E+2);
ODM_Write1Byte(pDM_Odm, REG_FWHW_TXQ_CTRL_8192E+2, tmpReg422 & (~BIT6));
if (tmpReg422 & BIT6) {
ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_WARNING, ("%s There is an Adapter is sending beacon.\n", __func__));
bSendBeacon = TRUE;
}
/*TDECTRL[15:8] 0x209[7:0] = 0xFE/0xFD NDPA Head for TXDMA*/
ODM_Write1Byte(pDM_Odm, REG_DWBCN0_CTRL_8192E+1, Head_Page);
do {
/*Clear beacon valid check bit.*/
BcnValidReg = ODM_Read1Byte(pDM_Odm, REG_DWBCN0_CTRL_8192E+2);
ODM_Write1Byte(pDM_Odm, REG_DWBCN0_CTRL_8192E+2, (BcnValidReg | BIT0));
// download NDPA rsvd page.
Beamforming_SendHTNDPAPacket(pDM_Odm, pBeamEntry->MacAddr, pBeamEntry->SoundBW, BEACON_QUEUE);
#if(DEV_BUS_TYPE == RT_PCI_INTERFACE)
u1bTmp = ODM_Read1Byte(pDM_Odm, REG_MGQ_TXBD_NUM_8192E+3);
count = 0;
while ((count < 20) && (u1bTmp & BIT4)) {
count++;
ODM_delay_us(10);
u1bTmp = ODM_Read1Byte(pDM_Odm, REG_MGQ_TXBD_NUM_8192E+3);
}
ODM_Write1Byte(pDM_Odm, REG_MGQ_TXBD_NUM_8192E+3, u1bTmp | BIT4);
#endif
/*check rsvd page download OK.*/
BcnValidReg = ODM_Read1Byte(pDM_Odm, REG_DWBCN0_CTRL_8192E+2);
count = 0;
while (!(BcnValidReg & BIT0) && count < 20) {
count++;
ODM_delay_us(10);
BcnValidReg = ODM_Read1Byte(pDM_Odm, REG_DWBCN0_CTRL_8192E+2);
}
DLBcnCount++;
} while (!(BcnValidReg & BIT0) && DLBcnCount < 5);
if (!(BcnValidReg & BIT0))
ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_WARNING, ("%s Download RSVD page failed!\n", __func__));
/*TDECTRL[15:8] 0x209[7:0] = 0xF9 Beacon Head for TXDMA*/
ODM_Write1Byte(pDM_Odm, REG_DWBCN0_CTRL_8192E+1, TxPageBndy);
/*To make sure that if there exists an adapter which would like to send beacon.*/
/*If exists, the origianl value of 0x422[6] will be 1, we should check this to*/
/*prevent from setting 0x422[6] to 0 after download reserved page, or it will cause*/
/*the beacon cannot be sent by HW.*/
/*2010.06.23. Added by tynli.*/
if (bSendBeacon)
ODM_Write1Byte(pDM_Odm, REG_FWHW_TXQ_CTRL_8192E+2, tmpReg422);
/*Do not enable HW DMA BCN or it will cause Pcie interface hang by timing issue. 2011.11.24. by tynli.*/
/*Clear CR[8] or beacon packet will not be send to TxBuf anymore.*/
u1bTmp = ODM_Read1Byte(pDM_Odm, REG_CR_8192E+1);
ODM_Write1Byte(pDM_Odm, REG_CR_8192E+1, (u1bTmp & (~BIT0)));
pBeamEntry->BeamformEntryState = BEAMFORMING_ENTRY_STATE_PROGRESSED;
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
*pDM_Odm->pbFwDwRsvdPageInProgress = FALSE;
#endif
}