/*
* Fill in the cache parameters using the cpu node.
*/
void
cache_init(struct pcpu *pcpu)
{
u_long set;
if (OF_GET(pcpu->pc_node, "icache-size",
pcpu->pc_cache.ic_size) == -1 ||
OF_GET(pcpu->pc_node, "icache-line-size",
pcpu->pc_cache.ic_linesize) == -1 ||
OF_GET(pcpu->pc_node, "icache-associativity",
pcpu->pc_cache.ic_assoc) == -1 ||
OF_GET(pcpu->pc_node, "dcache-size",
pcpu->pc_cache.dc_size) == -1 ||
OF_GET(pcpu->pc_node, "dcache-line-size",
pcpu->pc_cache.dc_linesize) == -1 ||
OF_GET(pcpu->pc_node, "dcache-associativity",
pcpu->pc_cache.dc_assoc) == -1 ||
OF_GET(pcpu->pc_node, "ecache-size",
pcpu->pc_cache.ec_size) == -1 ||
OF_GET(pcpu->pc_node, "ecache-line-size",
pcpu->pc_cache.ec_linesize) == -1 ||
OF_GET(pcpu->pc_node, "ecache-associativity",
pcpu->pc_cache.ec_assoc) == -1)
panic("cache_init: could not retrieve cache parameters");
set = pcpu->pc_cache.ic_size / pcpu->pc_cache.ic_assoc;
if ((set & ~(1UL << (ffs(set) - 1))) != 0)
panic("cache_init: I$ set size not a power of 2");
if ((pcpu->pc_cache.dc_size &
~(1UL << (ffs(pcpu->pc_cache.dc_size) - 1))) != 0)
panic("cache_init: D$ size not a power of 2");
if (((pcpu->pc_cache.dc_size / pcpu->pc_cache.dc_assoc) /
PAGE_SIZE) != DCACHE_COLORS)
panic("cache_init: too many D$ colors");
set = pcpu->pc_cache.ec_size / pcpu->pc_cache.ec_assoc;
if ((set & ~(1UL << (ffs(set) - 1))) != 0)
panic("cache_init: E$ set size not a power of 2");
if (cpu_impl >= CPU_IMPL_ULTRASPARCIII) {
cache_enable = cheetah_cache_enable;
cache_flush = cheetah_cache_flush;
dcache_page_inval = cheetah_dcache_page_inval;
icache_page_inval = cheetah_icache_page_inval;
tlb_flush_nonlocked = cheetah_tlb_flush_nonlocked;
tlb_flush_user = cheetah_tlb_flush_user;
} else {
cache_enable = spitfire_cache_enable;
cache_flush = spitfire_cache_flush;
dcache_page_inval = spitfire_dcache_page_inval;
icache_page_inval = spitfire_icache_page_inval;
tlb_flush_nonlocked = spitfire_tlb_flush_nonlocked;
tlb_flush_user = spitfire_tlb_flush_user;
}
}
/*
* Fill in the cache parameters using the CPU node.
*/
void
cache_init(struct pcpu *pcpu)
{
u_long set;
u_int use_new_prop;
/*
* For CPUs which ignore TD_CV and support hardware unaliasing don't
* bother doing page coloring. This is equal across all CPUs.
*/
if (pcpu->pc_cpuid == 0 && pcpu->pc_impl == CPU_IMPL_SPARC64V)
dcache_color_ignore = 1;
use_new_prop = cache_new_prop(pcpu->pc_impl);
if (OF_GET(pcpu->pc_node, !use_new_prop ? "icache-size" :
"l1-icache-size", pcpu->pc_cache.ic_size) == -1 ||
OF_GET(pcpu->pc_node, !use_new_prop ? "icache-line-size" :
"l1-icache-line-size", pcpu->pc_cache.ic_linesize) == -1 ||
OF_GET(pcpu->pc_node, !use_new_prop ? "icache-associativity" :
"l1-icache-associativity", pcpu->pc_cache.ic_assoc) == -1 ||
OF_GET(pcpu->pc_node, !use_new_prop ? "dcache-size" :
"l1-dcache-size", pcpu->pc_cache.dc_size) == -1 ||
OF_GET(pcpu->pc_node, !use_new_prop ? "dcache-line-size" :
"l1-dcache-line-size", pcpu->pc_cache.dc_linesize) == -1 ||
OF_GET(pcpu->pc_node, !use_new_prop ? "dcache-associativity" :
"l1-dcache-associativity", pcpu->pc_cache.dc_assoc) == -1 ||
OF_GET(pcpu->pc_node, !use_new_prop ? "ecache-size" :
"l2-cache-size", pcpu->pc_cache.ec_size) == -1 ||
OF_GET(pcpu->pc_node, !use_new_prop ? "ecache-line-size" :
"l2-cache-line-size", pcpu->pc_cache.ec_linesize) == -1 ||
OF_GET(pcpu->pc_node, !use_new_prop ? "ecache-associativity" :
"l2-cache-associativity", pcpu->pc_cache.ec_assoc) == -1)
panic("cache_init: could not retrieve cache parameters");
set = pcpu->pc_cache.ic_size / pcpu->pc_cache.ic_assoc;
if ((set & ~(1UL << (ffs(set) - 1))) != 0)
panic("cache_init: I$ set size not a power of 2");
if ((pcpu->pc_cache.dc_size &
~(1UL << (ffs(pcpu->pc_cache.dc_size) - 1))) != 0)
panic("cache_init: D$ size not a power of 2");
/*
* For CPUs which don't support unaliasing in hardware ensure that
* the data cache doesn't have too many virtual colors.
*/
if (dcache_color_ignore == 0 && ((pcpu->pc_cache.dc_size /
pcpu->pc_cache.dc_assoc) / PAGE_SIZE) != DCACHE_COLORS)
panic("cache_init: too many D$ colors");
set = pcpu->pc_cache.ec_size / pcpu->pc_cache.ec_assoc;
if ((set & ~(1UL << (ffs(set) - 1))) != 0)
panic("cache_init: E$ set size not a power of 2");
if (pcpu->pc_impl >= CPU_IMPL_ULTRASPARCIII) {
cache_enable = cheetah_cache_enable;
cache_flush = cheetah_cache_flush;
dcache_page_inval = cheetah_dcache_page_inval;
icache_page_inval = cheetah_icache_page_inval;
tlb_flush_nonlocked = cheetah_tlb_flush_nonlocked;
tlb_flush_user = cheetah_tlb_flush_user;
} else if (pcpu->pc_impl == CPU_IMPL_SPARC64V) {
cache_enable = zeus_cache_enable;
cache_flush = zeus_cache_flush;
dcache_page_inval = zeus_dcache_page_inval;
icache_page_inval = zeus_icache_page_inval;
tlb_flush_nonlocked = zeus_tlb_flush_nonlocked;
tlb_flush_user = zeus_tlb_flush_user;
} else if (pcpu->pc_impl >= CPU_IMPL_ULTRASPARCI &&
pcpu->pc_impl < CPU_IMPL_ULTRASPARCIII) {
cache_enable = spitfire_cache_enable;
cache_flush = spitfire_cache_flush;
dcache_page_inval = spitfire_dcache_page_inval;
icache_page_inval = spitfire_icache_page_inval;
tlb_flush_nonlocked = spitfire_tlb_flush_nonlocked;
tlb_flush_user = spitfire_tlb_flush_user;
} else
panic("cache_init: unknown CPU");
}
