/**
* @brief Initialize the SDRC module
*
* @return void
*/
static void sdrc_init(void)
{
/* SDRAM software reset */
/* No idle ack and RESET enable */
writel(0x1A, OMAP3_SDRC_REG(SYSCONFIG));
sdelay(100);
/* No idle ack and RESET disable */
writel(0x18, OMAP3_SDRC_REG(SYSCONFIG));
/* SDRC Sharing register */
/* 32-bit SDRAM on data lane [31:0] - CS0 */
/* pin tri-stated = 1 */
writel(0x00000100, OMAP3_SDRC_REG(SHARING));
/* ----- SDRC Registers Configuration --------- */
/* SDRC_MCFG0 register */
writel(0x02584099, OMAP3_SDRC_REG(MCFG_0));
/* SDRC_RFR_CTRL0 register */
writel(0x54601, OMAP3_SDRC_REG(RFR_CTRL_0));
/* SDRC_ACTIM_CTRLA0 register */
writel(0xA29DB4C6, OMAP3_SDRC_REG(ACTIM_CTRLA_0));
/* SDRC_ACTIM_CTRLB0 register */
writel(0x12214, OMAP3_SDRC_REG(ACTIM_CTRLB_0));
/* Disble Power Down of CKE due to 1 CKE on combo part */
writel(0x00000081, OMAP3_SDRC_REG(POWER));
/* SDRC_MANUAL command register */
/* NOP command */
writel(0x00000000, OMAP3_SDRC_REG(MANUAL_0));
/* Precharge command */
writel(0x00000001, OMAP3_SDRC_REG(MANUAL_0));
/* Auto-refresh command */
writel(0x00000002, OMAP3_SDRC_REG(MANUAL_0));
/* Auto-refresh command */
writel(0x00000002, OMAP3_SDRC_REG(MANUAL_0));
/* SDRC MR0 register Burst length=4 */
writel(0x00000032, OMAP3_SDRC_REG(MR_0));
/* SDRC DLLA control register */
writel(0x0000000A, OMAP3_SDRC_REG(DLLA_CTRL));
return;
}
/**
* @brief Do the SDRC initialization for 128Meg Infenion DDR for CS0
*
* @return void
*/
static void sdrc_init(void)
{
/* Issue SDRC Soft reset */
writel(0x12, OMAP3_SDRC_REG(SYSCONFIG));
/* Wait until Reset complete */
while ((readl(OMAP3_SDRC_REG(STATUS)) & 0x1) == 0);
/* SDRC to normal mode */
writel(0x10, OMAP3_SDRC_REG(SYSCONFIG));
/* SDRC Sharing register */
/* 32-bit SDRAM on data lane [31:0] - CS0 */
/* pin tri-stated = 1 */
writel(0x00000100, OMAP3_SDRC_REG(SHARING));
/* ----- SDRC_REG(CS0 Configuration --------- */
/* SDRC_REG(MCFG0 register */
writel(0x02584019, OMAP3_SDRC_REG(MCFG_0));
/* SDRC_REG(RFR_CTRL0 register */
writel(0x0003DE01, OMAP3_SDRC_REG(RFR_CTRL_0));
/* SDRC_REG(ACTIM_CTRLA0 register */
writel(0X5A9A4486, OMAP3_SDRC_REG(ACTIM_CTRLA_0));
/* SDRC_REG(ACTIM_CTRLB0 register */
writel(0x00000010, OMAP3_SDRC_REG(ACTIM_CTRLB_0));
/* Disble Power Down of CKE cuz of 1 CKE on combo part */
writel(0x00000081, OMAP3_SDRC_REG(POWER));
/* SDRC_REG(Manual command register */
/* NOP command */
writel(0x00000000, OMAP3_SDRC_REG(MANUAL_0));
/* Precharge command */
writel(0x00000001, OMAP3_SDRC_REG(MANUAL_0));
/* Auto-refresh command */
writel(0x00000002, OMAP3_SDRC_REG(MANUAL_0));
/* Auto-refresh command */
writel(0x00000002, OMAP3_SDRC_REG(MANUAL_0));
/* SDRC MR0 register */
/* CAS latency = 3 */
/* Write Burst = Read Burst */
/* Serial Mode */
writel(0x00000032, OMAP3_SDRC_REG(MR_0)); /* Burst length =4 */
/* SDRC DLLA control register */
/* Enable DLL A */
writel(0x0000000A, OMAP3_SDRC_REG(DLLA_CTRL));
/* wait until DLL is locked */
while ((readl(OMAP3_SDRC_REG(DLLA_STATUS)) & 0x4) == 0);
}
