static int __init init_soleng_maps(void)
{
int nr_parts = 0;
/* First probe at offset 0 */
soleng_flash_map.phys = 0;
soleng_flash_map.virt = (void __iomem *)P2SEGADDR(0);
soleng_eprom_map.phys = 0x01000000;
soleng_eprom_map.virt = (void __iomem *)P1SEGADDR(0x01000000);
simple_map_init(&soleng_eprom_map);
simple_map_init(&soleng_flash_map);
printk(KERN_NOTICE "Probing for flash chips at 0x00000000:\n");
flash_mtd = do_map_probe("cfi_probe", &soleng_flash_map);
if (!flash_mtd) {
/* Not there. Try swapping */
printk(KERN_NOTICE "Probing for flash chips at 0x01000000:\n");
soleng_flash_map.phys = 0x01000000;
soleng_flash_map.virt = P2SEGADDR(0x01000000);
soleng_eprom_map.phys = 0;
soleng_eprom_map.virt = P1SEGADDR(0);
flash_mtd = do_map_probe("cfi_probe", &soleng_flash_map);
if (!flash_mtd) {
/* Eep. */
printk(KERN_NOTICE "Flash chips not detected at either possible location.\n");
return -ENXIO;
}
}
printk(KERN_NOTICE "Solution Engine: Flash at 0x%08lx, EPROM at 0x%08lx\n",
soleng_flash_map.phys & 0x1fffffff,
soleng_eprom_map.phys & 0x1fffffff);
flash_mtd->owner = THIS_MODULE;
eprom_mtd = do_map_probe("map_rom", &soleng_eprom_map);
if (eprom_mtd) {
eprom_mtd->owner = THIS_MODULE;
add_mtd_device(eprom_mtd);
}
nr_parts = parse_mtd_partitions(flash_mtd, probes, &parsed_parts, 0);
#ifdef CONFIG_MTD_SUPERH_RESERVE
if (nr_parts <= 0) {
printk(KERN_NOTICE "Using configured partition at 0x%08x.\n",
CONFIG_MTD_SUPERH_RESERVE);
parsed_parts = superh_se_partitions;
nr_parts = sizeof(superh_se_partitions)/sizeof(*parsed_parts);
}
#endif /* CONFIG_MTD_SUPERH_RESERVE */
if (nr_parts > 0)
add_mtd_partitions(flash_mtd, parsed_parts, nr_parts);
else
add_mtd_device(flash_mtd);
return 0;
}
/*
* Re-map an arbitrary physical address space into the kernel virtual
* address space. Needed when the kernel wants to access physical
* memory directly.
*/
void __iomem *__ioremap(unsigned long phys_addr, size_t size,
unsigned long flags)
{
unsigned long addr;
struct vm_struct *area;
unsigned long offset, last_addr;
pgprot_t prot;
/*
* Check if we can simply use the P4 segment. This area is
* uncacheable, so if caching/buffering is requested, we can't
* use it.
*/
if ((phys_addr >= P4SEG) && (flags == 0))
return (void __iomem *)phys_addr;
/* Don't allow wraparound or zero size */
last_addr = phys_addr + size - 1;
if (!size || last_addr < phys_addr)
return NULL;
/*
* XXX: When mapping regular RAM, we'd better make damn sure
* it's never used for anything else. But this is really the
* caller's responsibility...
*/
if (PHYSADDR(P2SEGADDR(phys_addr)) == phys_addr)
return (void __iomem *)P2SEGADDR(phys_addr);
/* Mappings have to be page-aligned */
offset = phys_addr & ~PAGE_MASK;
phys_addr &= PAGE_MASK;
size = PAGE_ALIGN(last_addr + 1) - phys_addr;
prot = __pgprot(_PAGE_PRESENT | _PAGE_GLOBAL | _PAGE_RW | _PAGE_DIRTY
| _PAGE_ACCESSED | _PAGE_TYPE_SMALL | flags);
/*
* Ok, go for it..
*/
area = get_vm_area(size, VM_IOREMAP);
if (!area)
return NULL;
area->phys_addr = phys_addr;
addr = (unsigned long )area->addr;
if (ioremap_page_range(addr, addr + size, phys_addr, prot)) {
vunmap((void *)addr);
return NULL;
}
return (void __iomem *)(offset + (char *)addr);
}
/*
* Do not allocate memory (or fail in any way) in machine_kexec().
* We are past the point of no return, committed to rebooting now.
*/
void machine_kexec(struct kimage *image)
{
unsigned long page_list;
unsigned long reboot_code_buffer;
unsigned long vbr_reg;
relocate_new_kernel_t rnk;
#if defined(CONFIG_SH_STANDARD_BIOS)
vbr_reg = ((unsigned long )gdb_vbr_vector) - 0x100;
#else
vbr_reg = 0x80000000; // dummy
#endif
/* Interrupts aren't acceptable while we reboot */
local_irq_disable();
page_list = image->head;
/* we need both effective and real address here */
reboot_code_buffer =
(unsigned long)page_address(image->control_code_page);
/* copy our kernel relocation code to the control code page */
memcpy((void *)reboot_code_buffer, relocate_new_kernel,
relocate_new_kernel_size);
kexec_info(image);
flush_cache_all();
/* now call it */
rnk = (relocate_new_kernel_t) reboot_code_buffer;
(*rnk)(page_list, reboot_code_buffer, P2SEGADDR(image->start), vbr_reg);
}
static int __init init_soleng_maps(void)
{
int nr_parts;
/* First probe at offset 0 */
soleng_flash_map.map_priv_1 = P2SEGADDR(0);
soleng_eprom_map.map_priv_1 = P1SEGADDR(0x400000);
printk(KERN_NOTICE "Probing for flash chips at 0x000000:\n");
flash_mtd = do_map_probe("cfi_probe", &soleng_flash_map);
if (!flash_mtd) {
/* Not there. Try swapping */
printk(KERN_NOTICE "Probing for flash chips at 0x400000:\n");
soleng_flash_map.map_priv_1 = P2SEGADDR(0x400000);
soleng_eprom_map.map_priv_1 = P1SEGADDR(0);
flash_mtd = do_map_probe("cfi_probe", &soleng_flash_map);
if (!flash_mtd) {
/* Eep. */
printk(KERN_NOTICE "Flash chips not detected at either possible location.\n");
return -ENXIO;
}
}
printk(KERN_NOTICE "Solution Engine: Flash at 0x%08lx, EPROM at 0x%08lx\n",
soleng_flash_map.map_priv_1 & 0x1fffffff,
soleng_eprom_map.map_priv_1 & 0x1fffffff);
flash_mtd->module = THIS_MODULE;
eprom_mtd = do_map_probe("map_rom", &soleng_eprom_map);
if (eprom_mtd) {
eprom_mtd->module = THIS_MODULE;
add_mtd_device(eprom_mtd);
}
nr_parts = parse_redboot_partitions(flash_mtd, &parsed_parts);
if (nr_parts)
add_mtd_partitions(flash_mtd, parsed_parts, nr_parts);
else
add_mtd_device(flash_mtd);
return 0;
}
static int __init init_soleng_maps(void)
{
/* First probe at offset 0 */
soleng_flash_map.phys = 0;
soleng_flash_map.virt = (void __iomem *)P2SEGADDR(0);
soleng_eprom_map.phys = 0x01000000;
soleng_eprom_map.virt = (void __iomem *)P1SEGADDR(0x01000000);
simple_map_init(&soleng_eprom_map);
simple_map_init(&soleng_flash_map);
printk(KERN_NOTICE "Probing for flash chips at 0x00000000:\n");
flash_mtd = do_map_probe("cfi_probe", &soleng_flash_map);
if (!flash_mtd) {
/* Not there. Try swapping */
printk(KERN_NOTICE "Probing for flash chips at 0x01000000:\n");
soleng_flash_map.phys = 0x01000000;
soleng_flash_map.virt = P2SEGADDR(0x01000000);
soleng_eprom_map.phys = 0;
soleng_eprom_map.virt = P1SEGADDR(0);
flash_mtd = do_map_probe("cfi_probe", &soleng_flash_map);
if (!flash_mtd) {
/* Eep. */
printk(KERN_NOTICE "Flash chips not detected at either possible location.\n");
return -ENXIO;
}
}
printk(KERN_NOTICE "Solution Engine: Flash at 0x%08lx, EPROM at 0x%08lx\n",
soleng_flash_map.phys & 0x1fffffff,
soleng_eprom_map.phys & 0x1fffffff);
flash_mtd->owner = THIS_MODULE;
eprom_mtd = do_map_probe("map_rom", &soleng_eprom_map);
if (eprom_mtd) {
eprom_mtd->owner = THIS_MODULE;
mtd_device_register(eprom_mtd, NULL, 0);
}
mtd_device_parse_register(flash_mtd, probes, NULL,
superh_se_partitions, NUM_PARTITIONS);
return 0;
}
void *pci_alloc_consistent(struct pci_dev *hwdev, size_t size,
dma_addr_t * dma_handle)
{
void *ret;
int gfp = GFP_ATOMIC;
ret = (void *) __get_free_pages(gfp, get_order(size));
if (ret != NULL) {
/* Is it neccessary to do the memset? */
memset(ret, 0, size);
*dma_handle = virt_to_bus(ret);
}
/* We must flush the cache before we pass it on to the device */
flush_cache_all();
return P2SEGADDR(ret);
}
void *pci_alloc_consistent(struct pci_dev *hwdev, size_t size,
dma_addr_t * dma_handle)
{
unsigned long buf;
if (gapspci_dma_used+size > GAPSPCI_DMA_SIZE)
return NULL;
buf = GAPSPCI_DMA_BASE+gapspci_dma_used;
gapspci_dma_used = PAGE_ALIGN(gapspci_dma_used+size);
printk("pci_alloc_consistent: %ld bytes at 0x%lx\n", (long)size, buf);
*dma_handle = (dma_addr_t)buf;
return (void *)P2SEGADDR(buf);
}
unsigned long bigsur_isa_port2addr(unsigned long port)
{
unsigned long addr = 0;
unsigned char shift;
/* Physical address not in P0, do nothing */
if (PXSEG(port)) addr = port;
/* physical address in P0, map to P2 */
else if (port >= 0x30000)
addr = P2SEGADDR(port);
/* Big Sur I/O + HD64465 registers 0x10000-0x30000 */
else if (port >= BIGSUR_IOMAP_HI_THRESH)
addr = BIGSUR_INTERNAL_BASE + (port - BIGSUR_IOMAP_HI_THRESH);
/* Handle remapping of high IO/PCI IO ports */
else if (port >= BIGSUR_IOMAP_LO_THRESH) {
addr = bigsur_iomap_hi[port >> BIGSUR_IOMAP_HI_SHIFT];
shift = bigsur_iomap_hi_shift[port >> BIGSUR_IOMAP_HI_SHIFT];
if (addr != 0)
addr += (port & BIGSUR_IOMAP_HI_MASK) << shift;
}
static int __init init_mpc1211_maps(void)
{
int nr_parts;
mpc1211_flash_map.phys = 0;
mpc1211_flash_map.virt = (void __iomem *)P2SEGADDR(0);
simple_map_init(&mpc1211_flash_map);
printk(KERN_NOTICE "Probing for flash chips at 0x00000000:\n");
flash_mtd = do_map_probe("jedec_probe", &mpc1211_flash_map);
if (!flash_mtd) {
printk(KERN_NOTICE "Flash chips not detected at either possible location.\n");
return -ENXIO;
}
printk(KERN_NOTICE "MPC-1211: Flash at 0x%08lx\n", mpc1211_flash_map.virt & 0x1fffffff);
flash_mtd->module = THIS_MODULE;
parsed_parts = mpc1211_partitions;
nr_parts = ARRAY_SIZE(mpc1211_partitions);
add_mtd_partitions(flash_mtd, parsed_parts, nr_parts);
return 0;
}
void *dreamcast_consistent_alloc(struct device *dev, size_t size,
dma_addr_t *dma_handle, gfp_t flag)
{
unsigned long buf;
if (dev && dev->bus != &pci_bus_type)
return NULL;
if (gapspci_dma_used + size > GAPSPCI_DMA_SIZE)
return ERR_PTR(-EINVAL);
buf = GAPSPCI_DMA_BASE + gapspci_dma_used;
gapspci_dma_used = PAGE_ALIGN(gapspci_dma_used+size);
*dma_handle = (dma_addr_t)buf;
buf = P2SEGADDR(buf);
/* Flush the dcache before we hand off the buffer */
__flush_purge_region((void *)buf, size);
return (void *)buf;
}
void * generic_ioremap(unsigned long offset, unsigned long size)
{
return (void *) P2SEGADDR(offset);
}
/*
* Initialize the SnapGear PCI interface
* Setup hardware to be Central Funtion
* Copy the BSR regs to the PCI interface
* Setup PCI windows into local RAM
*/
int __init pcibios_init_platform(void) {
u32 reg;
u32 word;
u32 id;
PCIDBG(1,"PCI: snapgear_pci_init called\n");
/* Set the BCR's to enable PCI access */
reg = inl(SH7751_BCR1);
reg |= 0x80000;
outl(reg, SH7751_BCR1);
/* check for SH7751/SH7751R hardware */
id = inl(SH7751_PCIREG_BASE+SH7751_PCICONF0);
switch (id) {
case (SH7751_DEVICE_ID << 16) | SH7751_VENDOR_ID:
printk("PCI: SH7751 PCI host bridge found.\n");
break;
case (SH7751R_DEVICE_ID << 16) | SH7751_VENDOR_ID:
printk("PCI: SH7751R PCI host bridge found.\n");
break;
default:
printk("PCI: Unknown PCI host bridge (id=0x%x).\n", id);
return(0);
}
/* Turn the clocks back on (not done in reset)*/
outl(0, PCI_REG(SH7751_PCICLKR));
/* Clear Powerdown IRQ's (not done in reset) */
word = SH7751_PCIPINT_D3 | SH7751_PCIPINT_D0;
outl(word, PCI_REG(SH7751_PCICLKR));
#if 0
/*
* This code is removed as it is done in the bootloader and doing it
* here means the MAC addresses loaded by the bootloader get lost
*/
/* toggle PCI reset pin */
word = SH7751_PCICR_PREFIX | SH7751_PCICR_PRST;
outl(word,PCI_REG(SH7751_PCICR));
/* Wait for a long time... not 1 sec. but long enough */
mdelay(100);
word = SH7751_PCICR_PREFIX;
outl(word,PCI_REG(SH7751_PCICR));
#endif
/* set the command/status bits to:
* Wait Cycle Control + Parity Enable + Bus Master +
* Mem space enable
*/
word = SH7751_PCICONF1_WCC | SH7751_PCICONF1_PER |
SH7751_PCICONF1_BUM | SH7751_PCICONF1_MES;
outl(word, PCI_REG(SH7751_PCICONF1));
/* define this host as the host bridge */
word = SH7751_PCI_HOST_BRIDGE << 24;
outl(word, PCI_REG(SH7751_PCICONF2));
/* Set IO and Mem windows to local address
* Make PCI and local address the same for easy 1 to 1 mapping
* Window0 = SNAPGEAR_LSR0_SIZE @ non-cached CS2 base = SDRAM
* Window1 = SNAPGEAR_LSR1_SIZE @ cached CS2 base = SDRAM
*/
word = SNAPGEAR_LSR0_SIZE - 1;
outl(word, PCI_REG(SH7751_PCILSR0));
word = SNAPGEAR_LSR1_SIZE - 1;
outl(word, PCI_REG(SH7751_PCILSR1));
/* Set the values on window 0 PCI config registers */
word = P2SEGADDR(SH7751_CS2_BASE_ADDR);
outl(word, PCI_REG(SH7751_PCILAR0));
outl(word, PCI_REG(SH7751_PCICONF5));
/* Set the values on window 1 PCI config registers */
word = PHYSADDR(SH7751_CS2_BASE_ADDR);
outl(word, PCI_REG(SH7751_PCILAR1));
outl(word, PCI_REG(SH7751_PCICONF6));
/* Set the local 16MB PCI memory space window to
* the lowest PCI mapped address
*/
word = PCIBIOS_MIN_MEM & SH7751_PCIMBR_MASK;
PCIDBG(2,"PCI: Setting upper bits of Memory window to 0x%x\n", word);
outl(word , PCI_REG(SH7751_PCIMBR));
/* Map IO space into PCI IO window
* The IO window is 64K-PCIBIOS_MIN_IO in size
* IO addresses will be translated to the
* PCI IO window base address
*/
PCIDBG(3,"PCI: Mapping IO address 0x%x - 0x%x to base 0x%x\n", PCIBIOS_MIN_IO,
(64*1024), SH7751_PCI_IO_BASE+PCIBIOS_MIN_IO);
/* Make sure the MSB's of IO window are set to access PCI space correctly */
word = PCIBIOS_MIN_IO & SH7751_PCIIOBR_MASK;
PCIDBG(2,"PCI: Setting upper bits of IO window to 0x%x\n", word);
outl(word, PCI_REG(SH7751_PCIIOBR));
/* Set PCI WCRx, BCRx's, copy from BSC locations */
word = inl(SH7751_BCR1);
/* check BCR for SDRAM in area 3 */
if(((word >> 2) & 1) == 0) {
printk("PCI: Area 2 is not configured for SDRAM. BCR1=0x%x\n", word);
return 0;
}
outl(word, PCI_REG(SH7751_PCIBCR1));
word = (u16)inw(SH7751_BCR2);
/* check BCR2 for 32bit SDRAM interface*/
if(((word >> 4) & 0x3) != 0x3) {
printk("PCI: Area 2 is not 32 bit SDRAM. BCR2=0x%x\n", word);
return 0;
}
outl(word, PCI_REG(SH7751_PCIBCR2));
/* configure the wait control registers */
word = inl(SH7751_WCR1);
outl(word, PCI_REG(SH7751_PCIWCR1));
word = inl(SH7751_WCR2);
outl(word, PCI_REG(SH7751_PCIWCR2));
word = inl(SH7751_WCR3);
outl(word, PCI_REG(SH7751_PCIWCR3));
word = inl(SH7751_MCR);
outl(word, PCI_REG(SH7751_PCIMCR));
/* NOTE: I'm ignoring the PCI error IRQs for now..
* TODO: add support for the internal error interrupts and
* DMA interrupts...
*/
/* SH7751 init done, set central function init complete */
/* use round robin mode to stop a device starving/overruning */
word = SH7751_PCICR_PREFIX | SH7751_PCICR_CFIN | SH7751_PCICR_ARBM;
outl(word,PCI_REG(SH7751_PCICR));
PCIDBG(2,"PCI: snapgear_pci_init finished\n");
return 1;
}
static void sh7785lcr_power_off(void)
{
ctrl_outb(0x01, P2SEGADDR(PLD_POFCR));
}
/* FPGA Reed-Solomon ECC check register */
#define RTC_FROM4_RS_ECC_CHK (RTC_FROM4_NAND_ADDR_FPGA | 0x00000070)
#define RTC_FROM4_RS_ECC_CHK_ERROR (1 << 7)
#define ERR_STAT_ECC_AVAILABLE 0x20
/* Undefine for software ECC */
#define RTC_FROM4_HWECC 1
/* Define as 1 for no virtual erase blocks (in JFFS2) */
#define RTC_FROM4_NO_VIRTBLOCKS 0
/*
* Module stuff
*/
static void __iomem *rtc_from4_fio_base = (void *)P2SEGADDR(RTC_FROM4_FIO_BASE);
static const struct mtd_partition partition_info[] = {
{
.name = "Renesas flash partition 1",
.offset = 0,
.size = MTDPART_SIZ_FULL},
};
#define NUM_PARTITIONS 1
/*
* hardware specific flash bbt decriptors
* Note: this is to allow debugging by disabling
* NAND_BBT_CREATE and/or NAND_BBT_WRITE
*
int __init sh7780_pcic_init(struct sh4_pci_address_map *map)
{
u32 word;
/*
* This code is unused for some boards as it is done in the
* bootloader and doing it here means the MAC addresses loaded
* by the bootloader get lost.
*/
if (!(map->flags & SH4_PCIC_NO_RESET)) {
/* toggle PCI reset pin */
word = SH4_PCICR_PREFIX | SH4_PCICR_PRST;
pci_write_reg(word, SH4_PCICR);
/* Wait for a long time... not 1 sec. but long enough */
mdelay(100);
word = SH4_PCICR_PREFIX;
pci_write_reg(word, SH4_PCICR);
}
/* set the command/status bits to:
* Wait Cycle Control + Parity Enable + Bus Master +
* Mem space enable
*/
pci_write_reg(0x00000046, SH7780_PCICMD);
/* define this host as the host bridge */
word = PCI_BASE_CLASS_BRIDGE << 24;
pci_write_reg(word, SH7780_PCIRID);
/* Set IO and Mem windows to local address
* Make PCI and local address the same for easy 1 to 1 mapping
* Window0 = map->window0.size @ non-cached area base = SDRAM
* Window1 = map->window1.size @ cached area base = SDRAM
*/
word = ((map->window0.size - 1) & 0x1ff00001) | 0x01;
pci_write_reg(0x07f00001, SH4_PCILSR0);
word = ((map->window1.size - 1) & 0x1ff00001) | 0x01;
pci_write_reg(0x00000001, SH4_PCILSR1);
/* Set the values on window 0 PCI config registers */
word = P2SEGADDR(map->window0.base);
pci_write_reg(0xa8000000, SH4_PCILAR0);
pci_write_reg(0x08000000, SH7780_PCIMBAR0);
/* Set the values on window 1 PCI config registers */
word = P2SEGADDR(map->window1.base);
pci_write_reg(0x00000000, SH4_PCILAR1);
pci_write_reg(0x00000000, SH7780_PCIMBAR1);
/* Map IO space into PCI IO window
* The IO window is 64K-PCIBIOS_MIN_IO in size
* IO addresses will be translated to the
* PCI IO window base address
*/
pr_debug("PCI: Mapping IO address 0x%x - 0x%x to base 0x%x\n",
PCIBIOS_MIN_IO, (64 << 10),
SH7780_PCI_IO_BASE + PCIBIOS_MIN_IO);
/* NOTE: I'm ignoring the PCI error IRQs for now..
* TODO: add support for the internal error interrupts and
* DMA interrupts...
*/
/* Apply any last-minute PCIC fixups */
pci_fixup_pcic();
/* SH7780 init done, set central function init complete */
/* use round robin mode to stop a device starving/overruning */
word = SH4_PCICR_PREFIX | SH4_PCICR_CFIN | SH4_PCICR_FTO;
pci_write_reg(word, SH4_PCICR);
return 1;
}
