* GNU General Public License for more details. */ #include <commonlib/helpers.h> #include <baseboard/variants.h> /* * Pad configuration in ramstage. The order largely follows the 'GPIO Muxing' * table found in EDS vol 1, but some pins aren't grouped functionally in * the table so those were moved for more logical grouping. */ static const struct pad_config gpio_table[] = { /* Southwest Community */ /* PCIE_WAKE[0:3]_N - unused */ PAD_CFG_GPI(GPIO_205, UP_20K, DEEP), PAD_CFG_GPI(GPIO_206, UP_20K, DEEP), PAD_CFG_GPI(GPIO_207, UP_20K, DEEP), PAD_CFG_GPI(GPIO_208, UP_20K, DEEP), /* EMMC interface. */ PAD_CFG_NF(GPIO_156, DN_20K, DEEP, NF1), /* EMMC_CLK */ PAD_CFG_NF(GPIO_157, UP_20K, DEEP, NF1), /* EMMC_D0 */ PAD_CFG_NF(GPIO_158, UP_20K, DEEP, NF1), /* EMMC_D1 */ PAD_CFG_NF(GPIO_159, UP_20K, DEEP, NF1), /* EMMC_D2 */ PAD_CFG_NF(GPIO_160, UP_20K, DEEP, NF1), /* EMMC_D3 */ PAD_CFG_NF(GPIO_161, UP_20K, DEEP, NF1), /* EMMC_D4 */ PAD_CFG_NF(GPIO_162, UP_20K, DEEP, NF1), /* EMMC_D5 */ PAD_CFG_NF(GPIO_163, UP_20K, DEEP, NF1), /* EMMC_D6 */ PAD_CFG_NF(GPIO_164, UP_20K, DEEP, NF1), /* EMMC_D7 */ PAD_CFG_NF(GPIO_165, UP_20K, DEEP, NF1), /* EMMC_CMD */
/* SUSACK# */ PAD_NC(GPP_A15, NONE), /* SD_1P8_SEL */ PAD_NC(GPP_A16, NONE), /* SD_PWR_EN# */ PAD_NC(GPP_A17, NONE), /* ISH_GP0 */ PAD_NC(GPP_A18, NONE), /* ISH_GP1 */ PAD_NC(GPP_A19, NONE), /* ISH_GP2 */ PAD_NC(GPP_A20, NONE), /* ISH_GP3 */ PAD_NC(GPP_A21, NONE), /* ISH_GP4 */ PAD_NC(GPP_A22, NONE), /* ISH_GP5 */ PAD_NC(GPP_A23, NONE), /* CORE_VID0 */ /* CORE_VID1 */ /* VRALERT# */ PAD_NC(GPP_B2, NONE), /* CPU_GP2 */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST, EDGE_SINGLE, INVERT), /* TOUCHPAD_INTR# */ /* CPU_GP3 */ PAD_CFG_GPI(GPP_B4, NONE, DEEP), /* TOUCH_SCREEN_DET# */ /* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), /* CLKREQ_PCIE#0 */ /* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* CLKREQ_PCIE#1 */ /* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* CLKREQ_PCIE#2 */ /* SRCCLKREQ3# */ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), /* CLKREQ_PCIE#3 */ /* SRCCLKREQ4# */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), /* CLKREQ_PCIE#4 */ /* SRCCLKREQ5# */ PAD_NC(GPP_B10, NONE), /* EXT_PWR_GATE# */ PAD_CFG_GPO(GPP_B11, 0, DEEP), /* 3.3V_CAM_EN# */ /* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* SPKR */ PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), /* GSPI0_CS# */ PAD_NC(GPP_B15, NONE), /* GSPI0_CLK */ PAD_NC(GPP_B16, NONE), /* GSPI0_MISO */ PAD_NC(GPP_B17, NONE), /* GSPI0_MOSI */ PAD_NC(GPP_B18, NONE), /* GSPI1_CS# */ PAD_NC(GPP_B19, NONE), /* HDD_FALL_INT (nostuff) */
* GNU General Public License for more details. */ #include <baseboard/gpio.h> #include <baseboard/variants.h> #include <commonlib/helpers.h> /* * Pad configuration in ramstage. The order largely follows the 'GPIO Muxing' * table found in EDS vol 1, but some pins aren't grouped functionally in * the table so those were moved for more logical grouping. */ static const struct pad_config gpio_table[] = { /* PCIE_WAKE[0:3]_N */ PAD_CFG_NF(GPIO_205, UP_20K, DEEP, NF1), /* WLAN */ PAD_CFG_GPI(GPIO_206, UP_20K, DEEP), /* Unused */ PAD_CFG_GPI(GPIO_207, UP_20K, DEEP), /* Unused */ PAD_CFG_GPI(GPIO_208, UP_20K, DEEP), /* Unused */ /* EMMC interface */ PAD_CFG_NF(GPIO_156, DN_20K, DEEP, NF1), /* EMMC_CLK */ PAD_CFG_NF(GPIO_157, UP_20K, DEEP, NF1), /* EMMC_D0 */ PAD_CFG_NF(GPIO_158, UP_20K, DEEP, NF1), /* EMMC_D1 */ PAD_CFG_NF(GPIO_159, UP_20K, DEEP, NF1), /* EMMC_D2 */ PAD_CFG_NF(GPIO_160, UP_20K, DEEP, NF1), /* EMMC_D3 */ PAD_CFG_NF(GPIO_161, UP_20K, DEEP, NF1), /* EMMC_D4 */ PAD_CFG_NF(GPIO_162, UP_20K, DEEP, NF1), /* EMMC_D5 */ PAD_CFG_NF(GPIO_163, UP_20K, DEEP, NF1), /* EMMC_D6 */ PAD_CFG_NF(GPIO_164, UP_20K, DEEP, NF1), /* EMMC_D7 */ PAD_CFG_NF(GPIO_165, UP_20K, DEEP, NF1), /* EMMC_CMD */ PAD_CFG_NF(GPIO_182, DN_20K, DEEP, NF1), /* EMMC_RCLK */