void
gscpcib_attach(struct device *parent, struct device *self, void *aux)
{
#ifndef SMALL_KERNEL
struct gscpcib_softc *sc = (struct gscpcib_softc *)self;
struct pci_attach_args *pa = aux;
struct gpiobus_attach_args gba;
pcireg_t gpiobase;
int i;
int gpio_present = 0;
/* Map GPIO I/O space */
gpiobase = pci_conf_read(pa->pa_pc, pa->pa_tag, GSCGPIO_BASE);
sc->sc_gpio_iot = pa->pa_iot;
if (PCI_MAPREG_IO_ADDR(gpiobase) == 0 ||
bus_space_map(sc->sc_gpio_iot, PCI_MAPREG_IO_ADDR(gpiobase),
GSCGPIO_SIZE, 0, &sc->sc_gpio_ioh)) {
printf(": failed to map GPIO I/O space");
goto corepcib;
}
/* Initialize pins array */
for (i = 0; i < GSCGPIO_NPINS; i++) {
sc->sc_gpio_pins[i].pin_num = i;
sc->sc_gpio_pins[i].pin_caps = GPIO_PIN_INPUT |
GPIO_PIN_OUTPUT | GPIO_PIN_OPENDRAIN |
GPIO_PIN_PUSHPULL | GPIO_PIN_TRISTATE |
GPIO_PIN_PULLUP;
/* Read initial state */
sc->sc_gpio_pins[i].pin_state = gscpcib_gpio_pin_read(sc, i) ?
GPIO_PIN_HIGH : GPIO_PIN_LOW;
}
/* Create controller tag */
sc->sc_gpio_gc.gp_cookie = sc;
sc->sc_gpio_gc.gp_pin_read = gscpcib_gpio_pin_read;
sc->sc_gpio_gc.gp_pin_write = gscpcib_gpio_pin_write;
sc->sc_gpio_gc.gp_pin_ctl = gscpcib_gpio_pin_ctl;
gba.gba_name = "gpio";
gba.gba_gc = &sc->sc_gpio_gc;
gba.gba_pins = sc->sc_gpio_pins;
gba.gba_npins = GSCGPIO_NPINS;
gpio_present = 1;
corepcib:
#endif /* !SMALL_KERNEL */
/* Provide core pcib(4) functionality */
pcibattach(parent, self, aux);
#ifndef SMALL_KERNEL
/* Attach GPIO framework */
if (gpio_present)
config_found(&sc->sc_dev, &gba, gpiobus_print);
#endif /* !SMALL_KERNEL */
}
bus_addr_t
pciaddr_ioaddr(u_int32_t val)
{
return ((PCI_MAPREG_TYPE(val) == PCI_MAPREG_TYPE_MEM)
? PCI_MAPREG_MEM_ADDR(val)
: (PCI_MAPREG_IO_ADDR(val) & PCIADDR_PORT_END));
}
bus_addr_t
pciaddr_ioaddr(uint32_t val)
{
return (PCI_MAPREG_TYPE(val) == PCI_MAPREG_TYPE_MEM)
? PCI_MAPREG_MEM_ADDR(val)
: PCI_MAPREG_IO_ADDR(val);
}
static int
pci_io_find(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t type,
bus_addr_t *basep, bus_size_t *sizep, int *flagsp)
{
pcireg_t address, mask;
int s;
if (reg < PCI_MAPREG_START ||
#if 0
/*
* Can't do this check; some devices have mapping registers
* way out in left field.
*/
reg >= PCI_MAPREG_END ||
#endif
(reg & 3))
panic("pci_io_find: bad request");
/*
* Section 6.2.5.1, `Address Maps', tells us that:
*
* 1) The builtin software should have already mapped the device in a
* reasonable way.
*
* 2) A device which wants 2^n bytes of memory will hardwire the bottom
* n bits of the address to 0. As recommended, we write all 1s and see
* what we get back.
*/
s = splhigh();
address = pci_conf_read(pc, tag, reg);
pci_conf_write(pc, tag, reg, 0xffffffff);
mask = pci_conf_read(pc, tag, reg);
pci_conf_write(pc, tag, reg, address);
splx(s);
if (PCI_MAPREG_TYPE(address) != PCI_MAPREG_TYPE_IO) {
aprint_debug("pci_io_find: expected type i/o, found mem\n");
return (1);
}
if (PCI_MAPREG_IO_SIZE(mask) == 0) {
aprint_debug("pci_io_find: void region\n");
return (1);
}
if (basep != 0)
*basep = PCI_MAPREG_IO_ADDR(address);
if (sizep != 0)
*sizep = PCI_MAPREG_IO_SIZE(mask);
if (flagsp != 0)
*flagsp = 0;
return (0);
}
void
gscpm_attach(struct device *parent, struct device *self, void *aux)
{
struct gscpm_softc *sc = (struct gscpm_softc *)self;
struct pci_attach_args *pa = aux;
pcireg_t csr, acpibase;
sc->sc_pc = pa->pa_pc;
sc->sc_tag = pa->pa_tag;
sc->sc_iot = pa->pa_iot;
/* Enable I/O space */
csr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG);
pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG,
csr | PCI_COMMAND_IO_ENABLE);
/* Map ACPI registers */
acpibase = pci_conf_read(sc->sc_pc, sc->sc_tag, GSCPM_ACPIBASE);
if (PCI_MAPREG_IO_ADDR(acpibase) == 0 ||
bus_space_map(sc->sc_iot, PCI_MAPREG_IO_ADDR(acpibase),
GSCPM_ACPISIZE, 0, &sc->sc_acpi_ioh)) {
printf(": failed to map ACPI registers\n");
return;
}
printf("\n");
#ifdef __HAVE_TIMECOUNTER
/* Hook into the kern_tc */
gscpm_timecounter.tc_priv = sc;
tc_init(&gscpm_timecounter);
#endif /* __HAVE_TIMECOUNTER */
/* XXX: disabled due to unresolved yet hardware errata */
#if 0
/* Hook into the hw.setperf sysctl */
gscpm_cookie = sc;
cpu_setperf = gscpm_setperf;
#endif
}
/*
* Extract SMBus base address from SB800 Power Management (PM) registers.
* The PM registers can be accessed either through indirect I/O (CD6/CD7) or
* direct mapping if AcpiMMioDecodeEn is enabled. Since this function is only
* called once it uses indirect I/O for simplicity.
*/
static int
piixpm_sb800_init(struct piixpm_softc *sc)
{
bus_space_tag_t iot = sc->sc_iot;
bus_space_handle_t ioh; /* indirect I/O handle */
uint16_t val, base_addr;
/* Fetch SMB base address */
if (bus_space_map(iot,
PIIXPM_INDIRECTIO_BASE, PIIXPM_INDIRECTIO_SIZE, 0, &ioh)) {
device_printf(sc->sc_dev, "couldn't map indirect I/O space\n");
return EBUSY;
}
bus_space_write_1(iot, ioh, PIIXPM_INDIRECTIO_INDEX,
SB800_PM_SMBUS0EN_LO);
val = bus_space_read_1(iot, ioh, PIIXPM_INDIRECTIO_DATA);
bus_space_write_1(iot, ioh, PIIXPM_INDIRECTIO_INDEX,
SB800_PM_SMBUS0EN_HI);
val |= bus_space_read_1(iot, ioh, PIIXPM_INDIRECTIO_DATA) << 8;
sc->sc_sb800_ioh = ioh;
if ((val & SB800_PM_SMBUS0EN_ENABLE) == 0)
return ENOENT;
base_addr = val & SB800_PM_SMBUS0EN_BADDR;
aprint_debug_dev(sc->sc_dev, "SMBus @ 0x%04x\n", base_addr);
bus_space_write_1(iot, ioh, PIIXPM_INDIRECTIO_INDEX, SB800_PM_SMBUS0SELEN);
bus_space_write_1(iot, ioh, PIIXPM_INDIRECTIO_DATA, 1); /* SMBUS0SEL */
if (bus_space_map(iot, PCI_MAPREG_IO_ADDR(base_addr),
PIIX_SMB_SIZE, 0, &sc->sc_smb_ioh)) {
aprint_error_dev(sc->sc_dev, "can't map smbus I/O space\n");
return EBUSY;
}
aprint_normal_dev(sc->sc_dev, "polling (SB800)\n");
sc->sc_poll = 1;
return 0;
}
/*
* static int cardbus_io_find(cardbus_chipset_tag_t cc,
* cardbus_function_tag_t cf, pcitag_t tag,
* int reg, pcireg_t type, bus_addr_t *basep,
* bus_size_t *sizep, int *flagsp)
* This code is stolen from sys/dev/pci_map.c.
*/
static int
cardbus_io_find(
cardbus_chipset_tag_t cc,
cardbus_function_tag_t cf,
pcitag_t tag,
int reg,
pcireg_t type,
bus_addr_t *basep,
bus_size_t *sizep,
int *flagsp)
{
pcireg_t address, mask;
int s;
/* EXT ROM is able to map on memory space ONLY. */
if (reg == CARDBUS_ROM_REG) {
return 1;
}
if(reg < PCI_MAPREG_START || reg >= PCI_MAPREG_END || (reg & 3)) {
panic("cardbus_io_find: bad request");
}
/*
* Section 6.2.5.1, `Address Maps', tells us that:
*
* 1) The builtin software should have already mapped the device in a
* reasonable way.
*
* 2) A device which wants 2^n bytes of memory will hardwire the bottom
* n bits of the address to 0. As recommended, we write all 1s and see
* what we get back.
*/
s = splhigh();
address = cardbus_conf_read(cc, cf, tag, reg);
cardbus_conf_write(cc, cf, tag, reg, 0xffffffff);
mask = cardbus_conf_read(cc, cf, tag, reg);
cardbus_conf_write(cc, cf, tag, reg, address);
splx(s);
if (PCI_MAPREG_TYPE(address) != PCI_MAPREG_TYPE_IO) {
printf("cardbus_io_find: expected type i/o, found mem\n");
return 1;
}
if (PCI_MAPREG_IO_SIZE(mask) == 0) {
printf("cardbus_io_find: void region\n");
return 1;
}
if (basep != 0) {
*basep = PCI_MAPREG_IO_ADDR(address);
}
if (sizep != 0) {
*sizep = PCI_MAPREG_IO_SIZE(mask);
}
if (flagsp != 0) {
*flagsp = 0;
}
return 0;
}
static bus_addr_t
pucprobe_doit(struct consdev *cn)
{
struct pci_attach_args pa;
int bus;
static int dev = 0, func = 0;
int maxdev, nfunctions = 0, i; /* XXX */
pcireg_t reg, bhlcr, subsys = 0; /* XXX */
int foundport = 0;
const struct puc_device_description *desc;
pcireg_t base;
/* Fetch our tags */
if (cpu_comcnprobe(cn, &pa) != 0) {
return 0;
}
puctag = pa.pa_iot;
pci_decompose_tag(pa.pa_pc, pa.pa_tag, &bus, &maxdev, NULL);
/* scan through devices */
for (; dev <= maxdev ; dev++) {
pa.pa_tag = pci_make_tag(pa.pa_pc, bus, dev, 0);
reg = pci_conf_read(pa.pa_pc, pa.pa_tag, PCI_ID_REG);
if (PCI_VENDOR(reg) == PCI_VENDOR_INVALID
|| PCI_VENDOR(reg) == 0)
continue;
bhlcr = pci_conf_read(pa.pa_pc, pa.pa_tag, PCI_BHLC_REG);
if (PCI_HDRTYPE_MULTIFN(bhlcr)) {
nfunctions = 8;
} else {
nfunctions = 1;
}
resume_scan:
for (; func < nfunctions; func++) {
pa.pa_tag = pci_make_tag(pa.pa_pc, bus, dev, func);
reg = pci_conf_read(pa.pa_pc, pa.pa_tag, PCI_CLASS_REG);
if (PCI_CLASS(reg) == PCI_CLASS_COMMUNICATIONS
&& PCI_SUBCLASS(reg)
== PCI_SUBCLASS_COMMUNICATIONS_SERIAL) {
pa.pa_id = pci_conf_read(pa.pa_pc, pa.pa_tag, PCI_ID_REG);
subsys = pci_conf_read(pa.pa_pc, pa.pa_tag,
PCI_SUBSYS_ID_REG);
foundport = 1;
break;
}
}
if (foundport)
break;
func = 0;
}
if (!foundport)
return 0;
foundport = 0;
desc = puc_find_description(PCI_VENDOR(pa.pa_id),
PCI_PRODUCT(pa.pa_id), PCI_VENDOR(subsys), PCI_PRODUCT(subsys));
if (desc == NULL) {
func++;
goto resume_scan;
}
for (i = 0; PUC_PORT_VALID(desc, i); i++)
{
if (desc->ports[i].type != PUC_PORT_TYPE_COM)
continue;
base = pci_conf_read(pa.pa_pc, pa.pa_tag, desc->ports[i].bar);
base += desc->ports[i].offset;
if (PCI_MAPREG_TYPE(base) != PCI_MAPREG_TYPE_IO)
continue;
base = PCI_MAPREG_IO_ADDR(base);
if (com_is_console(puctag, base, NULL))
continue;
foundport = 1;
break;
}
if (foundport == 0) {
func++;
goto resume_scan;
}
cn->cn_pri = CN_REMOTE;
return PCI_MAPREG_IO_ADDR(base);
}
void
tcpcib_attach(struct device *parent, struct device *self, void *aux)
{
struct tcpcib_softc *sc = (struct tcpcib_softc *)self;
struct pci_attach_args *pa = aux;
struct timecounter *tc = &sc->sc_hpet_timecounter;
u_int32_t reg, wdtbase;
sc->sc_active = 0;
/* High Precision Event Timer */
sc->sc_hpet_iot = pa->pa_memt;
if (bus_space_map(sc->sc_hpet_iot, E600_HPET_BASE, E600_HPET_SIZE, 0,
&sc->sc_hpet_ioh) == 0) {
tc->tc_get_timecount = tcpcib_hpet_get_timecount;
/* XXX 64-bit counter is not supported! */
tc->tc_counter_mask = 0xffffffff;
reg = bus_space_read_4(sc->sc_hpet_iot, sc->sc_hpet_ioh,
E600_HPET_PERIOD);
/* femtosecs -> Hz */
tc->tc_frequency = 1000000000000000ULL / reg;
tc->tc_name = sc->sc_dev.dv_xname;
tc->tc_quality = 2000;
tc->tc_priv = sc;
tc_init(tc);
/* Enable counting */
bus_space_write_4(sc->sc_hpet_iot, sc->sc_hpet_ioh,
E600_HPET_GC, E600_HPET_GC_ENABLE);
sc->sc_active |= E600_HPET_ACTIVE;
printf(": %llu Hz timer", tc->tc_frequency);
}
/* Map Watchdog I/O space */
reg = pci_conf_read(pa->pa_pc, pa->pa_tag, E600_LPC_WDTBA);
wdtbase = reg & 0xffff;
sc->sc_wdt_iot = pa->pa_iot;
if (reg & (1U << 31) && wdtbase) {
if (PCI_MAPREG_IO_ADDR(wdtbase) == 0 ||
bus_space_map(sc->sc_wdt_iot, PCI_MAPREG_IO_ADDR(wdtbase),
E600_WDT_SIZE, 0, &sc->sc_wdt_ioh)) {
printf("%c can't map watchdog I/O space",
sc->sc_active ? ',' : ':');
goto corepcib;
}
printf("%c watchdog", sc->sc_active ? ',' : ':');
/* Check for reboot on timeout */
reg = bus_space_read_1(sc->sc_wdt_iot, sc->sc_wdt_ioh,
E600_WDT_RR1);
if (reg & E600_WDT_RR1_TIMEOUT) {
printf(", reboot on timeout");
/* Clear timeout bit */
tcpcib_wdt_unlock(sc);
bus_space_write_1(sc->sc_wdt_iot, sc->sc_wdt_ioh,
E600_WDT_RR1, E600_WDT_RR1_TIMEOUT);
}
/* Check it's not locked already */
reg = bus_space_read_1(sc->sc_wdt_iot, sc->sc_wdt_ioh,
E600_WDT_WDTLR);
if (reg & E600_WDT_WDTLR_LOCK) {
printf(", locked");
goto corepcib;
}
/* Disable watchdog */
tcpcib_wdt_stop(sc);
sc->sc_wdt_period = 0;
sc->sc_active |= E600_WDT_ACTIVE;
/* Register new watchdog */
wdog_register(tcpcib_wdt_cb, sc);
}
corepcib:
/* Provide core pcib(4) functionality */
pcibattach(parent, self, aux);
}
void
pciaddr_resource_manage(struct pcibios_softc *sc, pci_chipset_tag_t pc,
pcitag_t tag, pciaddr_resource_manage_func_t func)
{
struct extent *ex;
pcireg_t val, mask;
bus_addr_t addr;
bus_size_t size;
int error, mapreg, type, reg_start, reg_end, width;
val = pci_conf_read(pc, tag, PCI_BHLC_REG);
switch (PCI_HDRTYPE_TYPE(val)) {
default:
printf("WARNING: unknown PCI device header 0x%x.\n",
PCI_HDRTYPE_TYPE(val));
sc->nbogus++;
return;
case 0:
reg_start = PCI_MAPREG_START;
reg_end = PCI_MAPREG_END;
break;
case 1: /* PCI-PCI bridge */
reg_start = PCI_MAPREG_START;
reg_end = PCI_MAPREG_PPB_END;
break;
case 2: /* PCI-CardBus bridge */
reg_start = PCI_MAPREG_START;
reg_end = PCI_MAPREG_PCB_END;
break;
}
error = 0;
for (mapreg = reg_start; mapreg < reg_end; mapreg += width) {
/* inquire PCI device bus space requirement */
val = pci_conf_read(pc, tag, mapreg);
pci_conf_write(pc, tag, mapreg, ~0);
mask = pci_conf_read(pc, tag, mapreg);
pci_conf_write(pc, tag, mapreg, val);
type = PCI_MAPREG_TYPE(val);
width = 4;
if (type == PCI_MAPREG_TYPE_MEM) {
if (PCI_MAPREG_MEM_TYPE(val) ==
PCI_MAPREG_MEM_TYPE_64BIT) {
/* XXX We could examine the upper 32 bits
* XXX of the BAR here, but we are totally
* XXX unprepared to handle a non-zero value,
* XXX either here or anywhere else in
* XXX i386-land.
* XXX So just arrange to not look at the
* XXX upper 32 bits, lest we misinterpret
* XXX it as a 32-bit BAR set to zero.
*/
width = 8;
}
addr = PCI_MAPREG_MEM_ADDR(val);
size = PCI_MAPREG_MEM_SIZE(mask);
ex = sc->extent_mem;
} else {
/* XXX some devices give 32bit value */
addr = PCI_MAPREG_IO_ADDR(val) & PCIADDR_PORT_END;
size = PCI_MAPREG_IO_SIZE(mask);
ex = sc->extent_port;
}
if (!size) /* unused register */
continue;
/* reservation/allocation phase */
error += (*func) (sc, pc, tag, mapreg, ex, type, &addr, size);
PCIBIOS_PRINTV(("\t%02xh %s 0x%08x 0x%08x\n",
mapreg, type ? "port" : "mem ",
(unsigned int)addr, (unsigned int)size));
}
if (error)
sc->nbogus++;
PCIBIOS_PRINTV(("\t\t[%s]\n", error ? "NG" : "OK"));
}
void
device_register(struct device *dev, void *aux)
{
#if NPCI > 0
extern struct cfdriver pci_cd;
#endif
#if NCD > 0 || NSD > 0 || NST > 0
extern struct cfdriver scsibus_cd;
#endif
struct confargs *ca = aux;
static struct device *elder = NULL;
if (bootdv != NULL)
return; /* We already have a winner */
#if NPCI > 0
if (dev->dv_parent &&
dev->dv_parent->dv_cfdata->cf_driver == &pci_cd) {
struct pci_attach_args *pa = aux;
pcireg_t addr;
int reg;
for (reg = PCI_MAPREG_START; reg < PCI_MAPREG_END; reg += 4) {
addr = pci_conf_read(pa->pa_pc, pa->pa_tag, reg);
if (PCI_MAPREG_TYPE(addr) == PCI_MAPREG_TYPE_IO)
addr = PCI_MAPREG_IO_ADDR(addr);
else
addr = PCI_MAPREG_MEM_ADDR(addr);
if (addr == (pcireg_t)(u_long)PAGE0->mem_boot.pz_hpa) {
elder = dev;
break;
}
}
} else
#endif
if (ca->ca_hpa == (hppa_hpa_t)PAGE0->mem_boot.pz_hpa) {
/*
* If hpa matches, the only thing we know is that the
* booted device is either this one or one of its children.
* And the children will not necessarily have the correct
* hpa value.
* Save this elder for now.
*/
elder = dev;
} else if (elder == NULL) {
return; /* not the device we booted from */
}
/*
* Unfortunately, we can not match on pz_class vs dv_class on
* older snakes netbooting using the rbootd protocol.
* In this case, we'll end up with pz_class == PCL_RANDOM...
* Instead, trust the device class from what the kernel attached
* now...
*/
switch (dev->dv_class) {
case DV_IFNET:
/*
* Netboot is the top elder
*/
if (elder == dev) {
bootdv = dev;
}
return;
case DV_DISK:
case DV_DULL:
if ((PAGE0->mem_boot.pz_class & PCL_CLASS_MASK) != PCL_RANDOM)
return;
break;
case DV_TAPE:
if ((PAGE0->mem_boot.pz_class & PCL_CLASS_MASK) != PCL_SEQU)
return;
break;
default:
/* No idea what we were booted from, but better ask the user */
return;
}
/*
* If control goes here, we are booted from a block device and we
* matched a block device.
*
* We only grok SCSI boot currently. Match on proper device
* hierarchy and unit/lun values.
*/
#if NCD > 0 || NSD > 0 || NST > 0
if (dev->dv_parent &&
dev->dv_parent->dv_cfdata->cf_driver == &scsibus_cd) {
struct scsi_attach_args *sa = aux;
struct scsi_link *sl = sa->sa_sc_link;
/*
* sd/st/cd is attached to scsibus which is attached to
* the controller. Hence the grandparent here should be
* the elder.
*/
if (dev->dv_parent->dv_parent != elder) {
return;
}
/*
* And now check for proper target and lun values
*/
if (sl->target == PAGE0->mem_boot.pz_layers[0] &&
sl->lun == PAGE0->mem_boot.pz_layers[1]) {
bootdv = dev;
}
}
#endif
}
static void
puc_attach(device_t parent, device_t self, void *aux)
{
struct puc_softc *sc = device_private(self);
struct pci_attach_args *pa = aux;
struct puc_attach_args paa;
pci_intr_handle_t intrhandle;
pcireg_t subsys;
int i, barindex;
bus_addr_t base;
bus_space_tag_t tag;
#ifdef PUCCN
bus_space_handle_t ioh;
#endif
int locs[PUCCF_NLOCS];
subsys = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG);
sc->sc_desc = puc_find_description(PCI_VENDOR(pa->pa_id),
PCI_PRODUCT(pa->pa_id), PCI_VENDOR(subsys), PCI_PRODUCT(subsys));
if (sc->sc_desc == NULL) {
/*
* This was a class/subclass match, so tell people to compile
* kernel with options that cause this driver to spew.
*/
#ifdef PUC_PRINT_REGS
printf(":\n");
pci_conf_print(pa->pa_pc, pa->pa_tag, NULL);
#else
printf(": unknown PCI communications device\n");
printf("%s: compile kernel with PUC_PRINT_REGS and larger\n",
device_xname(self));
printf("%s: mesage buffer (via 'options MSGBUFSIZE=...'),\n",
device_xname(self));
printf("%s: and report the result with send-pr\n",
device_xname(self));
#endif
return;
}
printf(": %s (", sc->sc_desc->name);
for (i = 0; PUC_PORT_VALID(sc->sc_desc, i); i++)
printf("%s%s", i ? ", " : "",
puc_port_type_name(sc->sc_desc->ports[i].type));
printf(")\n");
for (i = 0; i < 6; i++) {
pcireg_t bar, type;
sc->sc_bar_mappings[i].mapped = 0;
bar = pci_conf_read(pa->pa_pc, pa->pa_tag,
PCI_MAPREG_START + 4 * i); /* XXX const */
if (bar == 0) /* BAR not implemented(?) */
continue;
type = (PCI_MAPREG_TYPE(bar) == PCI_MAPREG_TYPE_IO ?
PCI_MAPREG_TYPE_IO : PCI_MAPREG_MEM_TYPE(bar));
if (type == PCI_MAPREG_TYPE_IO) {
tag = pa->pa_iot;
base = PCI_MAPREG_IO_ADDR(bar);
} else {
tag = pa->pa_memt;
base = PCI_MAPREG_MEM_ADDR(bar);
}
#ifdef PUCCN
if (com_is_console(tag, base, &ioh)) {
sc->sc_bar_mappings[i].mapped = 1;
sc->sc_bar_mappings[i].a = base;
sc->sc_bar_mappings[i].s = COM_NPORTS;
sc->sc_bar_mappings[i].t = tag;
sc->sc_bar_mappings[i].h = ioh;
continue;
}
#endif
sc->sc_bar_mappings[i].mapped = (pci_mapreg_map(pa,
PCI_MAPREG_START + 4 * i, type, 0,
&sc->sc_bar_mappings[i].t, &sc->sc_bar_mappings[i].h,
&sc->sc_bar_mappings[i].a, &sc->sc_bar_mappings[i].s)
== 0);
if (sc->sc_bar_mappings[i].mapped)
continue;
aprint_error_dev(self, "couldn't map BAR at offset 0x%lx\n",
(long)(PCI_MAPREG_START + 4 * i));
}
/* Map interrupt. */
if (pci_intr_map(pa, &intrhandle)) {
aprint_error_dev(self, "couldn't map interrupt\n");
return;
}
/*
* XXX the sub-devices establish the interrupts, for the
* XXX following reasons:
* XXX
* XXX * we can't really know what IPLs they'd want
* XXX
* XXX * the MD dispatching code can ("should") dispatch
* XXX chained interrupts better than we can.
* XXX
* XXX It would be nice if we could indicate to the MD interrupt
* XXX handling code that the interrupt line used by the device
* XXX was a PCI (level triggered) interrupt.
* XXX
* XXX It's not pretty, but hey, what is?
*/
/* Configure each port. */
for (i = 0; PUC_PORT_VALID(sc->sc_desc, i); i++) {
bus_space_handle_t subregion_handle;
/* make sure the base address register is mapped */
barindex = PUC_PORT_BAR_INDEX(sc->sc_desc->ports[i].bar);
if (!sc->sc_bar_mappings[barindex].mapped) {
printf("%s: %s port uses unmapped BAR (0x%x)\n",
device_xname(self),
puc_port_type_name(sc->sc_desc->ports[i].type),
sc->sc_desc->ports[i].bar);
continue;
}
/* set up to configure the child device */
paa.port = i;
paa.type = sc->sc_desc->ports[i].type;
paa.flags = sc->sc_desc->ports[i].flags;
paa.pc = pa->pa_pc;
paa.tag = pa->pa_tag;
paa.intrhandle = intrhandle;
paa.a = sc->sc_bar_mappings[barindex].a;
paa.t = sc->sc_bar_mappings[barindex].t;
paa.dmat = pa->pa_dmat;
paa.dmat64 = pa->pa_dmat64;
if (
#ifdef PUCCN
!com_is_console(sc->sc_bar_mappings[barindex].t,
sc->sc_bar_mappings[barindex].a, &subregion_handle)
&&
#endif
bus_space_subregion(sc->sc_bar_mappings[barindex].t,
sc->sc_bar_mappings[barindex].h,
sc->sc_desc->ports[i].offset,
sc->sc_bar_mappings[barindex].s -
sc->sc_desc->ports[i].offset,
&subregion_handle) != 0) {
aprint_error_dev(self, "couldn't get subregion for port %d\n", i);
continue;
}
paa.h = subregion_handle;
#if 0
printf("%s: port %d: %s @ (index %d) 0x%x (0x%lx, 0x%lx)\n",
device_xname(self), paa.port,
puc_port_type_name(paa.type), barindex, (int)paa.a,
(long)paa.t, (long)paa.h);
#endif
locs[PUCCF_PORT] = i;
/* and configure it */
sc->sc_ports[i].dev = config_found_sm_loc(self, "puc", locs,
&paa, puc_print, config_stdsubmatch);
}
}
static bus_addr_t
pucprobe_doit(struct consdev *cn)
{
struct pci_attach_args pa;
int bus;
static int dev = 0, func = 0;
int maxdev, nfunctions = 0, i; /* XXX */
pcireg_t reg, bhlcr, subsys = 0; /* XXX */
int foundport = 0;
const struct puc_device_description *desc;
pcireg_t base;
/* Fetch our tags */
#if defined(amd64) || defined(i386)
if (cpu_puc_cnprobe(cn, &pa) != 0)
#endif
return 0;
pci_decompose_tag(pa.pa_pc, pa.pa_tag, &bus, &maxdev, NULL);
/* Scan through devices and find a communication class device. */
for (; dev <= maxdev ; dev++) {
pa.pa_tag = pci_make_tag(pa.pa_pc, bus, dev, 0);
reg = pci_conf_read(pa.pa_pc, pa.pa_tag, PCI_ID_REG);
if (PCI_VENDOR(reg) == PCI_VENDOR_INVALID
|| PCI_VENDOR(reg) == 0)
continue;
bhlcr = pci_conf_read(pa.pa_pc, pa.pa_tag, PCI_BHLC_REG);
if (PCI_HDRTYPE_MULTIFN(bhlcr)) {
nfunctions = 8;
} else {
nfunctions = 1;
}
resume_scan:
for (; func < nfunctions; func++) {
pa.pa_tag = pci_make_tag(pa.pa_pc, bus, dev, func);
reg = pci_conf_read(pa.pa_pc, pa.pa_tag,
PCI_CLASS_REG);
if (PCI_CLASS(reg) == PCI_CLASS_COMMUNICATIONS
&& PCI_SUBCLASS(reg)
== PCI_SUBCLASS_COMMUNICATIONS_SERIAL) {
pa.pa_id = pci_conf_read(pa.pa_pc, pa.pa_tag,
PCI_ID_REG);
subsys = pci_conf_read(pa.pa_pc, pa.pa_tag,
PCI_SUBSYS_ID_REG);
foundport = 1;
break;
}
}
if (foundport)
break;
func = 0;
}
/*
* If all devices was scanned and couldn't find any communication
* device, return with 0.
*/
if (!foundport)
return 0;
/* Clear foundport flag */
foundport = 0;
/* Check whether the device is in the puc device table or not */
desc = puc_find_description(PCI_VENDOR(pa.pa_id),
PCI_PRODUCT(pa.pa_id), PCI_VENDOR(subsys), PCI_PRODUCT(subsys));
/* If not, check the next communication device */
if (desc == NULL) {
/* Resume from the next function */
func++;
goto resume_scan;
}
/*
* We found a device and it's on the puc table. Set the tag and
* the base address.
*/
for (i = 0; PUC_PORT_VALID(desc, i); i++) {
if (desc->ports[i].type != PUC_PORT_TYPE_COM)
continue;
puccnflags = desc->ports[i].flags;
base = pci_conf_read(pa.pa_pc, pa.pa_tag, desc->ports[i].bar);
base += desc->ports[i].offset;
if (PCI_MAPREG_TYPE(base) == PCI_MAPREG_TYPE_IO) {
puctag = pa.pa_iot;
base = PCI_MAPREG_IO_ADDR(base);
}
#if 0 /* For MMIO device */
else {
puctag = pa.pa_memt;
base = PCI_MAPREG_MEM_ADDR(base);
}
#endif
if (com_is_console(puctag, base, NULL))
continue;
foundport = 1;
break;
}
if (foundport == 0) {
func++;
goto resume_scan;
}
#if 0
cn->cn_pri = CN_REMOTE;
#else
if (cn)
cn->cn_pri = CN_REMOTE;
#endif
return base;
}
static void
piixpm_attach(device_t parent, device_t self, void *aux)
{
struct piixpm_softc *sc = device_private(self);
struct pci_attach_args *pa = aux;
struct i2cbus_attach_args iba;
pcireg_t base, conf;
pcireg_t pmmisc;
pci_intr_handle_t ih;
char devinfo[256];
const char *intrstr = NULL;
sc->sc_dev = self;
sc->sc_pc = pa->pa_pc;
sc->sc_pcitag = pa->pa_tag;
aprint_naive("\n");
aprint_normal("\n");
pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo));
aprint_normal_dev(self, "%s (rev. 0x%02x)\n", devinfo,
PCI_REVISION(pa->pa_class));
if (!pmf_device_register(self, piixpm_suspend, piixpm_resume))
aprint_error_dev(self, "couldn't establish power handler\n");
/* Read configuration */
conf = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_SMB_HOSTC);
DPRINTF(("%s: conf 0x%x\n", device_xname(self), conf));
if ((PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL) ||
(PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_INTEL_82371AB_PMC))
goto nopowermanagement;
/* check whether I/O access to PM regs is enabled */
pmmisc = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_PMREGMISC);
if (!(pmmisc & 1))
goto nopowermanagement;
sc->sc_pm_iot = pa->pa_iot;
/* Map I/O space */
base = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_PM_BASE);
if (bus_space_map(sc->sc_pm_iot, PCI_MAPREG_IO_ADDR(base),
PIIX_PM_SIZE, 0, &sc->sc_pm_ioh)) {
aprint_error_dev(self, "can't map power management I/O space\n");
goto nopowermanagement;
}
/*
* Revision 0 and 1 are PIIX4, 2 is PIIX4E, 3 is PIIX4M.
* PIIX4 and PIIX4E have a bug in the timer latch, see Errata #20
* in the "Specification update" (document #297738).
*/
acpipmtimer_attach(self, sc->sc_pm_iot, sc->sc_pm_ioh,
PIIX_PM_PMTMR,
(PCI_REVISION(pa->pa_class) < 3) ? ACPIPMT_BADLATCH : 0 );
nopowermanagement:
if ((conf & PIIX_SMB_HOSTC_HSTEN) == 0) {
aprint_normal_dev(self, "SMBus disabled\n");
return;
}
/* Map I/O space */
sc->sc_smb_iot = pa->pa_iot;
base = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_SMB_BASE) & 0xffff;
if (bus_space_map(sc->sc_smb_iot, PCI_MAPREG_IO_ADDR(base),
PIIX_SMB_SIZE, 0, &sc->sc_smb_ioh)) {
aprint_error_dev(self, "can't map smbus I/O space\n");
return;
}
sc->sc_poll = 1;
if ((conf & PIIX_SMB_HOSTC_INTMASK) == PIIX_SMB_HOSTC_SMI) {
/* No PCI IRQ */
aprint_normal_dev(self, "interrupting at SMI");
} else if ((conf & PIIX_SMB_HOSTC_INTMASK) == PIIX_SMB_HOSTC_IRQ) {
/* Install interrupt handler */
if (pci_intr_map(pa, &ih) == 0) {
intrstr = pci_intr_string(pa->pa_pc, ih);
sc->sc_smb_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO,
piixpm_intr, sc);
if (sc->sc_smb_ih != NULL) {
aprint_normal_dev(self, "interrupting at %s",
intrstr);
sc->sc_poll = 0;
}
}
}
if (sc->sc_poll)
aprint_normal_dev(self, "polling");
aprint_normal("\n");
/* Attach I2C bus */
rw_init(&sc->sc_i2c_rwlock);
sc->sc_i2c_tag.ic_cookie = sc;
sc->sc_i2c_tag.ic_acquire_bus = piixpm_i2c_acquire_bus;
sc->sc_i2c_tag.ic_release_bus = piixpm_i2c_release_bus;
sc->sc_i2c_tag.ic_exec = piixpm_i2c_exec;
bzero(&iba, sizeof(iba));
iba.iba_tag = &sc->sc_i2c_tag;
config_found_ia(self, "i2cbus", &iba, iicbus_print);
return;
}
static void
piixpm_attach(device_t parent, device_t self, void *aux)
{
struct piixpm_softc *sc = device_private(self);
struct pci_attach_args *pa = aux;
struct i2cbus_attach_args iba;
pcireg_t base, conf;
pcireg_t pmmisc;
pci_intr_handle_t ih;
const char *intrstr = NULL;
int i, numbusses = 1;
sc->sc_dev = self;
sc->sc_iot = pa->pa_iot;
sc->sc_id = pa->pa_id;
sc->sc_pc = pa->pa_pc;
sc->sc_pcitag = pa->pa_tag;
pci_aprint_devinfo(pa, NULL);
if (!pmf_device_register(self, piixpm_suspend, piixpm_resume))
aprint_error_dev(self, "couldn't establish power handler\n");
/* Read configuration */
conf = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_SMB_HOSTC);
DPRINTF(("%s: conf 0x%x\n", device_xname(self), conf));
if ((PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL) ||
(PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_INTEL_82371AB_PMC))
goto nopowermanagement;
/* check whether I/O access to PM regs is enabled */
pmmisc = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_PMREGMISC);
if (!(pmmisc & 1))
goto nopowermanagement;
/* Map I/O space */
base = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_PM_BASE);
if (bus_space_map(sc->sc_pm_iot, PCI_MAPREG_IO_ADDR(base),
PIIX_PM_SIZE, 0, &sc->sc_pm_ioh)) {
aprint_error_dev(self, "can't map power management I/O space\n");
goto nopowermanagement;
}
/*
* Revision 0 and 1 are PIIX4, 2 is PIIX4E, 3 is PIIX4M.
* PIIX4 and PIIX4E have a bug in the timer latch, see Errata #20
* in the "Specification update" (document #297738).
*/
acpipmtimer_attach(self, sc->sc_pm_iot, sc->sc_pm_ioh,
PIIX_PM_PMTMR,
(PCI_REVISION(pa->pa_class) < 3) ? ACPIPMT_BADLATCH : 0 );
nopowermanagement:
/* SB800 rev 0x40+ needs special initialization */
if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ATI &&
PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ATI_SB600_SMB &&
PCI_REVISION(pa->pa_class) >= 0x40) {
if (piixpm_sb800_init(sc) == 0) {
numbusses = 4;
goto attach_i2c;
}
aprint_normal_dev(self, "SMBus disabled\n");
return;
}
if ((conf & PIIX_SMB_HOSTC_HSTEN) == 0) {
aprint_normal_dev(self, "SMBus disabled\n");
return;
}
/* Map I/O space */
base = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_SMB_BASE) & 0xffff;
if (bus_space_map(sc->sc_smb_iot, PCI_MAPREG_IO_ADDR(base),
PIIX_SMB_SIZE, 0, &sc->sc_smb_ioh)) {
aprint_error_dev(self, "can't map smbus I/O space\n");
return;
}
sc->sc_poll = 1;
aprint_normal_dev(self, "");
if ((conf & PIIX_SMB_HOSTC_INTMASK) == PIIX_SMB_HOSTC_SMI) {
/* No PCI IRQ */
aprint_normal("interrupting at SMI, ");
} else if ((conf & PIIX_SMB_HOSTC_INTMASK) == PIIX_SMB_HOSTC_IRQ) {
/* Install interrupt handler */
if (pci_intr_map(pa, &ih) == 0) {
intrstr = pci_intr_string(pa->pa_pc, ih);
sc->sc_smb_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO,
piixpm_intr, sc);
if (sc->sc_smb_ih != NULL) {
aprint_normal("interrupting at %s", intrstr);
sc->sc_poll = 0;
}
}
}
if (sc->sc_poll)
aprint_normal("polling");
aprint_normal("\n");
attach_i2c:
/* Attach I2C bus */
mutex_init(&sc->sc_i2c_mutex, MUTEX_DEFAULT, IPL_NONE);
for (i = 0; i < numbusses; i++) {
sc->sc_busses[i].sda = i;
sc->sc_busses[i].softc = sc;
sc->sc_i2c_tags[i].ic_cookie = &sc->sc_busses[i];
sc->sc_i2c_tags[i].ic_acquire_bus = piixpm_i2c_acquire_bus;
sc->sc_i2c_tags[i].ic_release_bus = piixpm_i2c_release_bus;
sc->sc_i2c_tags[i].ic_exec = piixpm_i2c_exec;
memset(&iba, 0, sizeof(iba));
iba.iba_type = I2C_TYPE_SMBUS;
iba.iba_tag = &sc->sc_i2c_tags[i];
config_found_ia(self, "i2cbus", &iba, iicbus_print);
}
}
static int
pci_device_openbsd_probe(struct pci_device *device)
{
struct pci_device_private *priv = (struct pci_device_private *)device;
struct pci_mem_region *region;
uint64_t reg64, size64;
uint32_t bar, reg, size;
int domain, bus, dev, func, err;
domain = device->domain;
bus = device->bus;
dev = device->dev;
func = device->func;
err = pci_read(domain, bus, dev, func, PCI_BHLC_REG, ®);
if (err)
return err;
priv->header_type = PCI_HDRTYPE_TYPE(reg);
if (priv->header_type != 0)
return 0;
region = device->regions;
for (bar = PCI_MAPREG_START; bar < PCI_MAPREG_END;
bar += sizeof(uint32_t), region++) {
err = pci_read(domain, bus, dev, func, bar, ®);
if (err)
return err;
/* Probe the size of the region. */
err = pci_readmask(domain, bus, dev, func, bar, &size);
if (err)
return err;
if (PCI_MAPREG_TYPE(reg) == PCI_MAPREG_TYPE_IO) {
region->is_IO = 1;
region->base_addr = PCI_MAPREG_IO_ADDR(reg);
region->size = PCI_MAPREG_IO_SIZE(size);
} else {
if (PCI_MAPREG_MEM_PREFETCHABLE(reg))
region->is_prefetchable = 1;
switch(PCI_MAPREG_MEM_TYPE(reg)) {
case PCI_MAPREG_MEM_TYPE_32BIT:
case PCI_MAPREG_MEM_TYPE_32BIT_1M:
region->base_addr = PCI_MAPREG_MEM_ADDR(reg);
region->size = PCI_MAPREG_MEM_SIZE(size);
break;
case PCI_MAPREG_MEM_TYPE_64BIT:
region->is_64 = 1;
reg64 = reg;
size64 = size;
bar += sizeof(uint32_t);
err = pci_read(domain, bus, dev, func, bar, ®);
if (err)
return err;
reg64 |= (uint64_t)reg << 32;
err = pci_readmask(domain, bus, dev, func, bar, &size);
if (err)
return err;
size64 |= (uint64_t)size << 32;
region->base_addr = PCI_MAPREG_MEM64_ADDR(reg64);
region->size = PCI_MAPREG_MEM64_SIZE(size64);
region++;
break;
}
}
}
/* Probe expansion ROM if present */
err = pci_read(domain, bus, dev, func, PCI_ROM_REG, ®);
if (err)
return err;
if (reg != 0) {
err = pci_write(domain, bus, dev, func, PCI_ROM_REG, ~PCI_ROM_ENABLE);
if (err)
return err;
pci_read(domain, bus, dev, func, PCI_ROM_REG, &size);
pci_write(domain, bus, dev, func, PCI_ROM_REG, reg);
if (PCI_ROM_ADDR(reg) != 0) {
priv->rom_base = PCI_ROM_ADDR(reg);
device->rom_size = PCI_ROM_SIZE(size);
}
}
return 0;
}
void
piixpm_attach(struct device *parent, struct device *self, void *aux)
{
struct piixpm_softc *sc = (struct piixpm_softc *)self;
struct pci_attach_args *pa = aux;
struct i2cbus_attach_args iba;
pcireg_t base, conf;
pci_intr_handle_t ih;
const char *intrstr = NULL;
/* Read configuration */
conf = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_SMB_HOSTC);
DPRINTF((": conf 0x%08x", conf));
if ((conf & PIIX_SMB_HOSTC_HSTEN) == 0) {
printf(": SMBus disabled\n");
return;
}
/* Map I/O space */
sc->sc_iot = pa->pa_iot;
base = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_SMB_BASE) & 0xffff;
if (PCI_MAPREG_IO_ADDR(base) == 0 ||
bus_space_map(sc->sc_iot, PCI_MAPREG_IO_ADDR(base),
PIIX_SMB_SIZE, 0, &sc->sc_ioh)) {
printf(": can't map I/O space\n");
return;
}
sc->sc_poll = 1;
if ((conf & PIIX_SMB_HOSTC_INTMASK) == PIIX_SMB_HOSTC_SMI) {
/* No PCI IRQ */
printf(": SMI");
} else {
if ((conf & PIIX_SMB_HOSTC_INTMASK) == PIIX_SMB_HOSTC_IRQ) {
/* Install interrupt handler */
if (pci_intr_map(pa, &ih) == 0) {
intrstr = pci_intr_string(pa->pa_pc, ih);
sc->sc_ih = pci_intr_establish(pa->pa_pc,
ih, IPL_BIO, piixpm_intr, sc,
sc->sc_dev.dv_xname);
if (sc->sc_ih != NULL) {
printf(": %s", intrstr);
sc->sc_poll = 0;
}
}
}
if (sc->sc_poll)
printf(": polling");
}
printf("\n");
/* Attach I2C bus */
lockinit(&sc->sc_i2c_lock, PRIBIO | PCATCH, "iiclk", 0, 0);
sc->sc_i2c_tag.ic_cookie = sc;
sc->sc_i2c_tag.ic_acquire_bus = piixpm_i2c_acquire_bus;
sc->sc_i2c_tag.ic_release_bus = piixpm_i2c_release_bus;
sc->sc_i2c_tag.ic_exec = piixpm_i2c_exec;
bzero(&iba, sizeof(iba));
iba.iba_name = "iic";
iba.iba_tag = &sc->sc_i2c_tag;
config_found(self, &iba, iicbus_print);
return;
}
