int
cas_pci_enaddr(struct cas_softc *sc, struct pci_attach_args *pa)
{
struct pci_vpd_largeres *res;
struct pci_vpd *vpd;
bus_space_handle_t romh;
bus_space_tag_t romt;
bus_size_t romsize;
u_int8_t buf[32], *desc;
pcireg_t address, mask;
int dataoff, vpdoff, len;
int rv = -1;
address = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_ROM_REG);
pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_ROM_REG, 0xfffffffe);
mask = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_ROM_REG);
address |= PCI_ROM_ENABLE;
pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_ROM_REG, address);
romt = pa->pa_memt;
romsize = PCI_ROM_SIZE(mask);
if (bus_space_map(romt, PCI_ROM_ADDR(address), romsize, 0, &romh)) {
romsize = 0;
goto fail;
}
bus_space_read_region_1(romt, romh, 0, buf, sizeof(buf));
if (bcmp(buf, cas_promhdr, sizeof(cas_promhdr)))
goto fail;
dataoff = buf[PROMHDR_PTR_DATA] | (buf[PROMHDR_PTR_DATA + 1] << 8);
if (dataoff < 0x1c)
goto fail;
bus_space_read_region_1(romt, romh, dataoff, buf, sizeof(buf));
if (bcmp(buf, cas_promdat, sizeof(cas_promdat)) ||
bcmp(buf + PROMDATA_DATA2, cas_promdat2, sizeof(cas_promdat2)))
goto fail;
vpdoff = buf[PROMDATA_PTR_VPD] | (buf[PROMDATA_PTR_VPD + 1] << 8);
if (vpdoff < 0x1c)
goto fail;
next:
bus_space_read_region_1(romt, romh, vpdoff, buf, sizeof(buf));
if (!PCI_VPDRES_ISLARGE(buf[0]))
goto fail;
res = (struct pci_vpd_largeres *)buf;
vpdoff += sizeof(*res);
len = ((res->vpdres_len_msb << 8) + res->vpdres_len_lsb);
switch(PCI_VPDRES_LARGE_NAME(res->vpdres_byte0)) {
case PCI_VPDRES_TYPE_IDENTIFIER_STRING:
/* Skip identifier string. */
vpdoff += len;
goto next;
case PCI_VPDRES_TYPE_VPD:
while (len > 0) {
bus_space_read_region_1(romt, romh, vpdoff,
buf, sizeof(buf));
vpd = (struct pci_vpd *)buf;
vpdoff += sizeof(*vpd) + vpd->vpd_len;
len -= sizeof(*vpd) + vpd->vpd_len;
/*
* We're looking for an "Enhanced" VPD...
*/
if (vpd->vpd_key0 != 'Z')
continue;
desc = buf + sizeof(*vpd);
/*
* ...which is an instance property...
*/
if (desc[0] != 'I')
continue;
desc += 3;
/*
* ...that's a byte array with the proper
* length for a MAC address...
*/
if (desc[0] != 'B' || desc[1] != ETHER_ADDR_LEN)
continue;
desc += 2;
/*
* ...named "local-mac-address".
*/
if (strcmp(desc, "local-mac-address") != 0)
continue;
desc += strlen("local-mac-address") + 1;
bcopy(desc, sc->sc_arpcom.ac_enaddr, ETHER_ADDR_LEN);
rv = 0;
}
break;
default:
goto fail;
}
fail:
if (romsize != 0)
bus_space_unmap(romt, romh, romsize);
address = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_ROM_REG);
address &= ~PCI_ROM_ENABLE;
pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_ROM_REG, address);
return (rv);
}
int
gem_pci_enaddr(struct gem_softc *sc, struct pci_attach_args *pa)
{
struct pci_vpd *vpd;
bus_space_handle_t romh;
bus_space_tag_t romt;
bus_size_t romsize = 0;
u_int8_t buf[32];
pcireg_t address;
int dataoff, vpdoff;
int rv = -1;
if (pci_mapreg_map(pa, PCI_ROM_REG, PCI_MAPREG_TYPE_MEM, 0,
&romt, &romh, 0, &romsize, 0))
return (-1);
address = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_ROM_REG);
address |= PCI_ROM_ENABLE;
pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_ROM_REG, address);
bus_space_read_region_1(romt, romh, 0, buf, sizeof(buf));
if (bcmp(buf, gem_promhdr, sizeof(gem_promhdr)))
goto fail;
dataoff = buf[PROMHDR_PTR_DATA] | (buf[PROMHDR_PTR_DATA + 1] << 8);
if (dataoff < 0x1c)
goto fail;
bus_space_read_region_1(romt, romh, dataoff, buf, sizeof(buf));
if (bcmp(buf, gem_promdat, sizeof(gem_promdat)) ||
bcmp(buf + PROMDATA_DATA2, gem_promdat2, sizeof(gem_promdat2)))
goto fail;
vpdoff = buf[PROMDATA_PTR_VPD] | (buf[PROMDATA_PTR_VPD + 1] << 8);
if (vpdoff < 0x1c)
goto fail;
bus_space_read_region_1(romt, romh, vpdoff, buf, sizeof(buf));
/*
* The VPD of gem is not in PCI 2.2 standard format. The length
* in the resource header is in big endian.
*/
vpd = (struct pci_vpd *)(buf + 3);
if (!PCI_VPDRES_ISLARGE(buf[0]) ||
PCI_VPDRES_LARGE_NAME(buf[0]) != PCI_VPDRES_TYPE_VPD)
goto fail;
if (vpd->vpd_key0 != 'N' || vpd->vpd_key1 != 'A')
goto fail;
bcopy(buf + 6, sc->sc_arpcom.ac_enaddr, ETHER_ADDR_LEN);
rv = 0;
fail:
if (romsize != 0)
bus_space_unmap(romt, romh, romsize);
address = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_ROM_REG);
address &= ~PCI_ROM_ENABLE;
pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_ROM_REG, address);
return (rv);
}
int
hme_pci_attach(device_t dev)
{
struct hme_pci_softc *hsc;
struct hme_softc *sc;
bus_space_tag_t memt;
bus_space_handle_t memh;
int i, error = 0;
#if !(defined(__powerpc__) || defined(__sparc64__))
device_t *children, ebus_dev;
struct resource *ebus_rres;
int j, slot;
#endif
pci_enable_busmaster(dev);
/*
* Some Sun HMEs do have their intpin register bogusly set to 0,
* although it should be 1. Correct that.
*/
if (pci_get_intpin(dev) == 0)
pci_set_intpin(dev, 1);
hsc = device_get_softc(dev);
sc = &hsc->hsc_hme;
sc->sc_dev = dev;
sc->sc_flags |= HME_PCI;
mtx_init(&sc->sc_lock, device_get_nameunit(dev), MTX_NETWORK_LOCK,
MTX_DEF);
/*
* Map five register banks:
*
* bank 0: HME SEB registers: +0x0000
* bank 1: HME ETX registers: +0x2000
* bank 2: HME ERX registers: +0x4000
* bank 3: HME MAC registers: +0x6000
* bank 4: HME MIF registers: +0x7000
*
*/
i = PCIR_BAR(0);
hsc->hsc_sres = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
&i, RF_ACTIVE);
if (hsc->hsc_sres == NULL) {
device_printf(dev, "could not map device registers\n");
error = ENXIO;
goto fail_mtx;
}
i = 0;
hsc->hsc_ires = bus_alloc_resource_any(dev, SYS_RES_IRQ,
&i, RF_SHAREABLE | RF_ACTIVE);
if (hsc->hsc_ires == NULL) {
device_printf(dev, "could not allocate interrupt\n");
error = ENXIO;
goto fail_sres;
}
memt = rman_get_bustag(hsc->hsc_sres);
memh = rman_get_bushandle(hsc->hsc_sres);
sc->sc_sebt = sc->sc_etxt = sc->sc_erxt = sc->sc_mact = sc->sc_mift =
memt;
bus_space_subregion(memt, memh, 0x0000, 0x1000, &sc->sc_sebh);
bus_space_subregion(memt, memh, 0x2000, 0x1000, &sc->sc_etxh);
bus_space_subregion(memt, memh, 0x4000, 0x1000, &sc->sc_erxh);
bus_space_subregion(memt, memh, 0x6000, 0x1000, &sc->sc_mach);
bus_space_subregion(memt, memh, 0x7000, 0x1000, &sc->sc_mifh);
#if defined(__powerpc__) || defined(__sparc64__)
OF_getetheraddr(dev, sc->sc_enaddr);
#else
/*
* Dig out VPD (vital product data) and read NA (network address).
*
* The PCI HME is a PCIO chip, which is composed of two functions:
* function 0: PCI-EBus2 bridge, and
* function 1: HappyMeal Ethernet controller.
*
* The VPD of HME resides in the Boot PROM (PCI FCode) attached
* to the EBus bridge and can't be accessed via the PCI capability
* pointer.
* ``Writing FCode 3.x Programs'' (newer ones, dated 1997 and later)
* chapter 2 describes the data structure.
*
* We don't have a MI EBus driver since no EBus device exists
* (besides the FCode PROM) on add-on HME boards. The ``no driver
* attached'' message for function 0 therefore is what is expected.
*/
#define PCI_ROMHDR_SIZE 0x1c
#define PCI_ROMHDR_SIG 0x00
#define PCI_ROMHDR_SIG_MAGIC 0xaa55 /* little endian */
#define PCI_ROMHDR_PTR_DATA 0x18
#define PCI_ROM_SIZE 0x18
#define PCI_ROM_SIG 0x00
#define PCI_ROM_SIG_MAGIC 0x52494350 /* "PCIR", endian */
/* reversed */
#define PCI_ROM_VENDOR 0x04
#define PCI_ROM_DEVICE 0x06
#define PCI_ROM_PTR_VPD 0x08
#define PCI_VPDRES_BYTE0 0x00
#define PCI_VPDRES_ISLARGE(x) ((x) & 0x80)
#define PCI_VPDRES_LARGE_NAME(x) ((x) & 0x7f)
#define PCI_VPDRES_TYPE_VPD 0x10 /* large */
#define PCI_VPDRES_LARGE_LEN_LSB 0x01
#define PCI_VPDRES_LARGE_LEN_MSB 0x02
#define PCI_VPDRES_LARGE_DATA 0x03
#define PCI_VPD_SIZE 0x03
#define PCI_VPD_KEY0 0x00
#define PCI_VPD_KEY1 0x01
#define PCI_VPD_LEN 0x02
#define PCI_VPD_DATA 0x03
#define HME_ROM_READ_N(n, offs) bus_space_read_ ## n (memt, memh, (offs))
#define HME_ROM_READ_1(offs) HME_ROM_READ_N(1, (offs))
#define HME_ROM_READ_2(offs) HME_ROM_READ_N(2, (offs))
#define HME_ROM_READ_4(offs) HME_ROM_READ_N(4, (offs))
/* Search accompanying EBus bridge. */
slot = pci_get_slot(dev);
if (device_get_children(device_get_parent(dev), &children, &i) != 0) {
device_printf(dev, "could not get children\n");
error = ENXIO;
goto fail_sres;
}
ebus_dev = NULL;
for (j = 0; j < i; j++) {
if (pci_get_class(children[j]) == PCIC_BRIDGE &&
pci_get_vendor(children[j]) == PCI_VENDOR_SUN &&
pci_get_device(children[j]) == PCI_PRODUCT_SUN_EBUS &&
pci_get_slot(children[j]) == slot) {
ebus_dev = children[j];
break;
}
}
if (ebus_dev == NULL) {
device_printf(dev, "could not find EBus bridge\n");
error = ENXIO;
goto fail_children;
}
/* Map EBus bridge PROM registers. */
i = PCIR_BAR(0);
if ((ebus_rres = bus_alloc_resource_any(ebus_dev, SYS_RES_MEMORY,
&i, RF_ACTIVE)) == NULL) {
device_printf(dev, "could not map PROM registers\n");
error = ENXIO;
goto fail_children;
}
memt = rman_get_bustag(ebus_rres);
memh = rman_get_bushandle(ebus_rres);
/* Read PCI Expansion ROM header. */
if (HME_ROM_READ_2(PCI_ROMHDR_SIG) != PCI_ROMHDR_SIG_MAGIC ||
(i = HME_ROM_READ_2(PCI_ROMHDR_PTR_DATA)) < PCI_ROMHDR_SIZE) {
device_printf(dev, "unexpected PCI Expansion ROM header\n");
error = ENXIO;
goto fail_rres;
}
/* Read PCI Expansion ROM data. */
if (HME_ROM_READ_4(i + PCI_ROM_SIG) != PCI_ROM_SIG_MAGIC ||
HME_ROM_READ_2(i + PCI_ROM_VENDOR) != pci_get_vendor(dev) ||
HME_ROM_READ_2(i + PCI_ROM_DEVICE) != pci_get_device(dev) ||
(j = HME_ROM_READ_2(i + PCI_ROM_PTR_VPD)) < i + PCI_ROM_SIZE) {
device_printf(dev, "unexpected PCI Expansion ROM data\n");
error = ENXIO;
goto fail_rres;
}
/*
* Read PCI VPD.
* SUNW,hme cards have a single large resource VPD-R tag
* containing one NA. SUNW,qfe cards have four large resource
* VPD-R tags containing one NA each (all four HME chips share
* the same PROM).
* The VPD used on both cards is not in PCI 2.2 standard format
* however. The length in the resource header is in big endian
* and the end tag is non-standard (0x79) and followed by an
* all-zero "checksum" byte. Sun calls this a "Fresh Choice
* Ethernet" VPD...
*/
/* Look at the end tag to determine whether this is a VPD with 4 NAs. */
if (HME_ROM_READ_1(j + PCI_VPDRES_LARGE_DATA + PCI_VPD_SIZE +
ETHER_ADDR_LEN) != 0x79 &&
HME_ROM_READ_1(j + 4 * (PCI_VPDRES_LARGE_DATA + PCI_VPD_SIZE +
ETHER_ADDR_LEN)) == 0x79)
/* Use the Nth NA for the Nth HME on this SUNW,qfe. */
j += slot * (PCI_VPDRES_LARGE_DATA + PCI_VPD_SIZE +
ETHER_ADDR_LEN);
if (PCI_VPDRES_ISLARGE(HME_ROM_READ_1(j + PCI_VPDRES_BYTE0)) == 0 ||
PCI_VPDRES_LARGE_NAME(HME_ROM_READ_1(j + PCI_VPDRES_BYTE0)) !=
PCI_VPDRES_TYPE_VPD ||
(HME_ROM_READ_1(j + PCI_VPDRES_LARGE_LEN_LSB) << 8 |
HME_ROM_READ_1(j + PCI_VPDRES_LARGE_LEN_MSB)) !=
PCI_VPD_SIZE + ETHER_ADDR_LEN ||
HME_ROM_READ_1(j + PCI_VPDRES_LARGE_DATA + PCI_VPD_KEY0) !=
0x4e /* N */ ||
HME_ROM_READ_1(j + PCI_VPDRES_LARGE_DATA + PCI_VPD_KEY1) !=
0x41 /* A */ ||
HME_ROM_READ_1(j + PCI_VPDRES_LARGE_DATA + PCI_VPD_LEN) !=
ETHER_ADDR_LEN) {
device_printf(dev, "unexpected PCI VPD\n");
error = ENXIO;
goto fail_rres;
}
bus_space_read_region_1(memt, memh, j + PCI_VPDRES_LARGE_DATA +
PCI_VPD_DATA, sc->sc_enaddr, ETHER_ADDR_LEN);
fail_rres:
bus_release_resource(ebus_dev, SYS_RES_MEMORY,
rman_get_rid(ebus_rres), ebus_rres);
fail_children:
free(children, M_TEMP);
if (error != 0)
goto fail_sres;
#endif
sc->sc_burst = 64; /* XXX */
/*
* call the main configure
*/
if ((error = hme_config(sc)) != 0) {
device_printf(dev, "could not be configured\n");
goto fail_ires;
}
if ((error = bus_setup_intr(dev, hsc->hsc_ires, INTR_TYPE_NET |
INTR_MPSAFE, NULL, hme_intr, sc, &hsc->hsc_ih)) != 0) {
device_printf(dev, "couldn't establish interrupt\n");
hme_detach(sc);
goto fail_ires;
}
return (0);
fail_ires:
bus_release_resource(dev, SYS_RES_IRQ,
rman_get_rid(hsc->hsc_ires), hsc->hsc_ires);
fail_sres:
bus_release_resource(dev, SYS_RES_MEMORY,
rman_get_rid(hsc->hsc_sres), hsc->hsc_sres);
fail_mtx:
mtx_destroy(&sc->sc_lock);
return (error);
}
static int
gem_pci_attach(device_t dev)
{
struct gem_softc *sc;
int i;
#if defined(__powerpc__) || defined(__sparc64__)
char buf[sizeof(GEM_SHARED_PINS)];
#else
int j;
#endif
sc = device_get_softc(dev);
sc->sc_variant = GEM_UNKNOWN;
for (i = 0; gem_pci_devlist[i].gpd_desc != NULL; i++) {
if (pci_get_devid(dev) == gem_pci_devlist[i].gpd_devid) {
sc->sc_variant = gem_pci_devlist[i].gpd_variant;
break;
}
}
if (sc->sc_variant == GEM_UNKNOWN) {
device_printf(dev, "unknown adaptor\n");
return (ENXIO);
}
pci_enable_busmaster(dev);
/*
* Some Sun GEMs/ERIs do have their intpin register bogusly set to 0,
* although it should be 1. Correct that.
*/
if (pci_get_intpin(dev) == 0)
pci_set_intpin(dev, 1);
/* Set the PCI latency timer for Sun ERIs. */
if (sc->sc_variant == GEM_SUN_ERI)
pci_write_config(dev, PCIR_LATTIMER, GEM_ERI_LATENCY_TIMER, 1);
sc->sc_dev = dev;
sc->sc_flags |= GEM_PCI;
if (bus_alloc_resources(dev, gem_pci_res_spec, sc->sc_res)) {
device_printf(dev, "failed to allocate resources\n");
bus_release_resources(dev, gem_pci_res_spec, sc->sc_res);
return (ENXIO);
}
GEM_LOCK_INIT(sc, device_get_nameunit(dev));
/*
* Derive GEM_RES_BANK2 from GEM_RES_BANK1. This seemed cleaner
* with the old way of using copies of the bus tag and handle in
* the softc along with bus_space_*()...
*/
sc->sc_res[GEM_RES_BANK2] = malloc(sizeof(*sc->sc_res[GEM_RES_BANK2]),
M_DEVBUF, M_NOWAIT | M_ZERO);
if (sc->sc_res[GEM_RES_BANK2] == NULL) {
device_printf(dev, "failed to allocate bank2 resource\n");
goto fail;
}
rman_set_bustag(sc->sc_res[GEM_RES_BANK2],
rman_get_bustag(sc->sc_res[GEM_RES_BANK1]));
bus_space_subregion(rman_get_bustag(sc->sc_res[GEM_RES_BANK1]),
rman_get_bushandle(sc->sc_res[GEM_RES_BANK1]),
GEM_PCI_BANK2_OFFSET, GEM_PCI_BANK2_SIZE,
&sc->sc_res[GEM_RES_BANK2]->r_bushandle);
/* Determine whether we're running at 66MHz. */
if ((GEM_BANK2_READ_4(sc, GEM_PCI_BIF_CONFIG) &
GEM_PCI_BIF_CNF_M66EN) != 0)
sc->sc_flags |= GEM_PCI66;
#if defined(__powerpc__) || defined(__sparc64__)
OF_getetheraddr(dev, sc->sc_enaddr);
if (OF_getprop(ofw_bus_get_node(dev), GEM_SHARED_PINS, buf,
sizeof(buf)) > 0) {
buf[sizeof(buf) - 1] = '\0';
if (strcmp(buf, GEM_SHARED_PINS_SERDES) == 0)
sc->sc_flags |= GEM_SERDES;
}
#else
/*
* Dig out VPD (vital product data) and read NA (network address).
* The VPD resides in the PCI Expansion ROM (PCI FCode) and can't
* be accessed via the PCI capability pointer.
* ``Writing FCode 3.x Programs'' (newer ones, dated 1997 and later)
* chapter 2 describes the data structure.
*/
#define PCI_ROMHDR_SIZE 0x1c
#define PCI_ROMHDR_SIG 0x00
#define PCI_ROMHDR_SIG_MAGIC 0xaa55 /* little endian */
#define PCI_ROMHDR_PTR_DATA 0x18
#define PCI_ROM_SIZE 0x18
#define PCI_ROM_SIG 0x00
#define PCI_ROM_SIG_MAGIC 0x52494350 /* "PCIR", endian */
/* reversed */
#define PCI_ROM_VENDOR 0x04
#define PCI_ROM_DEVICE 0x06
#define PCI_ROM_PTR_VPD 0x08
#define PCI_VPDRES_BYTE0 0x00
#define PCI_VPDRES_ISLARGE(x) ((x) & 0x80)
#define PCI_VPDRES_LARGE_NAME(x) ((x) & 0x7f)
#define PCI_VPDRES_LARGE_LEN_LSB 0x01
#define PCI_VPDRES_LARGE_LEN_MSB 0x02
#define PCI_VPDRES_LARGE_SIZE 0x03
#define PCI_VPDRES_TYPE_VPD 0x10 /* large */
#define PCI_VPD_KEY0 0x00
#define PCI_VPD_KEY1 0x01
#define PCI_VPD_LEN 0x02
#define PCI_VPD_SIZE 0x03
#define GEM_ROM_READ_1(sc, offs) \
GEM_BANK1_READ_1((sc), GEM_PCI_ROM_OFFSET + (offs))
#define GEM_ROM_READ_2(sc, offs) \
GEM_BANK1_READ_2((sc), GEM_PCI_ROM_OFFSET + (offs))
#define GEM_ROM_READ_4(sc, offs) \
GEM_BANK1_READ_4((sc), GEM_PCI_ROM_OFFSET + (offs))
/* Read PCI Expansion ROM header. */
if (GEM_ROM_READ_2(sc, PCI_ROMHDR_SIG) != PCI_ROMHDR_SIG_MAGIC ||
(i = GEM_ROM_READ_2(sc, PCI_ROMHDR_PTR_DATA)) <
PCI_ROMHDR_SIZE) {
device_printf(dev, "unexpected PCI Expansion ROM header\n");
goto fail;
}
/* Read PCI Expansion ROM data. */
if (GEM_ROM_READ_4(sc, i + PCI_ROM_SIG) != PCI_ROM_SIG_MAGIC ||
GEM_ROM_READ_2(sc, i + PCI_ROM_VENDOR) != pci_get_vendor(dev) ||
GEM_ROM_READ_2(sc, i + PCI_ROM_DEVICE) != pci_get_device(dev) ||
(j = GEM_ROM_READ_2(sc, i + PCI_ROM_PTR_VPD)) <
i + PCI_ROM_SIZE) {
device_printf(dev, "unexpected PCI Expansion ROM data\n");
goto fail;
}
/*
* Read PCI VPD.
* SUNW,pci-gem cards have a single large resource VPD-R tag
* containing one NA. The VPD used is not in PCI 2.2 standard
* format however. The length in the resource header is in big
* endian and the end tag is non-standard (0x79) and followed
* by an all-zero "checksum" byte. Sun calls this a "Fresh
* Choice Ethernet" VPD...
*/
if (PCI_VPDRES_ISLARGE(GEM_ROM_READ_1(sc,
j + PCI_VPDRES_BYTE0)) == 0 ||
PCI_VPDRES_LARGE_NAME(GEM_ROM_READ_1(sc,
j + PCI_VPDRES_BYTE0)) != PCI_VPDRES_TYPE_VPD ||
((GEM_ROM_READ_1(sc, j + PCI_VPDRES_LARGE_LEN_LSB) << 8) |
GEM_ROM_READ_1(sc, j + PCI_VPDRES_LARGE_LEN_MSB)) !=
PCI_VPD_SIZE + ETHER_ADDR_LEN ||
GEM_ROM_READ_1(sc, j + PCI_VPDRES_LARGE_SIZE + PCI_VPD_KEY0) !=
0x4e /* N */ ||
GEM_ROM_READ_1(sc, j + PCI_VPDRES_LARGE_SIZE + PCI_VPD_KEY1) !=
0x41 /* A */ ||
GEM_ROM_READ_1(sc, j + PCI_VPDRES_LARGE_SIZE + PCI_VPD_LEN) !=
ETHER_ADDR_LEN ||
GEM_ROM_READ_1(sc, j + PCI_VPDRES_LARGE_SIZE + PCI_VPD_SIZE +
ETHER_ADDR_LEN) != 0x79) {
device_printf(dev, "unexpected PCI VPD\n");
goto fail;
}
bus_read_region_1(sc->sc_res[GEM_RES_BANK1],
GEM_PCI_ROM_OFFSET + j + PCI_VPDRES_LARGE_SIZE + PCI_VPD_SIZE,
sc->sc_enaddr, ETHER_ADDR_LEN);
#endif
/*
* The Xserve G5 has a fake GMAC with an all-zero MAC address.
* Check for this, and don't attach in this case.
*/
for (i = 0; i < ETHER_ADDR_LEN && sc->sc_enaddr[i] == 0; i++) {}
if (i == ETHER_ADDR_LEN) {
device_printf(dev, "invalid MAC address\n");
goto fail;
}
if (gem_attach(sc) != 0) {
device_printf(dev, "could not be attached\n");
goto fail;
}
if (bus_setup_intr(dev, sc->sc_res[GEM_RES_INTR], INTR_TYPE_NET |
INTR_MPSAFE, NULL, gem_intr, sc, &sc->sc_ih) != 0) {
device_printf(dev, "failed to set up interrupt\n");
gem_detach(sc);
goto fail;
}
return (0);
fail:
if (sc->sc_res[GEM_RES_BANK2] != NULL)
free(sc->sc_res[GEM_RES_BANK2], M_DEVBUF);
GEM_LOCK_DESTROY(sc);
bus_release_resources(dev, gem_pci_res_spec, sc->sc_res);
return (ENXIO);
}
