int jz47_put_image_with_framebuf (struct vf_instance_s* vf, mp_image_t *mpi, double pts)
{
//lcd_ioctl((void *)0,IOCTL_PENDING_IPU_END);
//printf("+\n");
PEND_IPU();
//printf("-\n");
#if USE_OSD
if(pFunction)
pFunction(lcd_get_current_cframe());
#endif
if((unsigned int)lcd_get_current_phyframe() != useframebuf)
lcd_change_frame();
IPU_REG_OUT(IPU_Y_ADDR,PHY(mpi->planes[0]));
IPU_REG_OUT(IPU_U_ADDR,PHY(mpi->planes[1]));
IPU_REG_OUT(IPU_V_ADDR,PHY(mpi->planes[2]));
IPU_REG_OUT(IPU_Y_STRIDE_ADDR,PHY(mpi->stride[0]));
IPU_REG_OUT(IPU_UV_STRIDE_ADDR,(mpi->stride[1] << 16) |mpi->stride[2]);
useframebuf = (unsigned int)lcd_get_change_phyframe();
//add_frame_buf(useframebuf);
IPU_REG_OUT(IPU_OUT_ADDR,framebuf_offset + useframebuf);
lcd_flush_frame_all();
START_IPU();
return 1;
}
void init_lcd_regs()
{
int i=0;
int thsync=0x5f;
int thdel=0xf;
int tvsync=0x1;
int tvdel=0x9;
int burst=2; //8:7 VBL(video burst length) 11=64cycle, 10=8cycle, 01=4cycle 00=1cycle
int pseudocolor=0;
int colordepth=3; //10:9 CD(color depth) 11=16bit, 10=4b, 01=2b, 00=1b
int xres=640,yres=480;
LCD_SET32(REG_LCD_VBARa, PHY(SD_LCD_BAR_BASE));
LCD_SET32(REG_LCD_VBARb, PHY(SD_LCD_BAR_BASE));
LCD_SET32(REG_LCD_CTRL,0);
LCD_SET32(REG_LCD_HTIM,(thsync<<24)|(thdel<<16)|(xres-1));
LCD_SET32(REG_LCD_VTIM,(tvsync<<24)|(tvdel<<16)|(yres-1));
LCD_SET32(REG_LCD_HVLEN, ((xres+thsync+thdel+0x31)<<16)|(yres+tvsync+tvdel+0x22));
#if 0 // CMC STN 320x240
LCD_SET32(REG_LCD_CTRL, 0x00000009|(burst<<7)|(pseudocolor<<11)|(colordepth<<9));
#else // PrimeView TFT 800x600
LCD_SET32(REG_LCD_CTRL, 0x00008009|(burst<<7)|(pseudocolor<<11)|(colordepth<<9));
#endif
for(i=0;i<0x800;i=i+4) // fill clut
LCD_SET32((REG_LCD_PCLT+i), 0x0003ffff);
}
static int
ath_get_totstat(struct statfoo *sf, int s, char b[], size_t bs)
{
struct athstatfoo_p *wf = (struct athstatfoo_p *) sf;
#define STAT(x) \
snprintf(b, bs, "%u", wf->total.ath.ast_##x); return 1
#define PHY(x) \
snprintf(b, bs, "%u", wf->total.ath.ast_rx_phy[x]); return 1
#define ANI(x) \
snprintf(b, bs, "%u", wf->total.ani_state.x); return 1
#define ANISTAT(x) \
snprintf(b, bs, "%u", wf->total.ani_stats.ast_ani_##x); return 1
#define MIBSTAT(x) \
snprintf(b, bs, "%u", wf->total.ani_stats.ast_mibstats.x); return 1
#define TXANT(x) \
snprintf(b, bs, "%u", wf->total.ath.ast_ant_tx[x]); return 1
#define RXANT(x) \
snprintf(b, bs, "%u", wf->total.ath.ast_ant_rx[x]); return 1
switch (s) {
case S_INPUT:
snprintf(b, bs, "%lu",
wf->total.ath.ast_rx_packets - wf->total.ath.ast_rx_mgt);
return 1;
case S_OUTPUT:
snprintf(b, bs, "%lu", wf->total.ath.ast_tx_packets);
return 1;
case S_RATE:
snprintrate(b, bs, wf->total.ath.ast_tx_rate);
return 1;
case S_WATCHDOG: STAT(watchdog);
case S_FATAL: STAT(hardware);
case S_BMISS: STAT(bmiss);
case S_BMISS_PHANTOM: STAT(bmiss_phantom);
#ifdef S_BSTUCK
case S_BSTUCK: STAT(bstuck);
#endif
case S_RXORN: STAT(rxorn);
case S_RXEOL: STAT(rxeol);
case S_TXURN: STAT(txurn);
case S_MIB: STAT(mib);
#ifdef S_INTRCOAL
case S_INTRCOAL: STAT(intrcoal);
#endif
case S_TX_MGMT: STAT(tx_mgmt);
case S_TX_DISCARD: STAT(tx_discard);
case S_TX_QSTOP: STAT(tx_qstop);
case S_TX_ENCAP: STAT(tx_encap);
case S_TX_NONODE: STAT(tx_nonode);
case S_TX_NOBUF: STAT(tx_nobuf);
case S_TX_NOFRAG: STAT(tx_nofrag);
case S_TX_NOMBUF: STAT(tx_nombuf);
#ifdef S_TX_NOMCL
case S_TX_NOMCL: STAT(tx_nomcl);
case S_TX_LINEAR: STAT(tx_linear);
case S_TX_NODATA: STAT(tx_nodata);
case S_TX_BUSDMA: STAT(tx_busdma);
#endif
case S_TX_XRETRIES: STAT(tx_xretries);
case S_TX_FIFOERR: STAT(tx_fifoerr);
case S_TX_FILTERED: STAT(tx_filtered);
case S_TX_SHORTRETRY: STAT(tx_shortretry);
case S_TX_LONGRETRY: STAT(tx_longretry);
case S_TX_BADRATE: STAT(tx_badrate);
case S_TX_NOACK: STAT(tx_noack);
case S_TX_RTS: STAT(tx_rts);
case S_TX_CTS: STAT(tx_cts);
case S_TX_SHORTPRE: STAT(tx_shortpre);
case S_TX_ALTRATE: STAT(tx_altrate);
case S_TX_PROTECT: STAT(tx_protect);
case S_TX_RAW: STAT(tx_raw);
case S_TX_RAW_FAIL: STAT(tx_raw_fail);
case S_RX_NOMBUF: STAT(rx_nombuf);
#ifdef S_RX_BUSDMA
case S_RX_BUSDMA: STAT(rx_busdma);
#endif
case S_RX_ORN: STAT(rx_orn);
case S_RX_CRC_ERR: STAT(rx_crcerr);
case S_RX_FIFO_ERR: STAT(rx_fifoerr);
case S_RX_CRYPTO_ERR: STAT(rx_badcrypt);
case S_RX_MIC_ERR: STAT(rx_badmic);
case S_RX_PHY_ERR: STAT(rx_phyerr);
case S_RX_PHY_UNDERRUN: PHY(HAL_PHYERR_UNDERRUN);
case S_RX_PHY_TIMING: PHY(HAL_PHYERR_TIMING);
case S_RX_PHY_PARITY: PHY(HAL_PHYERR_PARITY);
case S_RX_PHY_RATE: PHY(HAL_PHYERR_RATE);
case S_RX_PHY_LENGTH: PHY(HAL_PHYERR_LENGTH);
case S_RX_PHY_RADAR: PHY(HAL_PHYERR_RADAR);
case S_RX_PHY_SERVICE: PHY(HAL_PHYERR_SERVICE);
case S_RX_PHY_TOR: PHY(HAL_PHYERR_TOR);
case S_RX_PHY_OFDM_TIMING: PHY(HAL_PHYERR_OFDM_TIMING);
case S_RX_PHY_OFDM_SIGNAL_PARITY: PHY(HAL_PHYERR_OFDM_SIGNAL_PARITY);
case S_RX_PHY_OFDM_RATE_ILLEGAL: PHY(HAL_PHYERR_OFDM_RATE_ILLEGAL);
case S_RX_PHY_OFDM_POWER_DROP: PHY(HAL_PHYERR_OFDM_POWER_DROP);
case S_RX_PHY_OFDM_SERVICE: PHY(HAL_PHYERR_OFDM_SERVICE);
case S_RX_PHY_OFDM_RESTART: PHY(HAL_PHYERR_OFDM_RESTART);
case S_RX_PHY_CCK_TIMING: PHY(HAL_PHYERR_CCK_TIMING);
case S_RX_PHY_CCK_HEADER_CRC: PHY(HAL_PHYERR_CCK_HEADER_CRC);
case S_RX_PHY_CCK_RATE_ILLEGAL: PHY(HAL_PHYERR_CCK_RATE_ILLEGAL);
case S_RX_PHY_CCK_SERVICE: PHY(HAL_PHYERR_CCK_SERVICE);
case S_RX_PHY_CCK_RESTART: PHY(HAL_PHYERR_CCK_RESTART);
case S_RX_TOOSHORT: STAT(rx_tooshort);
case S_RX_TOOBIG: STAT(rx_toobig);
case S_RX_MGT: STAT(rx_mgt);
case S_RX_CTL: STAT(rx_ctl);
case S_TX_RSSI:
snprintf(b, bs, "%d", wf->total.ath.ast_tx_rssi);
return 1;
case S_RX_RSSI:
snprintf(b, bs, "%d", wf->total.ath.ast_rx_rssi);
return 1;
case S_BE_XMIT: STAT(be_xmit);
case S_BE_NOMBUF: STAT(be_nombuf);
case S_PER_CAL: STAT(per_cal);
case S_PER_CALFAIL: STAT(per_calfail);
case S_PER_RFGAIN: STAT(per_rfgain);
#ifdef S_TDMA_UPDATE
case S_TDMA_UPDATE: STAT(tdma_update);
case S_TDMA_TIMERS: STAT(tdma_timers);
case S_TDMA_TSF: STAT(tdma_tsf);
case S_TDMA_TSFADJ:
snprintf(b, bs, "-%d/+%d",
wf->total.ath.ast_tdma_tsfadjm,
wf->total.ath.ast_tdma_tsfadjp);
return 1;
case S_TDMA_ACK: STAT(tdma_ack);
#endif
case S_RATE_CALLS: STAT(rate_calls);
case S_RATE_RAISE: STAT(rate_raise);
case S_RATE_DROP: STAT(rate_drop);
case S_ANT_DEFSWITCH: STAT(ant_defswitch);
case S_ANT_TXSWITCH: STAT(ant_txswitch);
#ifdef S_ANI_NOISE
case S_ANI_NOISE: ANI(noiseImmunityLevel);
case S_ANI_SPUR: ANI(spurImmunityLevel);
case S_ANI_STEP: ANI(firstepLevel);
case S_ANI_OFDM: ANI(ofdmWeakSigDetectOff);
case S_ANI_CCK: ANI(cckWeakSigThreshold);
case S_ANI_LISTEN: ANI(listenTime);
case S_ANI_NIUP: ANISTAT(niup);
case S_ANI_NIDOWN: ANISTAT(nidown);
case S_ANI_SIUP: ANISTAT(spurup);
case S_ANI_SIDOWN: ANISTAT(spurdown);
case S_ANI_OFDMON: ANISTAT(ofdmon);
case S_ANI_OFDMOFF: ANISTAT(ofdmoff);
case S_ANI_CCKHI: ANISTAT(cckhigh);
case S_ANI_CCKLO: ANISTAT(ccklow);
case S_ANI_STEPUP: ANISTAT(stepup);
case S_ANI_STEPDOWN: ANISTAT(stepdown);
case S_ANI_OFDMERRS: ANISTAT(ofdmerrs);
case S_ANI_CCKERRS: ANISTAT(cckerrs);
case S_ANI_RESET: ANISTAT(reset);
case S_ANI_LZERO: ANISTAT(lzero);
case S_ANI_LNEG: ANISTAT(lneg);
case S_MIB_ACKBAD: MIBSTAT(ackrcv_bad);
case S_MIB_RTSBAD: MIBSTAT(rts_bad);
case S_MIB_RTSGOOD: MIBSTAT(rts_good);
case S_MIB_FCSBAD: MIBSTAT(fcs_bad);
case S_MIB_BEACONS: MIBSTAT(beacons);
case S_NODE_AVGBRSSI:
snprintf(b, bs, "%u",
HAL_RSSI(wf->total.ani_stats.ast_nodestats.ns_avgbrssi));
return 1;
case S_NODE_AVGRSSI:
snprintf(b, bs, "%u",
HAL_RSSI(wf->total.ani_stats.ast_nodestats.ns_avgrssi));
return 1;
case S_NODE_AVGARSSI:
snprintf(b, bs, "%u",
HAL_RSSI(wf->total.ani_stats.ast_nodestats.ns_avgtxrssi));
return 1;
#endif
case S_ANT_TX0: TXANT(0);
case S_ANT_TX1: TXANT(1);
case S_ANT_TX2: TXANT(2);
case S_ANT_TX3: TXANT(3);
case S_ANT_TX4: TXANT(4);
case S_ANT_TX5: TXANT(5);
case S_ANT_TX6: TXANT(6);
case S_ANT_TX7: TXANT(7);
case S_ANT_RX0: RXANT(0);
case S_ANT_RX1: RXANT(1);
case S_ANT_RX2: RXANT(2);
case S_ANT_RX3: RXANT(3);
case S_ANT_RX4: RXANT(4);
case S_ANT_RX5: RXANT(5);
case S_ANT_RX6: RXANT(6);
case S_ANT_RX7: RXANT(7);
#ifdef S_CABQ_XMIT
case S_CABQ_XMIT: STAT(cabq_xmit);
case S_CABQ_BUSY: STAT(cabq_busy);
#endif
case S_FF_TXOK: STAT(ff_txok);
case S_FF_TXERR: STAT(ff_txerr);
case S_FF_RX: STAT(ff_rx);
case S_FF_FLUSH: STAT(ff_flush);
case S_TX_QFULL: STAT(tx_qfull);
case S_BMISSCOUNT: STAT(be_missed);
case S_RX_NOISE:
snprintf(b, bs, "%d", wf->total.ath.ast_rx_noise);
return 1;
case S_TX_SIGNAL:
snprintf(b, bs, "%d",
wf->total.ath.ast_tx_rssi + wf->total.ath.ast_rx_noise);
return 1;
case S_RX_SIGNAL:
snprintf(b, bs, "%d",
wf->total.ath.ast_rx_rssi + wf->total.ath.ast_rx_noise);
return 1;
case S_RX_AGG: STAT(rx_agg);
case S_RX_HALFGI: STAT(rx_halfgi);
case S_RX_2040: STAT(rx_2040);
case S_RX_PRE_CRC_ERR: STAT(rx_pre_crc_err);
case S_RX_POST_CRC_ERR: STAT(rx_post_crc_err);
case S_RX_DECRYPT_BUSY_ERR: STAT(rx_decrypt_busy_err);
case S_RX_HI_CHAIN: STAT(rx_hi_rx_chain);
case S_TX_HTPROTECT: STAT(tx_htprotect);
case S_RX_QEND: STAT(rx_hitqueueend);
case S_TX_TIMEOUT: STAT(tx_timeout);
case S_TX_CSTIMEOUT: STAT(tx_cst);
case S_TX_XTXOP_ERR: STAT(tx_xtxop);
case S_TX_TIMEREXPIRED_ERR: STAT(tx_timerexpired);
case S_TX_DESCCFG_ERR: STAT(tx_desccfgerr);
case S_TX_SWRETRIES: STAT(tx_swretries);
case S_TX_SWRETRIES_MAX: STAT(tx_swretrymax);
case S_TX_DATA_UNDERRUN: STAT(tx_data_underrun);
case S_TX_DELIM_UNDERRUN: STAT(tx_delim_underrun);
case S_TX_AGGR_OK: STAT(tx_aggr_ok);
case S_TX_AGGR_FAIL: STAT(tx_aggr_fail);
case S_TX_AGGR_FAILALL: STAT(tx_aggr_failall);
}
b[0] = '\0';
return 0;
#undef RXANT
#undef TXANT
#undef ANI
#undef ANISTAT
#undef MIBSTAT
#undef PHY
#undef STAT
}
}
int misc_init_r(void)
{
ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
return 0;
}
#if defined(CONFIG_KMVECT1)
#include <mv88e6352.h>
/* Marvell MV88E6122 switch configuration */
static struct mv88e_sw_reg extsw_conf[] = {
/* port 1, FRONT_MDI, autoneg */
{ PORT(1), PORT_PHY, NO_SPEED_FOR },
{ PORT(1), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
{ PHY(1), PHY_1000_CTRL, NO_ADV },
{ PHY(1), PHY_SPEC_CTRL, AUTO_MDIX_EN },
{ PHY(1), PHY_CTRL, PHY_100_MBPS | AUTONEG_EN | AUTONEG_RST |
FULL_DUPLEX },
/* port 2, unused */
{ PORT(2), PORT_CTRL, PORT_DIS },
{ PHY(2), PHY_CTRL, PHY_PWR_DOWN },
{ PHY(2), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
/* port 3, BP_MII (CPU), PHY mode, 100BASE */
{ PORT(3), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
/* port 4, ESTAR to slot 11, SerDes, 1000BASE-X */
{ PORT(4), PORT_STATUS, NO_PHY_DETECT },
{ PORT(4), PORT_PHY, SPEED_1000_FOR },
{ PORT(4), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
/* port 5, ESTAR to slot 13, SerDes, 1000BASE-X */
{ PORT(5), PORT_STATUS, NO_PHY_DETECT },
/* reset the phy */
miiphy_reset(name, CONFIG_PHY_BASE_ADR);
}
#elif defined(CONFIG_KM_PIGGY4_88E6352)
#include <mv88e6352.h>
#if defined(CONFIG_KM_NUSA)
struct mv88e_sw_reg extsw_conf[] = {
/*
* port 0, PIGGY4, autoneg
* first the fix for the 1000Mbits Autoneg, this is from
* a Marvell errata, the regs are undocumented
*/
{ PHY(0), PHY_PAGE, AN1000FIX_PAGE },
{ PHY(0), PHY_STATUS, AN1000FIX },
{ PHY(0), PHY_PAGE, 0 },
/* now the real port and phy configuration */
{ PORT(0), PORT_PHY, NO_SPEED_FOR },
{ PORT(0), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
{ PHY(0), PHY_1000_CTRL, NO_ADV },
{ PHY(0), PHY_SPEC_CTRL, AUTO_MDIX_EN },
{ PHY(0), PHY_CTRL, PHY_100_MBPS | AUTONEG_EN | AUTONEG_RST |
FULL_DUPLEX },
/* port 1, unused */
{ PORT(1), PORT_CTRL, PORT_DIS },
{ PHY(1), PHY_CTRL, PHY_PWR_DOWN },
{ PHY(1), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
/* port 2, unused */
{ PORT(2), PORT_CTRL, PORT_DIS },