Exemple #1
0
int l2_cache_enable (int l2control)
{
    if (l2control)              /* BAB750 */
    {
        mtspr(SPRN_L2CR, l2control);
        mtspr(SPRN_L2CR, (l2control | L2CR_I));
        while (mfspr(SPRN_L2CR) & L2CR_IP)
            ;
        mtspr(SPRN_L2CR, (l2control | L2CR_E));
        return (0);
    }
    else /* BAB740 */
    {
        int picr1, picr2, mask;
        int picr2CacheSize, cacheSize;
        int *d;
        int devbusfn;
        u32 reg32;

        devbusfn = pci_find_device(PCI_VENDOR_ID_MOTOROLA,
                                   PCI_DEVICE_ID_MOTOROLA_MPC106, 0);
        if (devbusfn == -1)
            return (-1);

        pci_read_config_dword  (devbusfn, PCI_PICR2, &reg32);
        reg32 &= ~PICR2_L2_EN;
        pci_write_config_dword (devbusfn, PCI_PICR2, reg32);

        /* cache size */
        if (*(volatile unsigned char *) (CFG_ISA_IO + 0x220) & 0x04)
        {
            /* cache size is 512 KB */
            picr2CacheSize = PICR2_L2_SIZE_512K;
            cacheSize = 0x80000;
        }
        else
        {
            /* cache size is 256 KB */
            picr2CacheSize = PICR2_L2_SIZE_256K;
            cacheSize = 0x40000;
        }

        /* setup PICR1 */
        mask =
            ~(PICR1_CF_BREAD_WS(1) |
              PICR1_CF_BREAD_WS(2) |
              PICR1_CF_CBA(0xff) |
              PICR1_CF_CACHE_1G |
              PICR1_CF_DPARK |
              PICR1_CF_APARK |
              PICR1_CF_L2_CACHE_MASK);

        picr1 =
            (PICR1_CF_CBA(0x3f) |
             PICR1_CF_CACHE_1G |
             PICR1_CF_APARK |
             PICR1_CF_DPARK |
             PICR1_CF_L2_COPY_BACK); /* PICR1_CF_L2_WRITE_THROUGH */

        pci_read_config_dword  (devbusfn, PCI_PICR1, &reg32);
        reg32 &= mask;
        reg32 |= picr1;
        pci_write_config_dword (devbusfn, PCI_PICR1, reg32);

        /*
         * invalidate all L2 cache
         */
        picr2 =
            (PICR2_CF_INV_MODE |
             PICR2_CF_HIT_HIGH |
             PICR2_CF_MOD_HIGH |
             PICR2_CF_L2_HIT_DELAY(1) |
             PICR2_CF_APHASE_WS(1) |
             picr2CacheSize);

        pci_write_config_dword (devbusfn, PCI_PICR2, picr2);

        /*
         * dummy transactions
         */
        for (d=0; d<(int *)(2*cacheSize); d++)
            dummy(*d);

        pci_write_config_dword (devbusfn, PCI_PICR2,
                                (picr2 | PICR2_CF_FLUSH_L2));

        /* setup PICR2 */
        picr2 =
            (PICR2_CF_FAST_CASTOUT |
             PICR2_CF_WDATA |
             PICR2_CF_ADDR_ONLY_DISABLE |
             PICR2_CF_HIT_HIGH |
             PICR2_CF_MOD_HIGH |
             PICR2_L2_UPDATE_EN |
             PICR2_L2_EN |
             PICR2_CF_APHASE_WS(1) |
             PICR2_CF_DATA_RAM_PBURST |
             PICR2_CF_L2_HIT_DELAY(1) |
             PICR2_CF_SNOOP_WS(2) |
             picr2CacheSize);

        pci_write_config_dword (devbusfn, PCI_PICR2, picr2);
    }
    return (0);
}
Exemple #2
0
void pci_init_board(void)
{
    struct pci_controller* hose = (struct pci_controller *)&local_hose;
    u32 reg32;
    u16 reg16;

    hose->first_busno = 0;
    hose->last_busno = 0xff;

    pci_set_region(hose->regions + 0,
	CFG_PCI_MEMORY_BUS,
	CFG_PCI_MEMORY_PHYS,
    /*
    * Attention: pci_hose_phys_to_bus() failes in address compare,
    * so we need (CFG_PCI_MEMORY_SIZE-1)
    */
	CFG_PCI_MEMORY_SIZE-1,
	PCI_REGION_MEM | PCI_REGION_MEMORY);

    /* PCI memory space */
    pci_set_region(hose->regions + 1,
	CFG_PCI_MEM_BUS,
	CFG_PCI_MEM_PHYS,
	CFG_PCI_MEM_SIZE,
	PCI_REGION_MEM);

    /* ISA/PCI memory space */
    pci_set_region(hose->regions + 2,
	CFG_ISA_MEM_BUS,
	CFG_ISA_MEM_PHYS,
	CFG_ISA_MEM_SIZE,
	PCI_REGION_MEM);

    /* PCI I/O space */
    pci_set_region(hose->regions + 3,
	CFG_PCI_IO_BUS,
	CFG_PCI_IO_PHYS,
	CFG_PCI_IO_SIZE,
	PCI_REGION_IO);

    /* ISA/PCI I/O space */
    pci_set_region(hose->regions + 4,
	CFG_ISA_IO_BUS,
	CFG_ISA_IO_PHYS,
	CFG_ISA_IO_SIZE,
	PCI_REGION_IO);

    hose->region_count = 5;

    pci_setup_indirect(hose,
	MPC106_REG_ADDR,
	MPC106_REG_DATA);

    pci_register_hose(hose);

    hose->last_busno = pci_hose_scan(hose);

    /* Initialises the MPC10x PCI Configuration regs. */
    pci_read_config_dword (PCI_BDF(0,0,0), PCI_PICR2, &reg32);
    reg32 |= PICR2_CF_SNOOP_WS(3) |
	     PICR2_CF_FLUSH_L2 |
	     PICR2_CF_L2_HIT_DELAY(3) |
	     PICR2_CF_APHASE_WS(3);
    reg32 &= ~(PICR2_L2_EN | PICR2_L2_UPDATE_EN);
    pci_write_config_dword (PCI_BDF(0,0,0), PCI_PICR2, reg32);

    pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, &reg16);
    reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
    pci_write_config_word(PCI_BDF(0,0,0), PCI_COMMAND, reg16);

    /* Clear non-reserved bits in status register */
    pci_write_config_word(PCI_BDF(0,0,0), PCI_STATUS, 0xffff);

    pci_read_config_dword (PCI_BDF(0,0,0), PCI_PICR1, &reg32);
    reg32 |= PICR1_CF_CBA(63) |
	     PICR1_CF_BREAD_WS(2) |
	     PICR1_MCP_EN |
	     PICR1_CF_DPARK |
	     PICR1_PROC_TYPE_604 |
	     PICR1_CF_LOOP_SNOOP |
	     PICR1_CF_APARK;
    pci_write_config_dword (PCI_BDF(0,0,0), PCI_PICR1, reg32);
}