void PIT_enable(uint32_t ldval) { SIM -> SCGC6 |= SIM_SCGC6_PIT_MASK;//enable PIT clock gate PIT -> MCR = ~PIT_MCR_MDIS_MASK; //PIT ->MCR = 0x00U;PIT_MCR: MDIS=0,FRZ=0 : Enable device clock// ~PIT_MCR_MDIS_MASK PIT -> PIT ->CHANNEL[0].TCTRL = 0X00U;/* PIT_TCTRL0: CHN=0,TIE=0,TEN=0 : Clear control register*/ PIT ->CHANNEL[0].TFLG = PIT_TFLG_TIF_MASK;/* PIT_TFLG0: TIF=1: Clear timer flag register */ PIT->CHANNEL[0].LDVAL = PIT_LDVAL_TSV(ldval); /* PIT_LDVAL0: TSV=0xD1B6: Set up load register */ NVIC_SetPriority(22, 2); /* Set priority for PIT IRQ22 */ NVIC_EnableIRQ(22); /* Enable IRQ for PIT IRQ22 */ /* PIT_TCTRL0: CHN=0,TIE=1,TEN=1 */ PIT->CHANNEL[0].TCTRL = (PIT_TCTRL_TIE_MASK | PIT_TCTRL_TEN_MASK); /* Set up control register */ }
/* ===================================================================*/ LDD_TDeviceData* TU1_Init(LDD_TUserData *UserDataPtr) { TU1_TDeviceData *DeviceDataPrv; if (PE_LDD_DeviceDataList[PE_LDD_COMPONENT_TU1_ID] == NULL) { /* Allocate device structure */ /* {Default RTOS Adapter} Driver memory allocation: Dynamic allocation is simulated by a pointer to the static object */ DeviceDataPrv = &DeviceDataPrv__DEFAULT_RTOS_ALLOC; DeviceDataPrv->UserDataPtr = UserDataPtr; /* Store the RTOS device structure */ DeviceDataPrv->InitCntr = 1U; /* First initialization */ } else { /* Memory is already allocated */ DeviceDataPrv = (TU1_TDeviceDataPtr) PE_LDD_DeviceDataList[PE_LDD_COMPONENT_TU1_ID]; DeviceDataPrv->UserDataPtr = UserDataPtr; /* Store the RTOS device structure */ DeviceDataPrv->InitCntr++; /* Increment counter of initialization */ return ((LDD_TDeviceData *)DeviceDataPrv); /* Return pointer to the device data structure */ } /* Interrupt vector(s) allocation */ /* {Default RTOS Adapter} Set interrupt vector: IVT is static, ISR parameter is passed by the global variable */ INT_PIT__DEFAULT_RTOS_ISRPARAM = DeviceDataPrv; /* SIM_SCGC6: PIT=1 */ SIM_SCGC6 |= SIM_SCGC6_PIT_MASK; /* PIT_MCR: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,MDIS=0,FRZ=0 */ PIT_MCR = 0x00U; /* Enable device clock */ /* PIT_TCTRL0: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHN=0,TIE=0,TEN=0 */ PIT_TCTRL0 = 0x00U; /* Clear control register */ /* PIT_TFLG0: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,TIF=1 */ PIT_TFLG0 = PIT_TFLG_TIF_MASK; /* Clear timer flag register */ /* PIT_LDVAL0: TSV=0x4E1F */ PIT_LDVAL0 = PIT_LDVAL_TSV(0x4E1F); /* Set up load register */ /* NVIC_IPR5: PRI_22=0x80 */ NVIC_IPR5 = (uint32_t)((NVIC_IPR5 & (uint32_t)~(uint32_t)( NVIC_IP_PRI_22(0x7F) )) | (uint32_t)( NVIC_IP_PRI_22(0x80) )); /* NVIC_ISER: SETENA|=0x00400000 */ NVIC_ISER |= NVIC_ISER_SETENA(0x00400000); /* PIT_TCTRL0: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHN=0,TIE=1,TEN=1 */ PIT_TCTRL0 = (PIT_TCTRL_TIE_MASK | PIT_TCTRL_TEN_MASK); /* Set up control register */ /* Registration of the device structure */ PE_LDD_RegisterDeviceStructure(PE_LDD_COMPONENT_TU1_ID,DeviceDataPrv); return ((LDD_TDeviceData *)DeviceDataPrv); /* Return pointer to the device data structure */ }
void Init_PIT(unsigned period) { // Enable clock to PIT module SIM->SCGC6 |= SIM_SCGC6_PIT_MASK; // Enable module, freeze timers in debug mode PIT->MCR &= ~PIT_MCR_MDIS_MASK; PIT->MCR |= PIT_MCR_FRZ_MASK; // Initialize PIT0 to count down from argument PIT->CHANNEL[0].LDVAL = PIT_LDVAL_TSV(period); // No chaining PIT->CHANNEL[0].TCTRL &= PIT_TCTRL_CHN_MASK; // Generate interrupts PIT->CHANNEL[0].TCTRL |= PIT_TCTRL_TIE_MASK; /* Enable Interrupts */ NVIC_SetPriority(PIT_IRQn, 128); // 0, 64, 128 or 192 NVIC_ClearPendingIRQ(PIT_IRQn); NVIC_EnableIRQ(PIT_IRQn); }