int board_init (void)
{
icache_enable();
/* address for the kernel command line */
gd->bd->bi_boot_params = 0x800;
/* enable board LEDs for output */
PUT_REG( REG_IOPDATA, 0x0);
PUT_REG( REG_IOPMODE, 0xFFFF);
PUT_REG( REG_IOPDATA, 0xFF);
return 0;
}
static s32 RxFDinit( ETH *eth) {
s32 i;
/* MACFrame *rxFrmBase; */
/* disable cache for access to the RX buffers */
/* rxFrmBase = (MACFrame *)( (u32)rxFrameBase | CACHE_DISABLE_MASK); */
/* store start of Rx descriptors and set current */
eth->m_curRX_FD = (RX_FrameDescriptor *)((u32)rxFDbase | CACHE_DISABLE_MASK);
eth->m_baseRX_FD = eth->m_curRX_FD;
for ( i = 0; i < PKTBUFSRX; i++) {
eth->m_baseRX_FD[i].m_frameDataPtr.bf.dataPtr = (u32)NetRxPackets[i] | CACHE_DISABLE_MASK;
eth->m_baseRX_FD[i].m_frameDataPtr.bf.owner = 0x1; /* BDMA owner */
eth->m_baseRX_FD[i].m_reserved = 0x0;
eth->m_baseRX_FD[i].m_status.ui = 0x0;
eth->m_baseRX_FD[i].m_nextFD = ð->m_baseRX_FD[i+1];
}
/* make the list circular */
eth->m_baseRX_FD[i-1].m_nextFD = ð->m_baseRX_FD[0];
PUT_REG( REG_BDMARXPTR, (u32)eth->m_curRX_FD);
return 0;
}
static s32 TxFDinit( ETH *eth) {
s32 i;
MACFrame *txFrmBase;
/* disable cache for access to the TX buffers */
txFrmBase = (MACFrame *)( (u32)txFrameBase | CACHE_DISABLE_MASK);
/* store start of Tx descriptors and set current */
eth->m_curTX_FD = (TX_FrameDescriptor *) ((u32)txFDbase | CACHE_DISABLE_MASK);
eth->m_baseTX_FD = eth->m_curTX_FD;
for ( i = 0; i < ETH_MaxTxFrames; i++) {
eth->m_baseTX_FD[i].m_frameDataPtr.bf.dataPtr = (u32)&txFrmBase[i];
eth->m_baseTX_FD[i].m_frameDataPtr.bf.owner = 0x0; /* CPU owner */
eth->m_baseTX_FD[i].m_opt.ui = 0x0;
eth->m_baseTX_FD[i].m_status.ui = 0x0;
eth->m_baseTX_FD[i].m_nextFD = ð->m_baseTX_FD[i+1];
}
/* make the list circular */
eth->m_baseTX_FD[i-1].m_nextFD = ð->m_baseTX_FD[0];
PUT_REG( REG_BDMATXPTR, (u32)eth->m_curTX_FD);
return 0;
}
/* Check for received packets */
s32 eth_rx (void)
{
s32 nLen = 0;
ETH *eth = &m_eth;
/* check if packet ready */
if ( (GET_REG( REG_BDMASTAT)) & ETH_S_BRxRDF) {
/* process all waiting packets */
while ( !eth->m_curRX_FD->m_frameDataPtr.bf.owner) {
nLen = eth->m_curRX_FD->m_status.bf.len;
/* call back u-boot -- may call eth_send() */
NetReceive ((u8 *)eth->m_curRX_FD->m_frameDataPtr.ui, nLen);
/* set owner back to CPU */
eth->m_curRX_FD->m_frameDataPtr.bf.owner = 1;
/* clear status */
eth->m_curRX_FD->m_status.ui = 0x0;
/* advance to next descriptor */
eth->m_curRX_FD = eth->m_curRX_FD->m_nextFD;
/* clear received frame bit */
PUT_REG( REG_BDMASTAT, ETH_S_BRxRDF);
}
}
return nLen;
}
static void timer_isr( void *data) {
unsigned int *pTime = (unsigned int *)data;
(*pTime)++;
if ( !(*pTime % (CFG_HZ/4))) {
/* toggle LED 0 */
PUT_REG( REG_IOPDATA, GET_REG(REG_IOPDATA) ^ 0x1);
}
}
int arch_interrupt_init (void)
{
int i;
/* install default interrupt handlers */
for ( i = 0; i < N_IRQS; i++) {
IRQ_HANDLER[i].m_data = (void *)i;
IRQ_HANDLER[i].m_func = default_isr;
}
/* configure interrupts for IRQ mode */
PUT_REG( REG_INTMODE, 0x0);
/* clear any pending interrupts */
PUT_REG( REG_INTPEND, 0x1FFFFF);
lastdec = 0;
/* install interrupt handler for timer */
IRQ_HANDLER[INT_TIMER0].m_data = (void *)×tamp;
IRQ_HANDLER[INT_TIMER0].m_func = timer_isr;
return 0;
}
int interrupt_init (void)
{
#if defined(CONFIG_NETARM)
/* disable all interrupts */
IRQEN = 0;
/* operate timer 2 in non-prescale mode */
TM2CTRL = ( NETARM_GEN_TIMER_SET_HZ(CFG_HZ) |
NETARM_GEN_TCTL_ENABLE |
NETARM_GEN_TCTL_INIT_COUNT(TIMER_LOAD_VAL));
/* set timer 2 counter */
lastdec = TIMER_LOAD_VAL;
#elif defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_ARMADILLO)
/* disable all interrupts */
IO_INTMR1 = 0;
/* operate timer 1 in prescale mode */
IO_SYSCON1 |= SYSCON1_TC1M;
/* select 2kHz clock source for timer 1 */
IO_SYSCON1 &= ~SYSCON1_TC1S;
/* set timer 1 counter */
lastdec = IO_TC1D = TIMER_LOAD_VAL;
#elif defined(CONFIG_S3C4510B)
int i;
/* install default interrupt handlers */
for ( i = 0; i < N_IRQS; i++) {
IRQ_HANDLER[i].m_data = (void *)i;
IRQ_HANDLER[i].m_func = default_isr;
}
/* configure interrupts for IRQ mode */
PUT_REG( REG_INTMODE, 0x0);
/* clear any pending interrupts */
PUT_REG( REG_INTPEND, 0x1FFFFF);
lastdec = 0;
/* install interrupt handler for timer */
IRQ_HANDLER[INT_TIMER0].m_data = (void *)×tamp;
IRQ_HANDLER[INT_TIMER0].m_func = timer_isr;
/* configure free running timer 0 */
PUT_REG( REG_TMOD, 0x0);
/* Stop timer 0 */
CLR_REG( REG_TMOD, TM0_RUN);
/* Configure for interval mode */
CLR_REG( REG_TMOD, TM1_TOGGLE);
/*
* Load Timer data register with count down value.
* count_down_val = CFG_SYS_CLK_FREQ/CFG_HZ
*/
PUT_REG( REG_TDATA0, (CFG_SYS_CLK_FREQ / CFG_HZ));
/*
* Enable global interrupt
* Enable timer0 interrupt
*/
CLR_REG( REG_INTMASK, ((1<<INT_GLOBAL) | (1<<INT_TIMER0)));
/* Start timer */
SET_REG( REG_TMOD, TM0_RUN);
#elif defined(CONFIG_LPC2292)
PUT32(T0IR, 0); /* disable all timer0 interrupts */
PUT32(T0TCR, 0); /* disable timer0 */
PUT32(T0PR, CFG_SYS_CLK_FREQ / CFG_HZ);
PUT32(T0MCR, 0);
PUT32(T0TC, 0);
PUT32(T0TCR, 1); /* enable timer0 */
#else
#error No interrupt_init() defined for this CPU type
#endif
timestamp = 0;
return (0);
}
int timer_init (void)
{
#if defined(CONFIG_NETARM)
/* disable all interrupts */
IRQEN = 0;
/* operate timer 2 in non-prescale mode */
TM2CTRL = ( NETARM_GEN_TIMER_SET_HZ(CONFIG_SYS_HZ) |
NETARM_GEN_TCTL_ENABLE |
NETARM_GEN_TCTL_INIT_COUNT(TIMER_LOAD_VAL));
/* set timer 2 counter */
lastdec = TIMER_LOAD_VAL;
#elif defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_ARMADILLO)
/* disable all interrupts */
IO_INTMR1 = 0;
/* operate timer 1 in prescale mode */
IO_SYSCON1 |= SYSCON1_TC1M;
/* select 2kHz clock source for timer 1 */
IO_SYSCON1 &= ~SYSCON1_TC1S;
/* set timer 1 counter */
lastdec = IO_TC1D = TIMER_LOAD_VAL;
#elif defined(CONFIG_S3C4510B)
/* configure free running timer 0 */
PUT_REG( REG_TMOD, 0x0);
/* Stop timer 0 */
CLR_REG( REG_TMOD, TM0_RUN);
/* Configure for interval mode */
CLR_REG( REG_TMOD, TM1_TOGGLE);
/*
* Load Timer data register with count down value.
* count_down_val = CONFIG_SYS_SYS_CLK_FREQ/CONFIG_SYS_HZ
*/
PUT_REG( REG_TDATA0, (CONFIG_SYS_SYS_CLK_FREQ / CONFIG_SYS_HZ));
/*
* Enable global interrupt
* Enable timer0 interrupt
*/
CLR_REG( REG_INTMASK, ((1<<INT_GLOBAL) | (1<<INT_TIMER0)));
/* Start timer */
SET_REG( REG_TMOD, TM0_RUN);
#elif defined(CONFIG_LPC2292)
PUT32(T0IR, 0); /* disable all timer0 interrupts */
PUT32(T0TCR, 0); /* disable timer0 */
PUT32(T0PR, CONFIG_SYS_SYS_CLK_FREQ / CONFIG_SYS_HZ);
PUT32(T0MCR, 0);
PUT32(T0TC, 0);
PUT32(T0TCR, 1); /* enable timer0 */
#else
#error No timer_init() defined for this CPU type
#endif
timestamp = 0;
return (0);
}
int eth_init(bd_t *bis)
{
ETH *eth = &m_eth;
/* store our MAC address */
eth->m_mac = bis->bi_enetaddr;
/* setup DBMA and MAC */
PUT_REG( REG_BDMARXCON, ETH_BRxRS); /* reset BDMA RX machine */
PUT_REG( REG_BDMATXCON, ETH_BTxRS); /* reset BDMA TX machine */
PUT_REG( REG_MACCON , ETH_SwReset); /* reset MAC machine */
PUT_REG( REG_BDMARXLSZ, sizeof(MACFrame));
PUT_REG( REG_MACCON , 0); /* reset MAC machine */
/* init frame descriptors */
TxFDinit( eth);
RxFDinit( eth);
/* init the CAM with our MAC address */
PUT_REG( REG_CAM_BASE, (eth->m_mac[0] << 24) |
(eth->m_mac[1] << 16) |
(eth->m_mac[2] << 8) |
(eth->m_mac[3]));
PUT_REG( REG_CAM_BASE + 0x4, (eth->m_mac[4] << 24) |
(eth->m_mac[5] << 16));
/* enable CAM address 1 -- the MAC we just loaded */
PUT_REG( REG_CAMEN, 0x1);
PUT_REG( REG_CAMCON,
ETH_BroadAcc | /* accept broadcast packetes */
ETH_CompEn); /* enable compare mode (check against the CAM) */
/* configure the BDMA Transmitter control */
PUT_REG( REG_BDMATXCON,
ETH_BTxBRST | /* BDMA Tx burst size 16 words */
ETH_BTxMSL110 | /* BDMA Tx wait to fill 6/8 of the BDMA */
ETH_BTxSTSKO | /* BDMA Tx interrupt(Stop) on non-owner TX FD */
ETH_BTxEn); /* BDMA Tx Enable */
/* configure the MAC Transmitter control */
PUT_REG( REG_MACTXCON,
ETH_EnComp | /* interrupt when the MAC transmits or discards packet */
ETH_TxEn); /* MAC transmit enable */
/* configure the BDMA Receiver control */
PUT_REG( REG_BDMARXCON,
ETH_BRxBRST | /* BDMA Rx Burst Size 16 words */
ETH_BRxSTSKO | /* BDMA Rx interrupt(Stop) on non-owner RX FD */
ETH_BRxMAINC | /* BDMA Rx Memory Address increment */
ETH_BRxDIE | /* BDMA Rx Every Received Frame Interrupt Enable */
ETH_BRxNLIE | /* BDMA Rx NULL List Interrupt Enable */
ETH_BRxNOIE | /* BDMA Rx Not Owner Interrupt Enable */
ETH_BRxLittle | /* BDMA Rx Little endian */
ETH_BRxEn); /* BDMA Rx Enable */
/* configure the MAC Receiver control */
PUT_REG( REG_MACRXCON,
ETH_RxEn); /* MAC ETH_RxEn */
return 0;
}
/* Halt ethernet engine */
void eth_halt(void)
{
/* disable MAC */
PUT_REG( REG_MACCON, ETH_HaltReg);
}