static void find_npu_checkstop_reason(int flat_chip_id,
struct OpalHMIEvent *hmi_evt,
uint64_t *out_flags)
{
struct phb *phb;
struct npu *p = NULL;
uint64_t npu_fir;
uint64_t npu_fir_mask;
uint64_t npu_fir_action0;
uint64_t npu_fir_action1;
uint64_t fatal_errors;
/* Only check for NPU errors if the chip has a NPU */
if (PVR_TYPE(mfspr(SPR_PVR)) != PVR_TYPE_P8NVL)
return find_npu2_checkstop_reason(flat_chip_id, hmi_evt, out_flags);
/* Find the NPU on the chip associated with the HMI. */
for_each_phb(phb) {
/* NOTE: if a chip ever has >1 NPU this will need adjusting */
if (dt_node_is_compatible(phb->dt_node, "ibm,power8-npu-pciex") &&
(dt_get_chip_id(phb->dt_node) == flat_chip_id)) {
p = phb_to_npu(phb);
break;
}
}
/* If we didn't find a NPU on the chip, it's not our checkstop. */
if (p == NULL)
return;
/* Read all the registers necessary to find a checkstop condition. */
if (xscom_read(flat_chip_id,
p->at_xscom + NX_FIR, &npu_fir) ||
xscom_read(flat_chip_id,
p->at_xscom + NX_FIR_MASK, &npu_fir_mask) ||
xscom_read(flat_chip_id,
p->at_xscom + NX_FIR_ACTION0, &npu_fir_action0) ||
xscom_read(flat_chip_id,
p->at_xscom + NX_FIR_ACTION1, &npu_fir_action1)) {
prerror("Couldn't read NPU registers with XSCOM\n");
return;
}
fatal_errors = npu_fir & ~npu_fir_mask & npu_fir_action0 & npu_fir_action1;
/* If there's no errors, we don't need to do anything. */
if (!fatal_errors)
return;
prlog(PR_DEBUG, "NPU: FIR 0x%016llx mask 0x%016llx\n",
npu_fir, npu_fir_mask);
prlog(PR_DEBUG, "NPU: ACTION0 0x%016llx, ACTION1 0x%016llx\n",
npu_fir_action0, npu_fir_action1);
/* Set the NPU to fenced since it can't recover. */
npu_set_fence_state(p, true);
/* Set up the HMI event */
hmi_evt->severity = OpalHMI_SEV_WARNING;
hmi_evt->type = OpalHMI_ERROR_MALFUNC_ALERT;
hmi_evt->u.xstop_error.xstop_type = CHECKSTOP_TYPE_NPU;
hmi_evt->u.xstop_error.u.chip_id = flat_chip_id;
/* The HMI is "recoverable" because it shouldn't crash the system */
queue_hmi_event(hmi_evt, 1, out_flags);
}
struct dt_node * add_core_common(struct dt_node *cpus,
const struct sppcia_cpu_cache *cache,
const struct sppaca_cpu_timebase *tb,
uint32_t int_server, bool okay)
{
const char *name;
struct dt_node *cpu;
uint32_t version;
uint64_t freq;
const uint8_t pa_features[] = {
6, 0, 0xf6, 0x3f, 0xc7, 0x00, 0x80, 0xc0 };
printf(" Cache: I=%u D=%u/%u/%u/%u\n",
be32_to_cpu(cache->icache_size_kb),
be32_to_cpu(cache->l1_dcache_size_kb),
be32_to_cpu(cache->l2_dcache_size_kb),
be32_to_cpu(cache->l3_dcache_size_kb),
be32_to_cpu(cache->l35_dcache_size_kb));
/* Use the boot CPU PVR to make up a CPU name in the device-tree
* since the HDAT doesn't seem to tell....
*/
version = mfspr(SPR_PVR);
switch(PVR_TYPE(version)) {
case PVR_TYPE_P7:
name = "PowerPC,POWER7";
break;
case PVR_TYPE_P7P:
name = "PowerPC,POWER7+";
break;
case PVR_TYPE_P8E:
case PVR_TYPE_P8:
name = "PowerPC,POWER8";
break;
default:
name = "PowerPC,Unknown";
}
cpu = dt_new_addr(cpus, name, int_server);
assert(cpu);
dt_add_property_string(cpu, "device_type", "cpu");
dt_add_property_string(cpu, "status", okay ? "okay" : "bad");
dt_add_property_cells(cpu, "reg", int_server);
dt_add_property_cells(cpu, "cpu-version", version);
dt_add_property(cpu, "64-bit", NULL, 0);
dt_add_property(cpu, "32-64-bridge", NULL, 0);
dt_add_property(cpu, "graphics", NULL, 0);
dt_add_property(cpu, "general-purpose", NULL, 0);
dt_add_property_cells(cpu, "ibm,processor-segment-sizes",
0x1c, 0x28, 0xffffffff, 0xffffffff);
dt_add_property_cells(cpu, "ibm,processor-page-sizes",
0xc, 0x10, 0x18, 0x22);
/* Page size encodings appear to be the same for P7 and P8 */
dt_add_property_cells(cpu, "ibm,segment-page-sizes",
0x0c, 0x000, 3, 0x0c, 0x0000, /* 4K seg 4k pages */
0x10, 0x0007, /* 4K seg 64k pages */
0x18, 0x0038, /* 4K seg 16M pages */
0x10, 0x110, 2, 0x10, 0x0001, /* 64K seg 64k pages */
0x18, 0x0008, /* 64K seg 16M pages */
0x18, 0x100, 1, 0x18, 0x0000, /* 16M seg 16M pages */
0x22, 0x120, 1, 0x22, 0x0003); /* 16G seg 16G pages */
dt_add_property(cpu, "ibm,pa-features",
pa_features, sizeof(pa_features));
dt_add_property_cells(cpu, "ibm,slb-size", 0x20);
dt_add_property_cells(cpu, "ibm,vmx", 0x2);
dt_add_property_cells(cpu, "ibm,dfp", 0x2);
dt_add_property_cells(cpu, "ibm,purr", 0x1);
dt_add_property_cells(cpu, "ibm,spurr", 0x1);
/*
* Do not create "clock-frequency" if the frequency doesn't
* fit in a single cell
*/
freq = ((uint64_t)be32_to_cpu(tb->actual_clock_speed)) * 1000000ul;
if (freq <= 0xfffffffful)
dt_add_property_cells(cpu, "clock-frequency", freq);
dt_add_property_cells(cpu, "ibm,extended-clock-frequency",
hi32(freq), lo32(freq));
/* FIXME: Hardcoding is bad. */
dt_add_property_cells(cpu, "timebase-frequency", 512000000);
dt_add_property_cells(cpu, "ibm,extended-timebase-frequency",
0, 512000000);
dt_add_property_cells(cpu, "reservation-granule-size",
be32_to_cpu(cache->reservation_size));
dt_add_property_cells(cpu, "d-tlb-size",
be32_to_cpu(cache->dtlb_entries));
dt_add_property_cells(cpu, "i-tlb-size",
be32_to_cpu(cache->itlb_entries));
/* Assume unified TLB */
dt_add_property_cells(cpu, "tlb-size",
be32_to_cpu(cache->dtlb_entries));
dt_add_property_cells(cpu, "d-tlb-sets",
be32_to_cpu(cache->dtlb_assoc_sets));
dt_add_property_cells(cpu, "i-tlb-sets",
be32_to_cpu(cache->itlb_assoc_sets));
dt_add_property_cells(cpu, "tlb-sets",
be32_to_cpu(cache->dtlb_assoc_sets));
dt_add_property_cells(cpu, "d-cache-block-size",
be32_to_cpu(cache->dcache_block_size));
dt_add_property_cells(cpu, "i-cache-block-size",
be32_to_cpu(cache->icache_block_size));
dt_add_property_cells(cpu, "d-cache-size",
be32_to_cpu(cache->l1_dcache_size_kb)*1024);
dt_add_property_cells(cpu, "i-cache-size",
be32_to_cpu(cache->icache_size_kb)*1024);
dt_add_property_cells(cpu, "i-cache-sets",
be32_to_cpu(cache->icache_assoc_sets));
dt_add_property_cells(cpu, "d-cache-sets",
be32_to_cpu(cache->dcache_assoc_sets));
if (cache->icache_line_size != cache->icache_block_size)
dt_add_property_cells(cpu, "i-cache-line-size",
be32_to_cpu(cache->icache_line_size));
if (cache->l1_dcache_line_size != cache->dcache_block_size)
dt_add_property_cells(cpu, "d-cache-line-size",
be32_to_cpu(cache->l1_dcache_line_size));
return cpu;
}
struct dt_node * add_core_common(struct dt_node *cpus,
const struct sppcia_cpu_cache *cache,
const struct sppaca_cpu_timebase *tb,
uint32_t int_server, bool okay)
{
const char *name;
struct dt_node *cpu;
uint32_t version;
uint64_t freq;
const uint8_t pa_features_p7[] = {
6, 0,
0xf6, 0x3f, 0xc7, 0x00, 0x80, 0xc0 };
const uint8_t pa_features_p7p[] = {
6, 0,
0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xc0 };
const uint8_t pa_features_p8[] = {
24, 0,
0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xd0, 0x80, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00,
};
const uint8_t pa_features_p9n_dd20[] = {
64, 0,
0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xd0, 0x80, 0x00, /* 0 .. 7 */
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 8 .. 15 */
0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 16 .. 23 */
0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 24 .. 31 */
0x80, 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, /* 32 .. 39 */
0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 40 .. 47 */
0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 .. 55 */
0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 56 .. 63 */
};
const uint8_t pa_features_p9[] = {
64, 0,
0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xd0, 0x80, 0x00, /* 0 .. 7 */
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 8 .. 15 */
0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 16 .. 23 */
0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 24 .. 31 */
0x80, 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, /* 32 .. 39 */
0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 40 .. 47 */
0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 .. 55 */
0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 56 .. 63 */
};
const uint8_t *pa_features;
size_t pa_features_size;
prlog(PR_INFO, " Cache: I=%u D=%u/%u/%u/%u\n",
be32_to_cpu(cache->icache_size_kb),
be32_to_cpu(cache->l1_dcache_size_kb),
be32_to_cpu(cache->l2_dcache_size_kb),
be32_to_cpu(cache->l3_dcache_size_kb),
be32_to_cpu(cache->l35_dcache_size_kb));
/* Use the boot CPU PVR to make up a CPU name in the device-tree
* since the HDAT doesn't seem to tell....
*/
version = mfspr(SPR_PVR);
switch(PVR_TYPE(version)) {
case PVR_TYPE_P7:
name = "PowerPC,POWER7";
pa_features = pa_features_p7;
pa_features_size = sizeof(pa_features_p7);
break;
case PVR_TYPE_P7P:
name = "PowerPC,POWER7+";
pa_features = pa_features_p7p;
pa_features_size = sizeof(pa_features_p7p);
break;
case PVR_TYPE_P8E:
case PVR_TYPE_P8:
case PVR_TYPE_P8NVL:
name = "PowerPC,POWER8";
pa_features = pa_features_p8;
pa_features_size = sizeof(pa_features_p8);
break;
case PVR_TYPE_P9:
case PVR_TYPE_P9P:
name = "PowerPC,POWER9";
if (is_power9n(version) &&
(PVR_VERS_MAJ(version) == 2) &&
(PVR_VERS_MIN(version) == 0)) {
/* P9N DD2.0 */
pa_features = pa_features_p9n_dd20;
pa_features_size = sizeof(pa_features_p9n_dd20);
} else {
pa_features = pa_features_p9;
pa_features_size = sizeof(pa_features_p9);
}
break;
default:
name = "PowerPC,Unknown";
pa_features = NULL;
}
cpu = dt_new_addr(cpus, name, int_server);
assert(cpu);
dt_add_property_string(cpu, "device_type", "cpu");
dt_add_property_string(cpu, "status", okay ? "okay" : "bad");
dt_add_property_cells(cpu, "reg", int_server);
dt_add_property_cells(cpu, "cpu-version", version);
dt_add_property(cpu, "64-bit", NULL, 0);
dt_add_property(cpu, "32-64-bridge", NULL, 0);
dt_add_property(cpu, "graphics", NULL, 0);
dt_add_property(cpu, "general-purpose", NULL, 0);
dt_add_property_cells(cpu, "ibm,processor-segment-sizes",
0x1c, 0x28, 0xffffffff, 0xffffffff);
dt_add_property_cells(cpu, "ibm,processor-page-sizes",
0xc, 0x10, 0x18, 0x22);
if (proc_gen == proc_gen_p9)
dt_add_property_cells(cpu, "ibm,processor-radix-AP-encodings",
0x0000000c, 0xa0000010, 0x20000015, 0x4000001e);
/* Page size encodings appear to be the same for P7 and P8 */
dt_add_property_cells(cpu, "ibm,segment-page-sizes",
0x0c, 0x000, 3, 0x0c, 0x0000, /* 4K seg 4k pages */
0x10, 0x0007, /* 4K seg 64k pages */
0x18, 0x0038, /* 4K seg 16M pages */
0x10, 0x110, 2, 0x10, 0x0001, /* 64K seg 64k pages */
0x18, 0x0008, /* 64K seg 16M pages */
0x18, 0x100, 1, 0x18, 0x0000, /* 16M seg 16M pages */
0x22, 0x120, 1, 0x22, 0x0003); /* 16G seg 16G pages */
if (pa_features) {
dt_add_property(cpu, "ibm,pa-features",
pa_features, pa_features_size);
}
dt_add_property_cells(cpu, "ibm,slb-size", 0x20);
dt_add_property_cells(cpu, "ibm,vmx", 0x2);
dt_add_property_cells(cpu, "ibm,dfp", 0x2);
dt_add_property_cells(cpu, "ibm,purr", 0x1);
dt_add_property_cells(cpu, "ibm,spurr", 0x1);
/*
* Do not create "clock-frequency" if the frequency doesn't
* fit in a single cell
*/
freq = ((uint64_t)be32_to_cpu(tb->actual_clock_speed)) * 1000000ul;
if (freq <= 0xfffffffful)
dt_add_property_cells(cpu, "clock-frequency", freq);
dt_add_property_u64(cpu, "ibm,extended-clock-frequency", freq);
/* FIXME: Hardcoding is bad. */
dt_add_property_cells(cpu, "timebase-frequency", 512000000);
dt_add_property_cells(cpu, "ibm,extended-timebase-frequency",
0, 512000000);
dt_add_property_cells(cpu, "reservation-granule-size",
be32_to_cpu(cache->reservation_size));
dt_add_property_cells(cpu, "d-tlb-size",
be32_to_cpu(cache->dtlb_entries));
dt_add_property_cells(cpu, "i-tlb-size",
be32_to_cpu(cache->itlb_entries));
/* Assume unified TLB */
dt_add_property_cells(cpu, "tlb-size",
be32_to_cpu(cache->dtlb_entries));
dt_add_property_cells(cpu, "d-tlb-sets",
be32_to_cpu(cache->dtlb_assoc_sets));
dt_add_property_cells(cpu, "i-tlb-sets",
be32_to_cpu(cache->itlb_assoc_sets));
dt_add_property_cells(cpu, "tlb-sets",
be32_to_cpu(cache->dtlb_assoc_sets));
dt_add_property_cells(cpu, "d-cache-block-size",
be32_to_cpu(cache->dcache_block_size));
dt_add_property_cells(cpu, "i-cache-block-size",
be32_to_cpu(cache->icache_block_size));
dt_add_property_cells(cpu, "d-cache-size",
be32_to_cpu(cache->l1_dcache_size_kb)*1024);
dt_add_property_cells(cpu, "i-cache-size",
be32_to_cpu(cache->icache_size_kb)*1024);
dt_add_property_cells(cpu, "i-cache-sets",
be32_to_cpu(cache->icache_assoc_sets));
dt_add_property_cells(cpu, "d-cache-sets",
be32_to_cpu(cache->dcache_assoc_sets));
if (cache->icache_line_size != cache->icache_block_size)
dt_add_property_cells(cpu, "i-cache-line-size",
be32_to_cpu(cache->icache_line_size));
if (cache->l1_dcache_line_size != cache->dcache_block_size)
dt_add_property_cells(cpu, "d-cache-line-size",
be32_to_cpu(cache->l1_dcache_line_size));
return cpu;
}
