/**
* Configure interrupt for a BAM pipe
*
*/
void bam_pipe_set_irq(void *base, u32 pipe, enum bam_enable irq_en,
u32 src_mask, u32 ee)
{
SPS_DBG2("sps:%s:bam=0x%x(va).pipe=%d.", __func__, (u32) base, pipe);
bam_write_reg(base, P_IRQ_EN(pipe), src_mask);
bam_write_reg_field(base, IRQ_SRCS_MSK_EE(ee), (1 << pipe), irq_en);
}
/**
* Configure a BAM pipe for satellite MTI use
*
*/
void bam_pipe_satellite_mti(void *base, u32 pipe, u32 irq_gen_addr, u32 ee)
{
bam_write_reg(base, P_IRQ_EN(pipe), 0);
bam_write_reg(base, P_IRQ_DEST_ADDR(pipe), irq_gen_addr);
bam_write_reg_field(base, IRQ_SIC_SEL, (1 << pipe), 1);
bam_write_reg_field(base, IRQ_SRCS_MSK, (1 << pipe), 1);
}
/**
* Configure a BAM pipe for satellite MTI use
*
*/
void bam_pipe_satellite_mti(void *base, u32 pipe, u32 irq_gen_addr, u32 ee)
{
bam_write_reg(base, P_IRQ_EN(pipe), 0);
#ifndef CONFIG_SPS_SUPPORT_NDP_BAM
bam_write_reg(base, P_IRQ_DEST_ADDR(pipe), irq_gen_addr);
bam_write_reg_field(base, IRQ_SIC_SEL, (1 << pipe), 1);
#endif
bam_write_reg_field(base, IRQ_SRCS_MSK, (1 << pipe), 1);
}
/**
* Reset the BAM pipe
*
*/
void bam_pipe_exit(void *base, u32 pipe, u32 ee)
{
bam_write_reg(base, P_IRQ_EN(pipe), 0);
/* Disable the Pipe Interrupt at the BAM level */
bam_write_reg_field(base, IRQ_SRCS_MSK_EE(ee), (1 << pipe), 0);
/* Pipe Disable */
bam_write_reg_field(base, P_CTRL(pipe), P_EN, 0);
}
void bam_pipe_set_mti(void *base, u32 pipe, enum bam_enable irq_en,
u32 src_mask, u32 irq_gen_addr)
{
#ifndef CONFIG_SPS_SUPPORT_NDP_BAM
bam_write_reg(base, P_IRQ_DEST_ADDR(pipe), irq_gen_addr);
#endif
if (!irq_en)
src_mask = 0;
bam_write_reg(base, P_IRQ_EN(pipe), src_mask);
}
/**
* Reset the BAM pipe
*
*/
void bam_pipe_exit(void *base, u32 pipe, u32 ee)
{
SPS_DBG2("sps:%s:bam=0x%x(va).pipe=%d.", __func__, (u32) base, pipe);
bam_write_reg(base, P_IRQ_EN(pipe), 0);
/* Disable the Pipe Interrupt at the BAM level */
bam_write_reg_field(base, IRQ_SRCS_MSK_EE(ee), (1 << pipe), 0);
/* Pipe Disable */
bam_write_reg_field(base, P_CTRL(pipe), P_EN, 0);
}
void bam_pipe_exit(void *base, u32 pipe, u32 ee)
{
SPS_DBG2("sps:%s:bam=0x%x(va).pipe=%d.", __func__, (u32) base, pipe);
bam_write_reg(base, P_IRQ_EN(pipe), 0);
bam_write_reg_field(base, IRQ_SRCS_MSK_EE(ee), (1 << pipe), 0);
bam_write_reg_field(base, P_CTRL(pipe), P_EN, 0);
}
/**
* Initialize a BAM pipe
*/
int bam_pipe_init(void *base, u32 pipe, struct bam_pipe_parameters *param,
u32 ee)
{
/* Reset the BAM pipe */
bam_write_reg(base, P_RST(pipe), 1);
/* No delay needed */
bam_write_reg(base, P_RST(pipe), 0);
/* Enable the Pipe Interrupt at the BAM level */
bam_write_reg_field(base, IRQ_SRCS_MSK_EE(ee), (1 << pipe), 1);
bam_write_reg(base, P_IRQ_EN(pipe), param->pipe_irq_mask);
bam_write_reg_field(base, P_CTRL(pipe), P_DIRECTION, param->dir);
bam_write_reg_field(base, P_CTRL(pipe), P_SYS_MODE, param->mode);
bam_write_reg(base, P_EVNT_GEN_TRSHLD(pipe), param->event_threshold);
bam_write_reg(base, P_DESC_FIFO_ADDR(pipe), param->desc_base);
bam_write_reg_field(base, P_FIFO_SIZES(pipe), P_DESC_FIFO_SIZE,
param->desc_size);
bam_write_reg_field(base, P_CTRL(pipe), P_SYS_STRM,
param->stream_mode);
if (param->mode == BAM_PIPE_MODE_BAM2BAM) {
u32 peer_dest_addr = param->peer_phys_addr +
P_EVNT_REG(param->peer_pipe);
bam_write_reg(base, P_DATA_FIFO_ADDR(pipe),
param->data_base);
bam_write_reg_field(base, P_FIFO_SIZES(pipe),
P_DATA_FIFO_SIZE, param->data_size);
bam_write_reg(base, P_EVNT_DEST_ADDR(pipe), peer_dest_addr);
SPS_DBG2("sps:bam=0x%x(va).pipe=%d.peer_bam=0x%x."
"peer_pipe=%d.\n",
(u32) base, pipe,
(u32) param->peer_phys_addr,
param->peer_pipe);
}
/* Pipe Enable - at last */
bam_write_reg_field(base, P_CTRL(pipe), P_EN, 1);
return 0;
}
/**
* Configure MTI for a BAM pipe
*
*/
void bam_pipe_set_mti(void *base, u32 pipe, enum bam_enable irq_en,
u32 src_mask, u32 irq_gen_addr)
{
/*
* MTI use is only supported on BAMs when global config is controlled
* by a remote processor.
* Consequently, the global configuration register to enable SIC (MTI)
* support cannot be accessed.
* The remote processor must be relied upon to enable the SIC and the
* interrupt. Since the remote processor enable both SIC and interrupt,
* the interrupt enable mask must be set to zero for polling mode.
*/
#ifndef CONFIG_SPS_SUPPORT_NDP_BAM
bam_write_reg(base, P_IRQ_DEST_ADDR(pipe), irq_gen_addr);
#endif
if (!irq_en)
src_mask = 0;
bam_write_reg(base, P_IRQ_EN(pipe), src_mask);
}
/**
* Configure interrupt for a BAM pipe
*
*/
void bam_pipe_set_irq(void *base, u32 pipe, enum bam_enable irq_en,
u32 src_mask, u32 ee)
{
bam_write_reg(base, P_IRQ_EN(pipe), src_mask);
bam_write_reg_field(base, IRQ_SRCS_MSK_EE(ee), (1 << pipe), irq_en);
}
/* output the content of selected BAM pipe registers */
void print_bam_pipe_selected_reg(void *virt_addr, u32 pipe_index)
{
void *base = virt_addr;
u32 pipe = pipe_index;
if (base == NULL)
return;
SPS_INFO("\nsps:----- Registers of Pipe %d -----\n", pipe);
SPS_INFO("BAM_P_CTRL: 0x%x\n"
"BAM_P_SYS_MODE: %d\n"
"BAM_P_DIRECTION: %d\n"
#ifdef CONFIG_SPS_SUPPORT_NDP_BAM
"BAM_P_LOCK_GROUP: 0x%x (%d)\n"
#endif
"BAM_P_EE: %d\n"
"BAM_P_IRQ_STTS: 0x%x\n"
"BAM_P_IRQ_STTS_P_TRNSFR_END_IRQ: 0x%x\n"
"BAM_P_IRQ_STTS_P_PRCSD_DESC_IRQ: 0x%x\n"
"BAM_P_IRQ_EN: %d\n"
"BAM_P_PRDCR_SDBNDn_BAM_P_BYTES_FREE: 0x%x (%d)\n"
"BAM_P_CNSMR_SDBNDn_BAM_P_BYTES_AVAIL: 0x%x (%d)\n"
"BAM_P_SW_DESC_OFST: 0x%x\n"
"BAM_P_DESC_FIFO_PEER_OFST: 0x%x\n"
"BAM_P_EVNT_DEST_ADDR: 0x%x\n"
"BAM_P_DESC_FIFO_ADDR: 0x%x\n"
"BAM_P_DESC_FIFO_SIZE: 0x%x (%d)\n"
"BAM_P_DATA_FIFO_ADDR: 0x%x\n"
"BAM_P_DATA_FIFO_SIZE: 0x%x (%d)\n"
"BAM_P_EVNT_GEN_TRSHLD: 0x%x (%d)\n",
bam_read_reg(base, P_CTRL(pipe)),
bam_read_reg_field(base, P_CTRL(pipe), P_SYS_MODE),
bam_read_reg_field(base, P_CTRL(pipe), P_DIRECTION),
#ifdef CONFIG_SPS_SUPPORT_NDP_BAM
bam_read_reg_field(base, P_CTRL(pipe), P_LOCK_GROUP),
bam_read_reg_field(base, P_CTRL(pipe), P_LOCK_GROUP),
#endif
bam_read_reg_field(base, P_TRUST_REG(pipe), BAM_P_EE),
bam_read_reg(base, P_IRQ_STTS(pipe)),
bam_read_reg_field(base, P_IRQ_STTS(pipe),
P_IRQ_STTS_P_TRNSFR_END_IRQ),
bam_read_reg_field(base, P_IRQ_STTS(pipe),
P_IRQ_STTS_P_PRCSD_DESC_IRQ),
bam_read_reg(base, P_IRQ_EN(pipe)),
bam_read_reg_field(base, P_PRDCR_SDBND(pipe),
P_PRDCR_SDBNDn_BAM_P_BYTES_FREE),
bam_read_reg_field(base, P_PRDCR_SDBND(pipe),
P_PRDCR_SDBNDn_BAM_P_BYTES_FREE),
bam_read_reg_field(base, P_CNSMR_SDBND(pipe),
P_CNSMR_SDBNDn_BAM_P_BYTES_AVAIL),
bam_read_reg_field(base, P_CNSMR_SDBND(pipe),
P_CNSMR_SDBNDn_BAM_P_BYTES_AVAIL),
bam_read_reg_field(base, P_SW_OFSTS(pipe), SW_DESC_OFST),
bam_read_reg_field(base, P_EVNT_REG(pipe),
P_DESC_FIFO_PEER_OFST),
bam_read_reg(base, P_EVNT_DEST_ADDR(pipe)),
bam_read_reg(base, P_DESC_FIFO_ADDR(pipe)),
bam_read_reg_field(base, P_FIFO_SIZES(pipe), P_DESC_FIFO_SIZE),
bam_read_reg_field(base, P_FIFO_SIZES(pipe), P_DESC_FIFO_SIZE),
bam_read_reg(base, P_DATA_FIFO_ADDR(pipe)),
bam_read_reg_field(base, P_FIFO_SIZES(pipe), P_DATA_FIFO_SIZE),
bam_read_reg_field(base, P_FIFO_SIZES(pipe), P_DATA_FIFO_SIZE),
bam_read_reg_field(base, P_EVNT_GEN_TRSHLD(pipe),
P_EVNT_GEN_TRSHLD_P_TRSHLD),
bam_read_reg_field(base, P_EVNT_GEN_TRSHLD(pipe),
P_EVNT_GEN_TRSHLD_P_TRSHLD));
}
/**
* Initialize a BAM pipe
*/
int bam_pipe_init(void *base, u32 pipe, struct bam_pipe_parameters *param,
u32 ee)
{
SPS_DBG2("sps:%s:bam=0x%x(va).pipe=%d.", __func__, (u32) base, pipe);
/* Reset the BAM pipe */
bam_write_reg(base, P_RST(pipe), 1);
/* No delay needed */
bam_write_reg(base, P_RST(pipe), 0);
/* Enable the Pipe Interrupt at the BAM level */
bam_write_reg_field(base, IRQ_SRCS_MSK_EE(ee), (1 << pipe), 1);
bam_write_reg(base, P_IRQ_EN(pipe), param->pipe_irq_mask);
bam_write_reg_field(base, P_CTRL(pipe), P_DIRECTION, param->dir);
bam_write_reg_field(base, P_CTRL(pipe), P_SYS_MODE, param->mode);
bam_write_reg(base, P_EVNT_GEN_TRSHLD(pipe), param->event_threshold);
bam_write_reg(base, P_DESC_FIFO_ADDR(pipe), param->desc_base);
bam_write_reg_field(base, P_FIFO_SIZES(pipe), P_DESC_FIFO_SIZE,
param->desc_size);
bam_write_reg_field(base, P_CTRL(pipe), P_SYS_STRM,
param->stream_mode);
#ifdef CONFIG_SPS_SUPPORT_NDP_BAM
bam_write_reg_field(base, P_CTRL(pipe), P_LOCK_GROUP,
param->lock_group);
SPS_DBG("sps:bam=0x%x(va).pipe=%d.lock_group=%d.\n",
(u32) base, pipe, param->lock_group);
#endif
if (param->mode == BAM_PIPE_MODE_BAM2BAM) {
u32 peer_dest_addr = param->peer_phys_addr +
P_EVNT_REG(param->peer_pipe);
bam_write_reg(base, P_DATA_FIFO_ADDR(pipe),
param->data_base);
bam_write_reg_field(base, P_FIFO_SIZES(pipe),
P_DATA_FIFO_SIZE, param->data_size);
bam_write_reg(base, P_EVNT_DEST_ADDR(pipe), peer_dest_addr);
SPS_DBG2("sps:bam=0x%x(va).pipe=%d.peer_bam=0x%x."
"peer_pipe=%d.\n",
(u32) base, pipe,
(u32) param->peer_phys_addr,
param->peer_pipe);
#ifdef CONFIG_SPS_SUPPORT_NDP_BAM
bam_write_reg_field(base, P_CTRL(pipe), P_WRITE_NWD,
param->write_nwd);
SPS_DBG("sps:%s WRITE_NWD bit for this bam2bam pipe.",
param->write_nwd ? "Set" : "Do not set");
#endif
}
/* Pipe Enable - at last */
bam_write_reg_field(base, P_CTRL(pipe), P_EN, 1);
return 0;
}