/**
Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space.
@param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
@param Width Signifies the width of the memory operations.
@param Address The base address of the memory operations.
@param Count The number of memory operations to perform.
@param Buffer For read operations, the destination buffer to store the results. For write
operations, the source buffer to write data from.
@retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
@retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
@retval EFI_INVALID_PARAMETER One or more parameters are invalid.
**/
EFI_STATUS
EFIAPI
PciRootBridgeIoMemWrite (
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
IN UINT64 Address,
IN UINTN Count,
IN OUT VOID *Buffer
)
{
PCI_ROOT_BRIDGE *Private;
UINTN AlignMask;
PTR In;
PTR Out;
if ( Buffer == NULL ) {
return EFI_INVALID_PARAMETER;
}
Private = INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This);
if (!PciRootBridgeMemAddressValid (Private, Address)) {
return EFI_INVALID_PARAMETER;
}
AlignMask = (1 << (Width & 0x03)) - 1;
if (Address & AlignMask) {
return EFI_INVALID_PARAMETER;
}
In.Buffer = (VOID *)(UINTN) Address;
Out.Buffer = Buffer;
switch (Width) {
case EfiPciWidthUint8:
case EfiPciWidthUint16:
case EfiPciWidthUint32:
case EfiPciWidthUint64:
return PciRootBridgeIoMemRW (Width, Count, TRUE, In, TRUE, Out);
case EfiPciWidthFifoUint8:
case EfiPciWidthFifoUint16:
case EfiPciWidthFifoUint32:
case EfiPciWidthFifoUint64:
return PciRootBridgeIoMemRW (Width, Count, FALSE, In, TRUE, Out);
case EfiPciWidthFillUint8:
case EfiPciWidthFillUint16:
case EfiPciWidthFillUint32:
case EfiPciWidthFillUint64:
return PciRootBridgeIoMemRW (Width, Count, TRUE, In, FALSE, Out);
default:
break;
}
return EFI_INVALID_PARAMETER;
}
EFI_STATUS
PciIoPciWrite (
IN EFI_PCI_IO_PROTOCOL *This,
IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
IN UINT32 Offset,
IN UINTN Count,
IN OUT VOID *Buffer
)
{
EFI_PCI_IO_PRIVATE_DATA *Private = EFI_PCI_IO_PRIVATE_DATA_FROM_THIS(This);
return PciRootBridgeIoMemRW ((EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,
Count,
TRUE,
(PTR)(UINTN)(((UINT8 *)Private->ConfigSpace) + Offset),
TRUE,
(PTR)(UINTN)Buffer
);
}
