VOID
STATIC
PcieSiliconEnablePortsV5 (
IN PCIe_SILICON_CONFIG *Silicon,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
PCIe_ENGINE_CONFIG *EngineList;
EngineList = PcieConfigGetChildEngine (Silicon);
while (EngineList != NULL) {
if (PcieConfigIsPcieEngine (EngineList)) {
if (!PcieConfigIsSbPcieEngine (EngineList) &&
(PcieConfigCheckPortStatus (EngineList, INIT_STATUS_PCIE_TRAINING_SUCCESS) ||
((EngineList->Type.Port.PortData.LinkHotplug != HotplugDisabled) &&
(EngineList->Type.Port.PortData.LinkHotplug != HotplugInboard)))) {
GnbLibPciIndirectRMW (
Silicon->Address.AddressValue | D0F0xC8_ADDRESS,
D0F0xCC_x01_ADDRESS | ((EngineList->Type.Port.PortData.DeviceNumber << 3 | EngineList->Type.Port.PortData.FunctionNumber) << D0F0xC8_NB_DEV_IND_SEL_OFFSET),
AccessS3SaveWidth32,
(UINT32)~(D0F0xCC_x01_BridgeDis_MASK | D0F0xCC_x01_CfgDis_MASK | D0F0xCC_x01_CsrEnable_MASK | D0F0xCC_x01_SetPowEn_MASK),
((1 << D0F0xCC_x01_CsrEnable_OFFSET) | (1 << D0F0xCC_x01_SetPowEn_OFFSET)),
GnbLibGetHeader (Pcie)
);
}
}
EngineList = (PCIe_ENGINE_CONFIG *) PcieConfigGetNextTopologyDescriptor (EngineList, DESCRIPTOR_TERMINATE_GNB);
}
}
VOID
STATIC
PcieSiliconControlPortsV5 (
IN PCIE_PORT_VISIBILITY Control,
IN PCIe_SILICON_CONFIG *Silicon,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
PCIe_ENGINE_CONFIG *EngineList;
UINT32 Value;
Value = (Control == HidePorts) ? ((1 << D0F0xCC_x01_BridgeDis_OFFSET) | (1 << D0F0xCC_x01_CfgDis_OFFSET)) : 0;
Value |= (1 << D0F0xCC_x01_CsrEnable_OFFSET) | (1 << D0F0xCC_x01_SetPowEn_OFFSET);
EngineList = PcieConfigGetChildEngine (Silicon);
while (EngineList != NULL) {
if (PcieConfigIsPcieEngine (EngineList)) {
GnbLibPciIndirectRMW (
Silicon->Address.AddressValue | D0F0xC8_ADDRESS,
D0F0xCC_x01_ADDRESS | ((EngineList->Type.Port.NativeDevNumber << 3 | EngineList->Type.Port.NativeFunNumber) << D0F0xC8_NB_DEV_IND_SEL_OFFSET),
AccessS3SaveWidth32,
(UINT32)~(D0F0xCC_x01_BridgeDis_MASK | D0F0xCC_x01_CfgDis_MASK | D0F0xCC_x01_CsrEnable_MASK | D0F0xCC_x01_SetPowEn_MASK),
Value,
GnbLibGetHeader (Pcie)
);
}
EngineList = (PCIe_ENGINE_CONFIG *) PcieConfigGetNextTopologyDescriptor (EngineList, DESCRIPTOR_TERMINATE_GNB);
}
}
UINT32
STATIC
PcieUtilGetPcieEngineLaneBitMap (
IN LANE_TYPE LaneType,
IN LANE_PROPERTY LaneProperty,
IN PCIe_ENGINE_CONFIG *Engine
)
{
UINT32 LaneBitmap;
UINT8 Width;
UINT16 Offset;
UINT16 LoPhylane;
UINT16 HiPhylane;
PCIe_PLATFORM_CONFIG *Pcie;
Width = 0;
Offset = 0;
LaneBitmap = 0;
Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Engine->Header);
if (PcieConfigIsPcieEngine (Engine)) {
if (LaneType == LaneTypeCore && LaneProperty == LanePropertyConfig) {
Width = PcieConfigGetNumberOfCoreLane (Engine);
Offset = Engine->Type.Port.StartCoreLane;
LaneBitmap = ((1 << Width) - 1) << Offset;
} else if (PcieConfigIsEngineAllocated (Engine)) {
if (LaneType == LaneTypeNativePhy) {
LaneBitmap = PcieUtilGetPcieEngineLaneBitMap (LaneTypePhy, LaneProperty, Engine);
LaneBitmap = PcieFmGetNativePhyLaneBitmap (LaneBitmap, Engine);
} else {
if (LaneType == LaneTypeCore) {
if (LaneProperty == LanePropertyActive) {
Width = PcieUtilGetLinkWidth (Engine, Pcie);
Offset = PcieUtilIsLinkReversed (TRUE, Engine, Pcie) ? (Engine->Type.Port.EndCoreLane - Width + 1) : Engine->Type.Port.StartCoreLane;
} else if (LaneProperty == LanePropertyAllocated) {
Width = PcieConfigGetNumberOfPhyLane (Engine);
Offset = PcieUtilIsLinkReversed (FALSE, Engine, Pcie) ? (Engine->Type.Port.EndCoreLane - Width + 1) : Engine->Type.Port.StartCoreLane;
}
}
if (LaneType == LaneTypePhy) {
LoPhylane = PcieLibGetLoPhyLane (Engine);
HiPhylane = PcieLibGetHiPhyLane (Engine);
if (LaneProperty == LanePropertyActive) {
Width = PcieUtilGetLinkWidth (Engine, Pcie);
Offset = (PcieUtilIsLinkReversed (TRUE, Engine, Pcie) ? (HiPhylane - Width + 1) : LoPhylane) - PcieConfigGetParentWrapper (Engine)->StartPhyLane;
} else if (LaneProperty == LanePropertyAllocated) {
Width = PcieConfigGetNumberOfPhyLane (Engine);
Offset = LoPhylane - PcieConfigGetParentWrapper (Engine)->StartPhyLane;
}
}
LaneBitmap = ((1 << Width) - 1) << Offset;
}
}
}
return LaneBitmap;
}
/**
* Check is engine is active or potentially active
*
*
*
* @param[in] Engine Pointer to engine descriptor
* @retval TRUE - engine active
* @retval FALSE - engine not active
*/
BOOLEAN
PcieConfigIsActivePcieEngine (
IN PCIe_ENGINE_CONFIG *Engine
)
{
BOOLEAN Result;
ASSERT (PcieConfigIsPcieEngine (Engine));
Result = FALSE;
if (PcieConfigIsEngineAllocated (Engine)) {
if (PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS) ||
(Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled && Engine->Type.Port.PortData.LinkHotplug != HotplugInboard)) {
Result = TRUE;
}
}
return Result;
}
/**
* get Master Lane of PCIe port engine
*
*
*
* @param[in] Engine Pointer to engine descriptor
* @retval Master Engine Lane Number
*/
UINT8
PcieConfigGetPcieEngineMasterLane (
IN PCIe_ENGINE_CONFIG *Engine
)
{
UINT8 MasterLane;
PCIe_WRAPPER_CONFIG *Wrapper;
ASSERT (PcieConfigIsPcieEngine (Engine));
Wrapper = PcieConfigGetParentWrapper (Engine);
if (Engine->EngineData.StartLane <= Engine->EngineData.EndLane) {
MasterLane = (UINT8) (Engine->EngineData.StartLane - Wrapper->StartPhyLane);
} else {
MasterLane = (UINT8) (Engine->EngineData.EndLane - Wrapper->StartPhyLane);
}
return MasterLane;
}
VOID
PcieSiliconHidePorts (
IN PCIe_SILICON_CONFIG *Silicon,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
D0F0x64_x0C_STRUCT D0F0x64_x0C;
PCIe_WRAPPER_CONFIG *WrapperList;
D0F0x64_x0C.Value = 0;
IDS_HDT_CONSOLE (GNB_TRACE, "PcieSiliconHidePorts Enter\n");
D0F0x64_x0C.Value = BIT2 | BIT3 | BIT4 | BIT5 | BIT6 | BIT7;
WrapperList = PcieConfigGetChildWrapper (Silicon);
while (WrapperList != NULL) {
PCIe_ENGINE_CONFIG *EngineList;
EngineList = PcieConfigGetChildEngine (WrapperList);
while (EngineList != NULL) {
if (PcieConfigIsPcieEngine (EngineList)) {
if (PcieConfigIsActivePcieEngine (EngineList) && !PcieConfigIsSbPcieEngine (EngineList)) {
D0F0x64_x0C.Value &= ~(1 << EngineList->Type.Port.Address.Address.Device);
}
}
EngineList = PcieLibGetNextDescriptor (EngineList);
}
WrapperList = PcieLibGetNextDescriptor (WrapperList);
}
GnbLibPciIndirectRMW (
Silicon->Address.AddressValue | D0F0x60_ADDRESS,
D0F0x64_x0C_ADDRESS | IOC_WRITE_ENABLE,
AccessS3SaveWidth32,
(UINT32)~(BIT2 | BIT3 | BIT4 | BIT5 | BIT6 | BIT7),
D0F0x64_x0C.Value,
GnbLibGetHeader (Pcie)
);
GnbLibPciIndirectRMW (
Silicon->Address.AddressValue | D0F0x60_ADDRESS,
D0F0x64_x00_ADDRESS | IOC_WRITE_ENABLE,
AccessS3SaveWidth32,
(UINT32)~BIT6,
0x0,
GnbLibGetHeader (Pcie)
);
IDS_HDT_CONSOLE (GNB_TRACE, "Write D0F0x64_x0C.Value = %x\n", D0F0x64_x0C.Value);
IDS_HDT_CONSOLE (GNB_TRACE, "PcieSiliconHidePorts Exit\n");
}
/**
* Get port configuration signature for given wrapper and core
*
* Support for unify register access through index/data pair on GNB
*
* @param[in] Wrapper Pointer to wrapper config descriptor
* @param[in] CoreId Core ID
* @retval Configuration Signature
*/
UINT64
PcieConfigGetConfigurationSignature (
IN PCIe_WRAPPER_CONFIG *Wrapper,
IN UINT8 CoreId
)
{
UINT64 ConfigurationSignature;
PCIe_ENGINE_CONFIG *EngineList;
ConfigurationSignature = 0;
EngineList = PcieConfigGetChildEngine (Wrapper);
while (EngineList != NULL) {
if (PcieConfigIsPcieEngine (EngineList) && EngineList->Type.Port.CoreId == CoreId) {
ConfigurationSignature = (ConfigurationSignature << 8) | PcieConfigGetNumberOfCoreLane (EngineList);
}
EngineList = PcieLibGetNextDescriptor (EngineList);
}
return ConfigurationSignature;
}
VOID
STATIC
GnbIommuMidInitCheckGfxPciePorts (
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
PCIe_WRAPPER_CONFIG *WrapperList;
BOOLEAN GfxPciePortUsed;
D0F2xF4_x57_STRUCT D0F2xF4_x57;
IDS_HDT_CONSOLE (GNB_TRACE, "GnbIommuMidInitCheckGfxPciePorts Enter\n");
GfxPciePortUsed = FALSE;
WrapperList = PcieConfigGetChildWrapper (Pcie);
ASSERT (WrapperList != NULL);
if (WrapperList->WrapId == GFX_WRAP_ID) {
PCIe_ENGINE_CONFIG *EngineList;
EngineList = PcieConfigGetChildEngine (WrapperList);
while (EngineList != NULL) {
if (PcieConfigIsPcieEngine (EngineList)) {
IDS_HDT_CONSOLE (GNB_TRACE, "Checking Gfx ports device number %x\n", EngineList->Type.Port.NativeDevNumber);
if (PcieConfigCheckPortStatus (EngineList, INIT_STATUS_PCIE_TRAINING_SUCCESS) ||
((EngineList->Type.Port.PortData.LinkHotplug != HotplugDisabled) && (EngineList->Type.Port.PortData.LinkHotplug != HotplugInboard))) {
// GFX PCIe ports beeing used
GfxPciePortUsed = TRUE;
IDS_HDT_CONSOLE (GNB_TRACE, "GFX PCIe ports beeing used\n");
break;
}
}
EngineList = PcieLibGetNextDescriptor (EngineList);
}
}
if (!GfxPciePortUsed) {
//D0F2xF4_x57.Field.L1ImuPcieGfxDis needs to be set
GnbRegisterReadTN (D0F2xF4_x57_TYPE, D0F2xF4_x57_ADDRESS, &D0F2xF4_x57.Value, 0, GnbLibGetHeader (Pcie));
D0F2xF4_x57.Field.L1ImuPcieGfxDis = 1;
GnbRegisterWriteTN (D0F2xF4_x57_TYPE, D0F2xF4_x57_ADDRESS, &D0F2xF4_x57.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Pcie));
}
IDS_HDT_CONSOLE (GNB_TRACE, "GnbIommuMidInitCheckGfxPciePorts Exit\n");
}
VOID
PcieTopologySelectMasterPll (
IN PCIe_WRAPPER_CONFIG *Wrapper,
OUT BOOLEAN *ConfigChanged,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
PCIe_ENGINE_CONFIG *EngineList;
UINT16 MasterLane;
UINT16 MasterHotplugLane;
D0F0xE4_WRAP_8013_STRUCT D0F0xE4_WRAP_8013;
D0F0xE4_WRAP_8013_STRUCT D0F0xE4_WRAP_8013_BASE;
IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologySelectMasterPll Enter\n");
MasterLane = 0xFFFF;
MasterHotplugLane = 0xFFFF;
EngineList = PcieConfigGetChildEngine (Wrapper);
while (EngineList != NULL) {
if (PcieConfigIsEngineAllocated (EngineList) && EngineList->Type.Port.PortData.PortPresent != PortDisabled && PcieConfigIsPcieEngine (EngineList)) {
if (EngineList->Type.Port.PortData.LinkHotplug != HotplugDisabled) {
MasterHotplugLane = PcieConfigGetPcieEngineMasterLane (EngineList);
} else {
MasterLane = PcieConfigGetPcieEngineMasterLane (EngineList);
if (PcieConfigIsSbPcieEngine (EngineList)) {
break;
}
}
}
EngineList = PcieLibGetNextDescriptor (EngineList);
}
if (MasterLane == 0xffff) {
if (MasterHotplugLane != 0xffff) {
MasterLane = MasterHotplugLane;
} else {
MasterLane = 0x0;
}
}
D0F0xE4_WRAP_8013.Value = PcieRegisterRead (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8013_ADDRESS),
Pcie
);
D0F0xE4_WRAP_8013_BASE.Value = D0F0xE4_WRAP_8013.Value;
if ( MasterLane <= 3 ) {
D0F0xE4_WRAP_8013.Field.MasterPciePllA = 0x1;
D0F0xE4_WRAP_8013.Field.MasterPciePllB = 0x0;
D0F0xE4_WRAP_8013.Field.MasterPciePllC = 0x0;
D0F0xE4_WRAP_8013.Field.MasterPciePllD = 0x0;
Wrapper->MasterPll = 0xA;
} else if (MasterLane <= 7) {
D0F0xE4_WRAP_8013.Field.MasterPciePllA = 0x0;
D0F0xE4_WRAP_8013.Field.MasterPciePllB = 0x1;
D0F0xE4_WRAP_8013.Field.MasterPciePllC = 0x0;
D0F0xE4_WRAP_8013.Field.MasterPciePllD = 0x0;
Wrapper->MasterPll = 0xB;
} else if (MasterLane <= 11) {
D0F0xE4_WRAP_8013.Field.MasterPciePllA = 0x0;
D0F0xE4_WRAP_8013.Field.MasterPciePllB = 0x0;
D0F0xE4_WRAP_8013.Field.MasterPciePllC = 0x1;
D0F0xE4_WRAP_8013.Field.MasterPciePllD = 0x0;
Wrapper->MasterPll = 0xC;
} else {
D0F0xE4_WRAP_8013.Field.MasterPciePllA = 0x0;
D0F0xE4_WRAP_8013.Field.MasterPciePllB = 0x0;
D0F0xE4_WRAP_8013.Field.MasterPciePllC = 0x0;
D0F0xE4_WRAP_8013.Field.MasterPciePllD = 0x1;
Wrapper->MasterPll = 0xD;
}
if (ConfigChanged != NULL) {
*ConfigChanged = (D0F0xE4_WRAP_8013.Value == D0F0xE4_WRAP_8013_BASE.Value) ? FALSE : TRUE;
}
PcieRegisterWrite (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8013_ADDRESS),
D0F0xE4_WRAP_8013.Value,
FALSE,
Pcie
);
IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologySelectMasterPll Exit\n");
}
