/**
* PHY Pll Personality Init Callback
*
*
*
* @param[in] Wrapper Pointer to wrapper config descriptor
* @param[in] Buffer Pointer to buffer
* @param[in] Pcie Pointer to global PCIe configuration
*/
AGESA_STATUS
PciePhyLetPllPersonalityInitCallbackTN (
IN PCIe_WRAPPER_CONFIG *Wrapper,
IN VOID *Buffer,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
IDS_HDT_CONSOLE (GNB_TRACE, "PciePhyLetPllPersonalityInitCallbackTN Enter\n");
PciePifPllPowerControl (PowerDownPifs, Wrapper, Pcie);
PciePifSetPllRampTime (NormalRampup, Wrapper, Pcie);
PciePollPifForCompeletion (Wrapper, Pcie);
PcieTopologyLaneControl (
DisableLanes,
PcieUtilGetWrapperLaneBitMap (LANE_TYPE_CORE_ALL, LANE_TYPE_PCIE_SB_CORE_CONFIG, Wrapper),
Wrapper,
Pcie
);
PciePollPifForCompeletion (Wrapper, Pcie);
PcieSetPhyPersonalityTN (Wrapper, Pcie);
PcieWrapSetTxS1CtrlForLaneMux (Wrapper, Pcie);
PciePollPifForCompeletion (Wrapper, Pcie);
PcieTopologyLaneControl (
EnableLanes,
PcieUtilGetWrapperLaneBitMap (LANE_TYPE_CORE_ALL, 0, Wrapper),
Wrapper,
Pcie
);
PcieWrapSetTxOffCtrlForLaneMux (Wrapper, Pcie);
PciePollPifForCompeletion (Wrapper, Pcie);
PciePifPllPowerControl (PowerUpPifs, Wrapper, Pcie);
IDS_HDT_CONSOLE (GNB_TRACE, "PciePhyLetPllPersonalityInitCallbackTN Exit\n");
return AGESA_SUCCESS;
}
/**
* Per wrapper Pcie Init prior training.
*
*
* @param[in] Wrapper Pointer to wrapper configuration descriptor
* @param[in] Buffer Pointer buffer
* @param[in] Pcie Pointer to global PCIe configuration
*/
AGESA_STATUS
PcieInitCallback (
IN PCIe_WRAPPER_CONFIG *Wrapper,
IN OUT VOID *Buffer,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
AGESA_STATUS Status;
PcieTopologyPrepareForReconfig (Wrapper, Pcie);
Status = PcieTopologySetCoreConfig (Wrapper, Pcie);
ASSERT (Status == AGESA_SUCCESS);
PcieTopologyApplyLaneMux (Wrapper, Pcie);
PcieFmPifSetRxDetectPowerMode (Wrapper, Pcie);
PciePifSetLs2ExitTime (Wrapper, Pcie);
PcieTopologySelectMasterPll (Wrapper, Pcie);
PcieTopologyExecuteReconfig (Wrapper, Pcie);
PcieTopologySetLinkReversal (Wrapper, Pcie);
PciePifApplyGanging (Wrapper, Pcie);
PcieFmPhyApplyGanging (Wrapper, Pcie);
PciePifPllInitForDdi (Wrapper, Pcie);
PcieTopologyLaneControl (
DisableLanes,
PcieUtilGetWrapperLaneBitMap (LANE_TYPE_CORE_ALL, LANE_TYPE_PCIE_CORE_ALLOC, Wrapper),
Wrapper,
Pcie
);
PcieSetDdiOwnPhy (Wrapper, Pcie);
PciePollPifForCompeletion (Wrapper, Pcie);
PcieFmAvertClockPickers (Wrapper, Pcie);
PcieCommonCoreInit (Wrapper, Pcie);
PciePifDisableFifoReset (Wrapper, Pcie);
return Status;
}
VOID
PciePwrPowerDownDdiPllsV4 (
IN PCIe_WRAPPER_CONFIG *Wrapper,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrPowerDownDdiPllsV4 Enter\n");
if (PcieConfigIsDdiWrapper (Wrapper) && !PcieConfigIsPcieWrapper (Wrapper)) {
PcieRegisterRMW (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8020_ADDRESS),
D0F0xE4_WRAP_8020_PrbsPcieLbSelect_MASK,
0x1 << D0F0xE4_WRAP_8020_PrbsPcieLbSelect_OFFSET,
FALSE,
Pcie
);
PciePollPifForCompeletion (Wrapper, Pcie);
PcieRegisterRMW (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8025_ADDRESS),
D0F0xE4_WRAP_8025_LMTxPhyCmd0_MASK | D0F0xE4_WRAP_8025_LMTxPhyCmd1_MASK,
(0x1 << D0F0xE4_WRAP_8025_LMTxPhyCmd0_OFFSET) | (0x1 << D0F0xE4_WRAP_8025_LMTxPhyCmd1_OFFSET),
FALSE,
Pcie
);
PciePollPifForCompeletion (Wrapper, Pcie);
PcieRegisterRMW (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8025_ADDRESS),
D0F0xE4_WRAP_8025_LMTxPhyCmd0_MASK | D0F0xE4_WRAP_8025_LMTxPhyCmd1_MASK,
(0x7 << D0F0xE4_WRAP_8025_LMTxPhyCmd0_OFFSET) | (0x7 << D0F0xE4_WRAP_8025_LMTxPhyCmd1_OFFSET),
FALSE,
Pcie
);
PcieRegisterRMW (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8020_ADDRESS),
D0F0xE4_WRAP_8020_PrbsPcieLbSelect_MASK,
0x0 << D0F0xE4_WRAP_8020_PrbsPcieLbSelect_OFFSET,
FALSE,
Pcie
);
}
IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrPowerDownDdiPllsV4 Exit\n");
}
/**
* Per wrapper Pcie Init prior training.
*
*
* @param[in] Wrapper Pointer to wrapper configuration descriptor
* @param[in] Buffer Pointer buffer
* @param[in] Pcie Pointer to global PCIe configuration
*/
AGESA_STATUS
STATIC
PcieEarlyInitCallbackTN (
IN PCIe_WRAPPER_CONFIG *Wrapper,
IN OUT VOID *Buffer,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
AGESA_STATUS Status;
BOOLEAN CoreConfigChanged;
BOOLEAN PllConfigChanged;
IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyInitCallbackTN Enter\n");
CoreConfigChanged = FALSE;
PllConfigChanged = FALSE;
PcieTopologyPrepareForReconfig (Wrapper, Pcie);
Status = PcieTopologySetCoreConfig (Wrapper, &CoreConfigChanged, Pcie);
ASSERT (Status == AGESA_SUCCESS);
PcieTopologyApplyLaneMux (Wrapper, Pcie);
PciePifSetRxDetectPowerMode (Wrapper, Pcie);
PciePifSetLs2ExitTime (Wrapper, Pcie);
PcieTopologySelectMasterPll (Wrapper, &PllConfigChanged, Pcie);
if (CoreConfigChanged || PllConfigChanged) {
PcieTopologyExecuteReconfigV4 (Wrapper, Pcie);
}
PcieTopologyCleanUpReconfig (Wrapper, Pcie);
PcieTopologySetLinkReversalV4 (Wrapper, Pcie);
if (Wrapper->Features.PowerOffUnusedPlls != 0) {
PciePifPllPowerDown (
PcieUtilGetWrapperLaneBitMap (LANE_TYPE_CORE_ALL, LANE_TYPE_PCIE_CORE_ALLOC | LANE_TYPE_DDI_PHY_NATIVE, Wrapper),
Wrapper,
Pcie
);
PciePifPllInitForDdi (Wrapper, Pcie);
PciePwrPowerDownDdiPllsV4 (Wrapper, Pcie);
}
PcieTopologyLaneControl (
DisableLanes,
PcieUtilGetWrapperLaneBitMap (LANE_TYPE_CORE_ALL, LANE_TYPE_PCIE_CORE_ALLOC, Wrapper),
Wrapper,
Pcie
);
PcieSetReciverTerminationTN (Wrapper, Pcie);
PcieSetDdiOwnPhyV4 (Wrapper, Pcie);
PciePollPifForCompeletion (Wrapper, Pcie);
PciePhyAvertClockPickers (Wrapper, Pcie);
PcieEarlyCoreInitTN (Wrapper, Pcie);
PcieSetSsidV4 (UserOptions.CfgGnbPcieSSID, Wrapper, Pcie);
if (PcieConfigIsPcieWrapper (Wrapper)) {
PcieSetDllCapTN (Wrapper, Pcie);
}
IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyInitCallbackTN Exit [%x]\n", Status);
return Status;
}
