VOID PcieForceCompliance ( IN PCIe_ENGINE_CONFIG *Engine, IN PCIe_PLATFORM_CONFIG *Pcie ) { if (Engine->Type.Port.PortData.LinkSpeedCapability >= PcieGen2) { GnbLibPciRMW ( Engine->Type.Port.Address.AddressValue | DxF0x88_ADDRESS, AccessWidth32, 0xffffffff, 0x1 << DxF0x88_EnterCompliance_OFFSET, GnbLibGetHeader (Pcie) ); } else if (Engine->Type.Port.PortData.LinkSpeedCapability == PcieGen1) { PciePortRegisterWriteField ( Engine, DxF0xE4_xC0_ADDRESS, DxF0xE4_xC0_StrapForceCompliance_OFFSET, DxF0xE4_xC0_StrapForceCompliance_WIDTH, 0x1, FALSE, Pcie ); } }
/** * Enable lane reversal * * * @param[in] Wrapper Pointer to wrapper config descriptor * @param[in] Pcie Pointer to global PCIe configuration */ VOID PcieTopologySetLinkReversal ( IN PCIe_WRAPPER_CONFIG *Wrapper, IN PCIe_PLATFORM_CONFIG *Pcie ) { PCIe_ENGINE_CONFIG *EngineList; IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologySetLinkReversal Enter\n"); EngineList = PcieConfigGetChildEngine (Wrapper); while (EngineList != NULL) { if (PcieLibIsEngineAllocated (EngineList)) { if (PcieLibIsPcieEngine (EngineList)) { if (EngineList->EngineData.StartLane > EngineList->EngineData.EndLane) { PciePortRegisterWriteField ( EngineList, DxF0xE4_xC1_ADDRESS, DxF0xE4_xC1_StrapReverseLanes_OFFSET, DxF0xE4_xC1_StrapReverseLanes_WIDTH, 0x1, FALSE, Pcie ); } } } EngineList = PcieLibGetNextDescriptor (EngineList); } IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologySetLinkReversal Exit\n"); }
VOID PcieCompletionTimeout ( IN PCIe_ENGINE_CONFIG *Engine, IN PCIe_PLATFORM_CONFIG *Pcie ) { GnbLibPciRMW ( Engine->Type.Port.Address.AddressValue | DxF0x80_ADDRESS, AccessWidth32, 0xffffffff, 0x6 << DxF0x80_CplTimeoutValue_OFFSET, GnbLibGetHeader (Pcie) ); if (Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled) { PciePortRegisterWriteField ( Engine, DxF0xE4_x20_ADDRESS, DxF0xE4_x20_TxFlushTlpDis_OFFSET, DxF0xE4_x20_TxFlushTlpDis_WIDTH, 0x0, TRUE, Pcie ); } }
/** * Retrain link * * * @param[in] CurrentEngine Pointer to engine config descriptor * @param[in] Pcie Pointer to global PCIe configuration * */ VOID STATIC PcieTrainingRetrainLink ( IN PCIe_ENGINE_CONFIG *CurrentEngine, IN PCIe_PLATFORM_CONFIG *Pcie ) { PciePortRegisterWriteField ( CurrentEngine, DxF0xE4_xA2_ADDRESS, DxF0xE4_xA2_LcReconfigNow_OFFSET, DxF0xE4_xA2_LcReconfigNow_WIDTH, 1, FALSE, Pcie ); PcieTrainingSetPortState (CurrentEngine, LinkStateDetecting, TRUE, Pcie); }
VOID PcieLinkInitHotplugV5 ( IN PCIe_ENGINE_CONFIG *Engine, IN PCIe_PLATFORM_CONFIG *Pcie ) { UINT32 Value; PcieLinkInitHotplug (Engine, Pcie); if (Engine->Type.Port.PortData.LinkHotplug == HotplugEnhanced) { Value = 1; } else { Value = 0; } PciePortRegisterWriteField ( Engine, DxF0xE4_x10_ADDRESS, DxF0xE4_x10_NativePmeEn_OFFSET, DxF0xE4_x10_NativePmeEn_WIDTH, Value, TRUE, Pcie ); }
VOID STATIC PcieLinkInitHotplugCZ ( IN PCIe_ENGINE_CONFIG *Engine, IN PCIe_PLATFORM_CONFIG *Pcie ) { DxFxxE4_xB5_STRUCT DxFxxE4_xB5; UINT32 Value; if ((Engine->Type.Port.PortData.LinkHotplug == HotplugEnhanced) || (Engine->Type.Port.PortData.LinkHotplug == HotplugInboard)) { DxFxxE4_xB5.Value = PciePortRegisterRead (Engine, DxFxxE4_xB5_ADDRESS, Pcie); DxFxxE4_xB5.Field.LcEhpRxPhyCmd = 0x3; DxFxxE4_xB5.Field.LcEhpTxPhyCmd = 0x3; DxFxxE4_xB5.Field.LcEnhancedHotPlugEn = 0x1; DxFxxE4_xB5.Field.LcRcvrDetEnOverride = 0; PciePortRegisterWrite ( Engine, DxFxxE4_xB5_ADDRESS, DxFxxE4_xB5.Value, TRUE, Pcie ); PcieRegisterWriteField ( PcieConfigGetParentWrapper (Engine), CORE_SPACE (Engine->Type.Port.CoreId, D0F0xE4_CORE_0010_ADDRESS), D0F0xE4_CORE_0010_LcHotPlugDelSel_OFFSET, D0F0xE4_CORE_0010_LcHotPlugDelSel_WIDTH, 0x5, TRUE, Pcie ); PcieRegisterWriteField ( PcieConfigGetParentWrapper (Engine), CORE_SPACE (Engine->Type.Port.CoreId, D0F0xE4_CORE_0118_ADDRESS), D0F0xE4_CORE_0118_RCVR_DET_CLK_ENABLE_OFFSET, D0F0xE4_CORE_0118_RCVR_DET_CLK_ENABLE_WIDTH, 0x1, TRUE, Pcie ); } if (Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled) { GnbLibPciRMW ( Engine->Type.Port.Address.AddressValue | DxFxx6C_ADDRESS, AccessS3SaveWidth32, 0xffffffff, 1 << DxFxx6C_HotplugCapable_OFFSET, GnbLibGetHeader (Pcie) ); PciePortRegisterWriteField ( Engine, DxFxxE4_x20_ADDRESS, DxFxxE4_x20_TxFlushTlpDis_OFFSET, DxFxxE4_x20_TxFlushTlpDis_WIDTH, 0x0, TRUE, Pcie ); PciePortRegisterWriteField ( Engine, DxFxxE4_x70_ADDRESS, DxFxxE4_x70_RxRcbCplTimeoutMode_OFFSET, DxFxxE4_x70_RxRcbCplTimeoutMode_WIDTH, 0x1, FALSE, Pcie ); } if (Engine->Type.Port.PortData.LinkHotplug == HotplugEnhanced) { Value = 1; } else { Value = 0; } PciePortRegisterWriteField ( Engine, DxFxxE4_x10_ADDRESS, DxFxxE4_x10_NativePmeEn_OFFSET, DxFxxE4_x10_NativePmeEn_WIDTH, Value, TRUE, Pcie ); }
VOID PcieLinkInitHotplug ( IN PCIe_ENGINE_CONFIG *Engine, IN PCIe_PLATFORM_CONFIG *Pcie ) { DxF0xE4_xB5_STRUCT DxF0xE4_xB5; if ((Engine->Type.Port.PortData.LinkHotplug == HotplugEnhanced) || (Engine->Type.Port.PortData.LinkHotplug == HotplugInboard)) { DxF0xE4_xB5.Value = PciePortRegisterRead (Engine, DxF0xE4_xB5_ADDRESS, Pcie); DxF0xE4_xB5.Field.LcEhpRxPhyCmd = 0x3; DxF0xE4_xB5.Field.LcEhpTxPhyCmd = 0x3; DxF0xE4_xB5.Field.LcEnhancedHotPlugEn = 0x1; PciePortRegisterWrite ( Engine, DxF0xE4_xB5_ADDRESS, DxF0xE4_xB5.Value, TRUE, Pcie ); PcieRegisterWriteField ( PcieConfigGetParentWrapper (Engine), CORE_SPACE (Engine->Type.Port.CoreId, D0F0xE4_CORE_0010_ADDRESS), D0F0xE4_CORE_0010_LcHotPlugDelSel_OFFSET, D0F0xE4_CORE_0010_LcHotPlugDelSel_WIDTH, 0x5, TRUE, Pcie ); PcieRegisterWriteField ( PcieConfigGetParentWrapper (Engine), WRAP_SPACE (PcieConfigGetParentWrapper (Engine)->WrapId, D0F0xE4_WRAP_8011_ADDRESS), D0F0xE4_WRAP_8011_RcvrDetClkEnable_OFFSET, D0F0xE4_WRAP_8011_RcvrDetClkEnable_WIDTH, 0x1, TRUE, Pcie ); } if (Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled) { GnbLibPciRMW ( Engine->Type.Port.Address.AddressValue | DxF0x6C_ADDRESS, AccessS3SaveWidth32, 0xffffffff, 1 << DxF0x6C_HotplugCapable_OFFSET, GnbLibGetHeader (Pcie) ); PciePortRegisterWriteField ( Engine, DxF0xE4_x20_ADDRESS, DxF0xE4_x20_TxFlushTlpDis_OFFSET, DxF0xE4_x20_TxFlushTlpDis_WIDTH, 0x0, TRUE, Pcie ); PciePortRegisterWriteField ( Engine, DxF0xE4_x70_ADDRESS, DxF0xE4_x70_RxRcbCplTimeoutMode_OFFSET, DxF0xE4_x70_RxRcbCplTimeoutMode_WIDTH, 0x1, FALSE, Pcie ); } }