void main(void)
{
WDTCTL = WDTPW + WDTHOLD; // Stop WDT
Port_Mapping();
// Setup Port Pins
P4DIR |= 0xFF; // P4.0 - P4.7 output
P4SEL |= 0xFF; // P4.0 - P4.6 Port Map functions
// Setup TB0
TB0CCR0 = 256; // PWM Period/2
TB0CCTL1 = OUTMOD_6; // CCR1 toggle/set
TB0CCR1 = 192; // CCR1 PWM duty cycle
TB0CCTL2 = OUTMOD_6; // CCR2 toggle/set
TB0CCR2 = 128; // CCR2 PWM duty cycle
TB0CCTL3 = OUTMOD_6; // CCR3 toggle/set
TB0CCR3 = 64; // CCR3 PWM duty cycle
TB0CCTL4 = OUTMOD_6; // CCR4 toggle/set
TB0CCR4 = 32; // CCR4 PWM duty cycle
TB0CTL = TBSSEL_1 + MC_3; // ACLK, up-down mode
// Setup WDT in interval mode
WDTCTL = WDT_ADLY_1000; // WDT 1s, ACLK, interval timer
SFRIE1 |= WDTIE; // Enable WDT interrupt
while(1)
{
__bis_SR_register(LPM3_bits + GIE); // Enter LPM3 w/interrupt
__no_operation(); // For debugger
Port_Mapping();
count++;
if(count==4)
count = 0;
}
}
void main(void)
{
WDTCTL = WDTPW + WDTHOLD; // Stop WDT
Port_Mapping();
// Setup Port Pins
P2DIR |= 0xFF; // P2.0 - P2.7 output
P2SEL |= 0xFF; // P2.0 - P2.6 Port Map functions
// Setup TB0
TB0CCTL0 = OUTMOD_4; // CCR1 toggle/set
TB0CCR0 = 256; // PWM Period/2
TB0CCTL1 = OUTMOD_6; // CCR1 toggle/set
TB0CCR1 = 192; // CCR1 PWM duty cycle
TB0CCTL2 = OUTMOD_6; // CCR2 toggle/set
TB0CCR2 = 128; // CCR2 PWM duty cycle
TB0CCTL3 = OUTMOD_6; // CCR3 toggle/set
TB0CCR3 = 96; // CCR3 PWM duty cycle
TB0CCTL4 = OUTMOD_6; // CCR4 toggle/set
TB0CCR4 = 64; // CCR4 PWM duty cycle
TB0CCTL5 = OUTMOD_6; // CCR5 toggle/set
TB0CCR5 = 32; // CCR5 PWM duty cycle
TB0CCTL6 = OUTMOD_6; // CCR6 toggle/set
TB0CCR6 = 16; // CCR6 PWM duty cycle
TB0CTL = TBSSEL_1 + MC_3; // ACLK, up-down mode
__bis_SR_register(LPM3_bits); // Enter LPM3
__no_operation(); // For debugger
}
int main(void)
{
WDTCTL = WDTPW + WDTHOLD; // Stop WDT
while(BAKCTL & LOCKBAK) // Unlock XT1 pins for operation
BAKCTL &= ~(LOCKBAK);
UCSCTL6 &= ~(XT1OFF); // XT1 On
UCSCTL6 |= XCAP_3; // Internal load cap
// Loop until XT1 fault flag is cleared
do
{
UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + DCOFFG);
// Clear XT2,XT1,DCO fault flags
SFRIFG1 &= ~OFIFG; // Clear fault flags
}while (SFRIFG1&OFIFG); // Test oscillator fault flag
Port_Mapping();
P2SEL |= 0x03; // Assign P2.0 to UCA0TXD and...
P2DIR |= 0x03; // P2.1 to UCA0RXD
UCA0CTL1 |= UCSWRST; // **Put state machine in reset**
UCA0CTL1 |= UCSSEL_2; // SMCLK
UCA0BR0 = 6; // 1MHz 9600 (see User's Guide)
UCA0BR1 = 0; // 1MHz 9600
UCA0MCTL = UCBRS_0 + UCBRF_13 + UCOS16; // Modln UCBRSx=0, UCBRFx=0,
// over sampling
UCA0CTL1 &= ~UCSWRST; // **Initialize USCI state machine**
UCA0IE |= UCRXIE; // Enable USCI_A0 RX interrupt
__bis_SR_register(LPM0_bits + GIE); // Enter LPM0, interrupts enabled
__no_operation(); // For debugger
}
void main(void)
{
WDTCTL = WDTPW + WDTHOLD; // Stop WDT
Port_Mapping();
P3DIR |= BIT0; // P3.0=ACLK set out to pins
P3SEL |= BIT0;
PJSEL |= BIT4+BIT5; // Port select XT1
UCSCTL6 &= ~(XT1OFF); // XT1 On
UCSCTL6 |= XCAP_3; // Internal load cap
UCSCTL3 = 0; // FLL Reference Clock = XT1
// Loop until XT2 & DCO stabilizes - In this case loop until XT1 and DCo settle
do
{
UCSCTL7 &= ~(XT1LFOFFG + XT1HFOFFG + DCOFFG);
// Clear XT1,DCO fault flags
SFRIFG1 &= ~OFIFG; // Clear fault flags
}while (SFRIFG1&OFIFG); // Test oscillator fault flag
UCSCTL6 &= ~(XT1DRIVE_3); // Xtal is now stable, reduce drive strength
UCSCTL4 |= SELA_0; // ACLK = LFTX1 (by default)
__bis_SR_register(LPM3_bits); // Enter LPM3
__no_operation(); // For debugger
}
int main(void)
{
unsigned int i;
WDTCTL = WDTPW + WDTHOLD; // Stop WDT
Port_Mapping();
P2SEL |= 0x03; // Assign P2.0 to UCB0SDA and...
P2DIR |= 0x03; // P2.1 to UCB0SCL
UCB0CTL1 |= UCSWRST; // Enable SW reset
UCB0CTL0 = UCMST + UCMODE_3 + UCSYNC; // I2C Master, synchronous mode
UCB0CTL1 = UCSSEL_2 + UCSWRST; // Use SMCLK, keep SW reset
UCB0BR0 = 12; // fSCL = SMCLK/12 = ~100kHz
UCB0BR1 = 0;
UCB0I2CSA = 0x48; // Slave Address is 048h
UCB0CTL1 &= ~UCSWRST; // Clear SW reset, resume operation
UCB0IE |= UCTXIE; // Enable TX interrupt
while (1)
{
for(i=0;i<10;i++); // Delay required between transaction
PTxData = (unsigned char *)TxData; // TX array start address
// Place breakpoint here to see each
// transmit operation.
TXByteCtr = sizeof TxData; // Load TX byte counter
UCB0CTL1 |= UCTR + UCTXSTT; // I2C TX, start condition
__bis_SR_register(LPM0_bits + GIE); // Enter LPM0, enable interrupts
__no_operation(); // Remain in LPM0 until all data
// is TX'd
while (UCB0CTL1 & UCTXSTP); // Ensure stop condition got sent
}
}
void main(void)
{
volatile unsigned int i;
WDTCTL = WDTPW+WDTHOLD; // Stop WDT
Port_Mapping(); // Port Map port3
P1DIR |= BIT0; // P1.0 output
// Setup Port Pins
P3DIR |= 0x07; // P3.0 - P3.2 output
P3SEL |= 0x07; // Port map P3.0 - P3.2
UCSCTL3 |= SELREF_2; // Set DCO FLL reference = REFO
UCSCTL4 |= SELA_2; // Set ACLK = REFO
__bis_SR_register(SCG0); // Disable the FLL control loop
UCSCTL0 = 0x0000; // Set lowest possible DCOx, MODx
UCSCTL1 = DCORSEL_5; // Select DCO range 24MHz operation
UCSCTL2 = FLLD_1 + 374; // Set DCO Multiplier for 12MHz
// (N + 1) * FLLRef = Fdco
// (374 + 1) * 32768 = 12MHz
// Set FLL Div = fDCOCLK/2
__bic_SR_register(SCG0); // Enable the FLL control loop
// Worst-case settling time for the DCO when the DCO range bits have been
// changed is n x 32 x 32 x f_MCLK / f_FLL_reference. See UCS chapter in 5xx
// UG for optimization.
// 32 x 32 x 12 MHz / 32,768 Hz = 375000 = MCLK cycles for DCO to settle
__delay_cycles(375000);
// Loop until XT1 & DCO fault flag is cleared
do
{
UCSCTL7 &= ~(XT1LFOFFG + XT1HFOFFG + DCOFFG);
// Clear XT1,DCO fault flags
SFRIFG1 &= ~OFIFG; // Clear fault flags
}while (SFRIFG1&OFIFG); // Test oscillator fault flag
while(1)
{
P1OUT ^= BIT0; // Toggle P1.0
__delay_cycles(600000); // Delay
}
}
void main(void)
{
WDTCTL = WDTPW + WDTHOLD; // Stop WDT
Port_Mapping();
P2SEL |= 0x03; // Assign P2.0 to UCB0SDA and...
P2DIR |= 0x03; // P2.1 to UCB0SCL
UCB0CTL1 |= UCSWRST; // Enable SW reset
UCB0CTL0 = UCMODE_3 + UCSYNC; // I2C Slave, synchronous mode
UCB0I2COA = 0x48; // Own Address is 048h
UCB0CTL1 &= ~UCSWRST; // Clear SW reset, resume operation
UCB0IE |= UCRXIE; // Enable RX interrupt
while (1)
{
__bis_SR_register(LPM0_bits + GIE); // Enter LPM0, enable interrupts
__no_operation(); // Set breakpoint >>here<< and read
} // RXData
}
void main(void)
{
volatile unsigned int i;
WDTCTL = WDTPW+WDTHOLD; // Stop WDT
Port_Mapping(); // Port Map port3
P1DIR |= BIT0; // P1.0 output
// Setup Port Pins
P3DIR |= 0x07; // P3.0 - P3.2 output
P3SEL |= 0x07; // Port map P3.0 - P3.2
while(1)
{
P1OUT ^= BIT0; // Toggle P1.0
__delay_cycles(60000); // Delay
}
}
//----------------------------------------------------------------------------
VOID Init_StartUp(VOID)
{
WDTCTL = WDTPW + WDTHOLD; // Stop watchdog timer
__disable_interrupt(); // Disable global interrupts
Init_Ports(); // Init ports (do first ports because clocks do change ports)
SetVCore(3); // USB core requires the VCore set to 1.8 volt, independ of CPU clock frequency
Init_Clock();
__enable_interrupt(); // enable global interrupts
Port_Mapping();
#ifdef UART0_INTFNUM
InitUart0(9600);
#endif
#ifdef UART1_INTFNUM
InitUart1(9600);
#endif
}
void main(void)
{
WDTCTL = WDTPW + WDTHOLD; // Stop WDT
Port_Mapping();
// Setup Port Pins
P4DIR |= 0xFF; // P4.0 - P4.7 output
P4SEL |= 0xFF; // P4.0 - P4.6 Port Map functions
// Setup TB0
TB0CCR0 = 128; // PWM Period/2
TB0CCTL1 = OUTMOD_6; // CCR1 toggle/set
TB0CCR1 = 96; // CCR1 PWM duty cycle
TB0CCTL2 = OUTMOD_6; // CCR2 toggle/set
TB0CCR2 = 64; // CCR2 PWM duty cycle
TB0CCTL3 = OUTMOD_6; // CCR1 toggle/set
TB0CCR3 = 32; // CCR1 PWM duty cycle
TB0CTL = TBSSEL_1 + MC_3; // ACLK/2, up-down mode
__bis_SR_register(LPM3_bits); // Enter LPM3
__no_operation(); // For debugger
}
void main(void)
{
WDTCTL = WDTPW+WDTHOLD; // Stop watchdog timer
Port_Mapping();
P2SEL |= BIT0+BIT1+BIT2; // Assign P2.0 to UCB0CLK and...
P2DIR |= BIT0+BIT1+BIT2; // P2.1 UCB0SOMI P2.2 UCB0SIMO
P1REN |= BIT4; // Enable P1.4 internal resistance
P1OUT |= BIT4; // Set P1.4 as pull-Up resistance
P1IES &= ~BIT4; // P1.4 Lo/Hi edge
P1IFG &= ~BIT4; // P1.4 IFG cleared
P1IE |= BIT4; // P1.4 interrupt enabled
UCA0CTL1 |= UCSWRST; // **Put state machine in reset**
UCA0CTL0 |= UCSYNC+UCCKPL+UCMSB; // 3-pin, 8-bit SPI slave,
// Clock polarity high, MSB
UCA0CTL1 &= ~UCSWRST; // **Initialize USCI state machine**
// Interrupts enabled in Port ISR
__bis_SR_register(LPM0_bits + GIE); // Enter LPM0, enable interrupts
}
void main(void)
{
WDTCTL = WDTPW + WDTHOLD; // Stop WDT
// Configure XT1
PJSEL |= BIT4+BIT5; // Port select XT1
UCSCTL6 &= ~(XT1OFF); // XT1 On
UCSCTL6 |= XCAP_3; // Internal load cap
// Loop until XT1 fault flag is cleared
do
{
UCSCTL7 &= ~XT1LFOFFG; // Clear XT1 fault flags
}while (UCSCTL7&XT1LFOFFG); // Test XT1 fault flag
// Increase Vcore setting to level1 to support fsystem=12MHz
// NOTE: Change core voltage one level at a time..
SetVcoreUp (0x01);
// Initialize DCO to 12MHz
__bis_SR_register(SCG0); // Disable the FLL control loop
UCSCTL0 = 0x0000; // Set lowest possible DCOx, MODx
UCSCTL1 = DCORSEL_5; // Select DCO range 24MHz operation
UCSCTL2 = FLLD_1 + 374; // Set DCO Multiplier for 12MHz
// (N + 1) * FLLRef = Fdco
// (374 + 1) * 32768 = 12MHz
// Set FLL Div = fDCOCLK/2
__bic_SR_register(SCG0); // Enable the FLL control loop
// Worst-case settling time for the DCO when the DCO range bits have been
// changed is n x 32 x 32 x f_MCLK / f_FLL_reference. See UCS chapter in 5xx
// UG for optimization.
// 32 x 32 x 12 MHz / 32,768 Hz = 375000 = MCLK cycles for DCO to settle
__delay_cycles(375000);
// Loop until XT1 & DCO fault flag is cleared
do
{
UCSCTL7 &= ~(XT1LFOFFG + XT1HFOFFG + DCOFFG);
// Clear XT1,DCO fault flags
SFRIFG1 &= ~OFIFG; // Clear fault flags
}while (SFRIFG1&OFIFG); // Test oscillator fault flag
// Setup Port Pins
P3DIR |= 0x07; // P3.0 - P3.2 output
P3SEL |= 0x07; // Port map P3.0 - P3.2
Port_Mapping();
// Configure ports TD0.0 input and TA0.0 output
P1DIR &= ~BIT6; // TD0.0 input
P1SEL |= BIT6; // TD0.0 option select
P3DIR |= BIT7; // TA0.0 output
P3SEL |= BIT7; // TA0.0 option select
// Configure LED on P1.0, output and driving low
P1DIR |= BIT0;
P1OUT &= ~BIT0;
// Configure TA0.0 compare output, 1kHz freq, 50% dutycycle
TA0CCR0 = 32; // Period = 2*164*/32khz = 2ms
TA0CCTL0 |= OUTMOD_4; // TD01CCR0, Toggle
TA0CTL = TASSEL_1 + MC_1 + TACLR; // ACLK, upmode, clear TDR
// Configure TD0.0 input capture, dual capture mode
TD0CTL2 |= TDCAPM0; // Channel 0; dual capture mode
TD0CCTL0 |= CAP + CM_1 + CCIE + SCS; // TD0CCR0 Capture mode; Rising Edge;
// CCI0A; interrupt enable
TD0CTL0 = TDSSEL_2 + MC_2 + TDCLR; // SMCLK=12Mhz, Cont Mode; Start timer
while(1)
{
__bis_SR_register(LPM0_bits + GIE); // Enter LPM0
__no_operation(); // For debugger
// On exiting LPM0
if (TD0CCTL0 & COV) // Capture Overflow?
while(1); // Loop Forever
Period = REdge2-REdge1; // Measured Period
__no_operation(); // BREAKPOINT HERE - measured period ~ 2ms
// Period ~ 2m*TD0 clock counts
}
}
