CPUCapabilities::CPUCapabilities() { #ifdef __INTEL__ setIntelCapabilities(); #endif PrintCapabilities(); }
CPUCapabilities::CPUCapabilities() : fCapabilities(0) { #if defined(__INTEL__) || defined(__x86_64__) _SetIntelCapabilities(); #endif PrintCapabilities(); }
UINT32 SVGA_CheckCapabilities(VgaGfxBase *VgaGfxBase) { UINT32 id; /* Needed to read/write registers */ PCISetMemEnable(&VgaGfxBase->pciAddr, TRUE); VgaGfxBase->indexPort = PCIGetBARAddr(&VgaGfxBase->pciAddr, 0) + SVGA_INDEX_PORT; VgaGfxBase->valuePort = PCIGetBARAddr(&VgaGfxBase->pciAddr, 0) + SVGA_VALUE_PORT; // DPrintF("index port: %x, value port: %x\n", VgaGfxBase->indexPort, VgaGfxBase->valuePort); /* This should be SVGA II according to the PCI device_id, * but just in case... */ WriteReg(VgaGfxBase, SVGA_REG_ID, SVGA_ID_2); if ((id = ReadReg(VgaGfxBase, SVGA_REG_ID)) != SVGA_ID_2) { DPrintF("SVGA_REG_ID is %ld, not %d\n", id, SVGA_REG_ID); return FALSE; } // DPrintF("SVGA_REG_ID OK\n"); /* Grab some info */ VgaGfxBase->maxWidth = ReadReg(VgaGfxBase, SVGA_REG_MAX_WIDTH); VgaGfxBase->maxHeight = ReadReg(VgaGfxBase, SVGA_REG_MAX_HEIGHT); //DPrintF("max resolution: %d x %d\n", VgaGfxBase->maxWidth, VgaGfxBase->maxHeight); VgaGfxBase->fbDma = (void *)ReadReg(VgaGfxBase, SVGA_REG_FB_START); VgaGfxBase->fb = (void *)ReadReg(VgaGfxBase, SVGA_REG_FB_START); VgaGfxBase->fbSize = ReadReg(VgaGfxBase, SVGA_REG_VRAM_SIZE); //DPrintF("frame buffer: %p, size %x\n", VgaGfxBase->fbDma, VgaGfxBase->fbSize); VgaGfxBase->fifoDma = (void *)ReadReg(VgaGfxBase, SVGA_REG_MEM_START); VgaGfxBase->fifo = (void *)ReadReg(VgaGfxBase, SVGA_REG_MEM_START); VgaGfxBase->fifoSize = ReadReg(VgaGfxBase, SVGA_REG_MEM_SIZE) & ~3; //DPrintF("fifo: %x, size %x\n", VgaGfxBase->fifoDma, VgaGfxBase->fifoSize); VgaGfxBase->capabilities = ReadReg(VgaGfxBase, SVGA_REG_CAPABILITIES); #if PRINTCAP PrintCapabilities(VgaGfxBase, VgaGfxBase->capabilities); #endif //DPrintF("HOSTBPP %d\n", ReadReg(VgaGfxBase, SVGA_REG_HOST_BITS_PER_PIXEL )); VgaGfxBase->fifoMin = (VgaGfxBase->capabilities & SVGA_CAP_EXTENDED_FIFO) ? ReadReg(VgaGfxBase, SVGA_REG_MEM_REGS) : 4; return TRUE; }
static status_t CheckCapabilities() { SharedInfo *si = gPd->si; uint32 id; /* Needed to read/write registers */ si->indexPort = gPd->pcii.u.h0.base_registers[0] + SVGA_INDEX_PORT; si->valuePort = gPd->pcii.u.h0.base_registers[0] + SVGA_VALUE_PORT; TRACE("index port: %d, value port: %d\n", si->indexPort, si->valuePort); /* This should be SVGA II according to the PCI device_id, * but just in case... */ WriteReg(SVGA_REG_ID, SVGA_ID_2); if ((id = ReadReg(SVGA_REG_ID)) != SVGA_ID_2) { TRACE("SVGA_REG_ID is %ld, not %d\n", id, SVGA_REG_ID); return B_ERROR; } TRACE("SVGA_REG_ID OK\n"); /* Grab some info */ si->maxWidth = ReadReg(SVGA_REG_MAX_WIDTH); si->maxHeight = ReadReg(SVGA_REG_MAX_HEIGHT); TRACE("max resolution: %ldx%ld\n", si->maxWidth, si->maxHeight); si->fbDma = (void *)ReadReg(SVGA_REG_FB_START); si->fbSize = ReadReg(SVGA_REG_VRAM_SIZE); TRACE("frame buffer: %p, size %ld\n", si->fbDma, si->fbSize); si->fifoDma = (void *)ReadReg(SVGA_REG_MEM_START); si->fifoSize = ReadReg(SVGA_REG_MEM_SIZE) & ~3; TRACE("fifo: %p, size %ld\n", si->fifoDma, si->fifoSize); si->capabilities = ReadReg(SVGA_REG_CAPABILITIES); PrintCapabilities(si->capabilities); si->fifoMin = (si->capabilities & SVGA_CAP_EXTENDED_FIFO) ? ReadReg(SVGA_REG_MEM_REGS) : 4; return B_OK; }