void gpio_init_pin(gpio_pin_t *pin)
{
// module should ignore null pins
if (pin == NULL)
return;
// all gpio pins on the stm32f373 are connected to AHB2 so this will be ok
///@todo should we check if it is enabled before re-enabling ?
RCC_AHBPeriphClockCmd(pin_to_rcc_periph(pin), ENABLE);
RCC_AHBPeriphResetCmd(pin_to_rcc_periph(pin), DISABLE);
// setup the pin configurations
if (pin->cfg.GPIO_Mode == GPIO_Mode_AF)
GPIO_PinAFConfig(pin->port, gpio_pin_to_pin_source(pin), pin->af);
GPIO_Init(pin->port, &pin->cfg);
}
/**
* @brief Deinitializes the GPIOx peripheral registers to their default reset
* values.
��ʼ��GPIOx�Ĵ�����ȱʡֵ,ͨ������RCC_AHBRSTR
* By default, The GPIO pins are configured in input floating mode
* (except JTAG pins).
ȱʡ�£�GPIO ���ó���������ģʽ������JTAG)
* @param GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral.
���� GPIOx:x����Ϊ(A, B, C, D, E or H)
* @retval None
û�з���ֵ
*/
void GPIO_DeInit(GPIO_TypeDef* GPIOx)
{
/* Check the parameters */
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
/*������Ժ����ڼ�麯������,�������������assert_failed����main.c)���û����ã���������Դ�ļ�����������ȷ������*/
/*IS_GPIO_ALL_PERIPH()���ڼ������Ƿ�ϸ���1����0*/
if(GPIOx == GPIOA)
{
RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOA, ENABLE);
RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOA, DISABLE);
/*����GPIOx,ͨ������RCC_AHBRSTR*/
}
else if(GPIOx == GPIOB)
{
RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOB, ENABLE);
RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOB, DISABLE);
}
else if(GPIOx == GPIOC)
{
RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOC, ENABLE);
RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOC, DISABLE);
}
else if(GPIOx == GPIOD)
{
RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOD, ENABLE);
RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOD, DISABLE);
}
else if(GPIOx == GPIOE)
{
RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOE, ENABLE);
RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOE, DISABLE);
}
else
{
if(GPIOx == GPIOH)
{
RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOH, ENABLE);
RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOH, DISABLE);
}
}
}
error_t stm32f107EthInit(NetInterface *interface)
{
error_t error;
//Debug message
TRACE_INFO("Initializing STM32F107 Ethernet MAC...\r\n");
//Save underlying network interface
nicDriverInterface = interface;
//GPIO configuration
stm32f107EthInitGpio(interface);
//Enable Ethernet MAC clock
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_ETH_MAC |
RCC_AHBPeriph_ETH_MAC_Tx | RCC_AHBPeriph_ETH_MAC_Rx, ENABLE);
//Reset Ethernet MAC peripheral
RCC_AHBPeriphResetCmd(RCC_AHBPeriph_ETH_MAC, ENABLE);
RCC_AHBPeriphResetCmd(RCC_AHBPeriph_ETH_MAC, DISABLE);
//Perform a software reset
ETH->DMABMR |= ETH_DMABMR_SR;
//Wait for the reset to complete
while(ETH->DMABMR & ETH_DMABMR_SR);
//Adjust MDC clock range depending on HCLK frequency
ETH->MACMIIAR = ETH_MACMIIAR_CR_Div42;
//PHY transceiver initialization
error = interface->phyDriver->init(interface);
//Failed to initialize PHY transceiver?
if(error) return error;
//Use default MAC configuration
ETH->MACCR = ETH_MACCR_ROD;
//Set the MAC address
ETH->MACA0LR = interface->macAddr.w[0] | (interface->macAddr.w[1] << 16);
ETH->MACA0HR = interface->macAddr.w[2];
//Initialize hash table
ETH->MACHTLR = 0;
ETH->MACHTHR = 0;
//Configure the receive filter
ETH->MACFFR = ETH_MACFFR_HPF | ETH_MACFFR_HM;
//Disable flow control
ETH->MACFCR = 0;
//Enable store and forward mode
ETH->DMAOMR = ETH_DMAOMR_RSF | ETH_DMAOMR_TSF;
//Configure DMA bus mode
ETH->DMABMR = ETH_DMABMR_AAB | ETH_DMABMR_USP | ETH_DMABMR_RDP_1Beat |
ETH_DMABMR_RTPR_1_1 | ETH_DMABMR_PBL_1Beat;
//Initialize DMA descriptor lists
stm32f107EthInitDmaDesc(interface);
//Prevent interrupts from being generated when the transmit statistic
//counters reach half their maximum value
ETH->MMCTIMR = ETH_MMCTIMR_TGFM | ETH_MMCTIMR_TGFMSCM | ETH_MMCTIMR_TGFSCM;
//Prevent interrupts from being generated when the receive statistic
//counters reach half their maximum value
ETH->MMCRIMR = ETH_MMCRIMR_RGUFM | ETH_MMCRIMR_RFAEM | ETH_MMCRIMR_RFCEM;
//Disable MAC interrupts
ETH->MACIMR = ETH_MACIMR_TSTIM | ETH_MACIMR_PMTIM;
//Enable the desired DMA interrupts
ETH->DMAIER = ETH_DMAIER_NISE | ETH_DMAIER_RIE | ETH_DMAIER_TIE;
//Set priority grouping (4 bits for pre-emption priority, no bits for subpriority)
NVIC_SetPriorityGrouping(STM32F107_ETH_IRQ_PRIORITY_GROUPING);
//Configure Ethernet interrupt priority
NVIC_SetPriority(ETH_IRQn, NVIC_EncodePriority(STM32F107_ETH_IRQ_PRIORITY_GROUPING,
STM32F107_ETH_IRQ_GROUP_PRIORITY, STM32F107_ETH_IRQ_SUB_PRIORITY));
//Enable MAC transmission and reception
ETH->MACCR |= ETH_MACCR_TE | ETH_MACCR_RE;
//Enable DMA transmission and reception
ETH->DMAOMR |= ETH_DMAOMR_ST | ETH_DMAOMR_SR;
//Accept any packets from the upper layer
osSetEvent(&interface->nicTxEvent);
//Successful initialization
return NO_ERROR;
}
