Exemple #1
0
static void rdma_config(u32 width, u32 height, u32 pixel_clk)
{
	u32 threshold;
	u32 reg;

	/* Config width */
	clrsetbits_le32(&disp_rdma[0]->size_con_0, 0x1FFF, width);

	/* Config height */
	clrsetbits_le32(&disp_rdma[0]->size_con_1, 0xFFFFF, height);

	/*
	 * Enable FIFO underflow since DSI and DPI can't be blocked. Keep the
	 * FIFO pseudo size reset default of 8 KiB. Set the output threshold to
	 * 6 microseconds with 7/6 overhead to account for blanking, and with a
	 * pixel depth of 4 bytes:
	 */

	threshold = pixel_clk * 4 * 7 / 1000;

	reg = RDMA_FIFO_UNDERFLOW_EN |
	      RDMA_FIFO_PSEUDO_SIZE(8 * KiB) |
	      RDMA_OUTPUT_VALID_FIFO_THRESHOLD(threshold);

	write32(&disp_rdma[0]->fifo_con, reg);
}
Exemple #2
0
static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width,
			    unsigned int height, unsigned int vrefresh)
{
	unsigned int threshold;
	unsigned int reg;

	rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_0, 0xfff, width);
	rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_1, 0xfffff, height);

	/*
	 * Enable FIFO underflow since DSI and DPI can't be blocked.
	 * Keep the FIFO pseudo size reset default of 8 KiB. Set the
	 * output threshold to 6 microseconds with 7/6 overhead to
	 * account for blanking, and with a pixel depth of 4 bytes:
	 */
	threshold = width * height * vrefresh * 4 * 7 / 1000000;
	reg = RDMA_FIFO_UNDERFLOW_EN |
	      RDMA_FIFO_PSEUDO_SIZE(SZ_8K) |
	      RDMA_OUTPUT_VALID_FIFO_THRESHOLD(threshold);
	writel(reg, comp->regs + DISP_REG_RDMA_FIFO_CON);
}