static void dma_update_DRQ(int dma_idx, int chan_idx)
{
switch (DMA_TRANSFER_MODE(dma[dma_idx].chans[chan_idx].mode)) {
case DEMAND:
dma_poll_DRQ(dma_idx, chan_idx);
break;
case SINGLE:
dma[dma_idx].status &= ~(1 << (chan_idx + 4));
break;
case BLOCK:
if (REACHED_TC(dma_idx, chan_idx))
dma_poll_DRQ(dma_idx, chan_idx);
break;
case CASCADE:
dma_poll_DRQ(dma_idx, chan_idx);
break;
}
}
static void dma_update_DRQ(int dma_idx, int chan_idx)
{
switch (dma[dma_idx].chans[chan_idx].mode & 0x30) {
case 0x00: // demand
dma_poll_DRQ(dma_idx, chan_idx);
break;
case 0x10: // single
dma[dma_idx].status &= ~(1 << (chan_idx + 4));
break;
case 0x20: // block
if (REACHED_TC(dma_idx, chan_idx))
dma_poll_DRQ(dma_idx, chan_idx);
break;
case 0x30: // cascade
dma_poll_DRQ(dma_idx, chan_idx);
break;
}
}
static void dma_run_channel(int dma_idx, int chan_idx)
{
int done = 0;
long ticks = 0;
while (!done &&
(HAVE_DRQ(dma_idx, chan_idx) || SW_ACTIVE(dma_idx, chan_idx))) {
if (!MASKED(dma_idx, chan_idx) &&
!REACHED_TC(dma_idx, chan_idx) &&
!(dma[dma_idx].command & 4) &&
(DMA_TRANSFER_MODE(dma[dma_idx].chans[chan_idx].mode) != CASCADE)) {
dma_process_channel(dma_idx, chan_idx);
ticks++;
} else {
done = 1;
}
dma_update_DRQ(dma_idx, chan_idx);
}
if (ticks > 1)
q_printf("DMA: processed %lu (left %u) cycles on controller %i channel %i\n",
ticks, dma[dma_idx].chans[chan_idx].cur_count.value, dma_idx,
chan_idx);
}