void hdmirx_set_hpd(int port, unsigned char val)
{
#ifdef USE_GPIO_FOR_HPD
    int bitpos = 1;
    switch(port){
        case 0:
            bitpos=1;
            break;
        case 1:
            bitpos=5;
            break;
        case 2:
            bitpos=9;
            break;
        case 3:
            bitpos=13;
            break;
    }
    if(val){
        WRITE_CBUS_REG(PREG_PAD_GPIO5_O, READ_CBUS_REG(PREG_PAD_GPIO5_O) & (~(1<<bitpos)));
    }
    else{
        WRITE_CBUS_REG(PREG_PAD_GPIO5_O, READ_CBUS_REG(PREG_PAD_GPIO5_O) | (1<<bitpos));
    }
#else
    if(val){
        hdmirx_wr_top( HDMIRX_TOP_HPD_PWR5V,  hdmirx_rd_top(HDMIRX_TOP_HPD_PWR5V)|(1<<rx.port));
    }
    else{
        hdmirx_wr_top( HDMIRX_TOP_HPD_PWR5V,  hdmirx_rd_top(HDMIRX_TOP_HPD_PWR5V)&(~(1<<rx.port)));
    }
#endif
    hdmirx_print("%s(%d,%d)\n", __func__, port, val);
    
}
// -----------------------------------------
// clk_util_clk_msr
// -----------------------------------------
// from twister_core.v
//
// .clk0           ( am_ring_osc_clk_out[0]    ),
// .clk1           ( am_ring_osc_clk_out[1]    ),
// .clk2           ( ext_clk_to_msr_i          ),
// .clk3           ( cts_a9_clk                ),
// .clk4           ( cts_a9_periph_clk         ),
// .clk5           ( cts_a9_axi_clk            ),
// .clk6           ( cts_a9_at_clk             ),
// .clk7           ( cts_a9_apb_clk            ),
// .clk8           ( cts_arc625_clk            ),
// .clk9           ( sys_pll_div3              ),
// .clk10          ( ddr_pll_clk               ),
// .clk11          ( other_pll_clk             ),
// .clk12          ( aud_pll_clk               ),
// .clk13          ( demod_pll_clk240          ),
// .clk14          ( demod_pll_adc_clk         ),
// .clk15          ( demod_pll_wifi_adc_clk    ),
// .clk16          ( demod_pll_adc_clk_57      ),
// .clk17          ( demod_pll_clk400          ),
// .clk18          ( demod_pll_wifi_dac_clk    ),
// .clk19          ( vid_pll_clk               ),
// .clk20          ( vid_pll_ref_clk           ),
// .clk21          ( HDMI_CH0_TMDSCLK          ),
//
// For Example
//
// unsigend long    clk81_clk   = clk_util_clk_msr( 2,      // mux select 2
//                                                  50 );   // measure for 50uS
//
// returns a value in "clk81_clk" in Hz
//
// The "uS_gate_time" can be anything between 1uS and 65535 uS, but the limitation is
// the circuit will only count 65536 clocks.  Therefore the uS_gate_time is limited by
//
//   uS_gate_time <= 65535/(expect clock frequency in MHz)
//
// For example, if the expected frequency is 400Mhz, then the uS_gate_time should
// be less than 163.
//
// Your measurement resolution is:
//
//    100% / (uS_gate_time * measure_val )
//
//
unsigned int clk_util_clk_msr_rl(unsigned int clk_mux)
{
    unsigned int regval = 0;
    WRITE_CBUS_REG(MSR_CLK_REG0, 0);
    // Set the measurement gate to 64uS
    CLEAR_CBUS_REG_MASK(MSR_CLK_REG0, 0xffff);
    SET_CBUS_REG_MASK(MSR_CLK_REG0, (64 - 1)); //64uS is enough for measure the frequence?
    // Disable continuous measurement
    // disable interrupts
    CLEAR_CBUS_REG_MASK(MSR_CLK_REG0, ((1 << 18) | (1 << 17)));
    CLEAR_CBUS_REG_MASK(MSR_CLK_REG0, (0x1f << 20));
    SET_CBUS_REG_MASK(MSR_CLK_REG0, (clk_mux << 20) | // Select MUX
                                    (1 << 19) |       // enable the clock
									(1 << 16));       //enable measuring
    // Wait for the measurement to be done
    regval = READ_CBUS_REG(MSR_CLK_REG0);
    do {
        regval = READ_CBUS_REG(MSR_CLK_REG0);
    } while (regval & (1 << 31));

    // disable measuring
    CLEAR_CBUS_REG_MASK(MSR_CLK_REG0, (1 << 16));
    regval = (READ_CBUS_REG(MSR_CLK_REG2) + 31) & 0x000FFFFF;
    // Return value in MHz*measured_val
    return (regval >> 6);
}
int lowlevel_init(void)
{
	  unsigned por_cfg = READ_CBUS_REG(ASSIST_POR_CONFIG);
	if (((por_cfg & POR_ROM_BOOT_ENABLE) == 0)) {
		// take me as a spi rom boot mode
		romboot_info->por_cfg = POR_ROM_BOOT_ENABLE | POR_INTL_SPI;
		romboot_info->boot_id = 0;
	}

	WRITE_CBUS_REG(PAD_PULL_UP_REG0,-1);
	WRITE_CBUS_REG(PAD_PULL_UP_REG1,-1);
	WRITE_CBUS_REG(PAD_PULL_UP_REG2,-1);
	WRITE_CBUS_REG(PAD_PULL_UP_REG3,-1);

	//changed by Elvis, add uart rx pull up
	//pull up LINUX_RX(B15--->GPIOE_19) reg (7422y v1.pdf)
	//GPIOE_19(M1-Apps v25- 2010-07-19-BGA372_297-6.xls serach B15)
	WRITE_CBUS_REG( PAD_PULL_UP_REG3, READ_CBUS_REG(PAD_PULL_UP_REG3) & ~(1<<2) );	// Meson-pull-up-down_table.xlsx ( GPIOE_19 is PAD_PULL_UP_REG3---0x203e 2bits)
	
	//Adjust 1us timer base
	WRITE_CBUS_REG_BITS(PREG_CTLREG0_ADDR,CONFIG_CRYSTAL_MHZ,4,5);
	pll_initial(); //running under default freq now . Before we fixed the PLL stable problem

	unsigned clk;
	if ((readl(P_HHI_MPEG_CLK_CNTL) & (1 << 8)) == 0) {
		clk = CONFIG_CRYSTAL_MHZ * 1000000;
	} else {
		clk = romboot_info->clk81;
	}
	unsigned memory_size;
	
	memory_size = PHYS_MEMORY_SIZE;
	serial_init_with_clk(clk);
	writel((1<<22)|1000000,P_WATCHDOG_TC);
	do {
		unsigned ret1, ret2, ret3, ret4;
		ret1 = ret2 = ret3 = ret4 = 0;
		por_cfg = 0;
		ret1 = initial_ddr(&__hw_setting.ddr, __hw_setting.ddr.lane);
		display_error(ret1, "DDr Init");

#ifdef CONFIG_MEM_TEST
		ret2=memTestDevice((volatile datum *)PHYS_MEMORY_START,memory_size);
		display_error(ret2,"TestDevice");
		por_cfg=ret2;
#endif
		ret3 = memTestDataBus((volatile datum *) PHYS_MEMORY_START);
		display_error(ret3, "TestDataBus");
		ret4 = memTestAddressBus((volatile datum *) PHYS_MEMORY_START,
				memory_size);

		display_error(ret4, "TestAddressBus");

		por_cfg = ret1 | ret2 | ret3 | ret4;

	} while (por_cfg != 0);
	writel(0,P_WATCHDOG_RESET);
	return 0;

}
Exemple #4
0
static int powerkey_init(void)
{
    if(board_ver == 0){
        WRITE_CBUS_REG(0x21d0/*RTC_ADDR0*/, (READ_CBUS_REG(0x21d0/*RTC_ADDR0*/) &~(1<<11)));
        WRITE_CBUS_REG(0x21d1/*RTC_ADDR0*/, (READ_CBUS_REG(0x21d1/*RTC_ADDR0*/) &~(1<<3)));
    }  
    return 1;
}
void power_on_backlight(void)
{
    //BL_PWM -> GPIOA_7: 1
    msleep(200);
    set_gpio_val(GPIOA_bank_bit(7), GPIOA_bit_bit0_14(7), 1);
    set_gpio_mode(GPIOA_bank_bit(7), GPIOA_bit_bit0_14(7), GPIO_OUTPUT_MODE); 
    //BL_adj -> VGHL_CS0: VGHL_PWM_REG0[3:0]=0x0
    //Idim=(375*(VGHL_PWM_REG0[3:0])/15)uA; BL_max_level:VGHL_PWM_REG0[3:0]=0x0 / BL_min_level:VGHL_PWM_REG0[3:0]=0xf    
    WRITE_CBUS_REG(VGHL_PWM_REG0, (READ_CBUS_REG(VGHL_PWM_REG0) &~(0xf<<0)));
    WRITE_CBUS_REG(VGHL_PWM_REG0, (READ_CBUS_REG(VGHL_PWM_REG0) | (0<<0)));
}
void lowlevel_init(void* cur,void * target)
{
#if 0    
	if(cur != target) //r0!=r1
	{
	    //running from spi
    	// take me as a spi rom boot mode
		romboot_info->por_cfg = POR_INTL_SPI |
		    (READ_CBUS_REG(ASSIST_POR_CONFIG)&(~POR_INTL_CFG_MASK));
		romboot_info->boot_id = 0;//boot from spi
		/// Release pull up registers .
	}
#endif	

	power_hold();
	backlight_off();

	//changed by Elvis, add uart rx pull up
	//pull up LINUX_RX(B15--->GPIOE_19) reg (7422y v1.pdf)
	//GPIOE_19(M1-Apps v25- 2010-07-19-BGA372_297-6.xls serach B15)
	WRITE_CBUS_REG( PAD_PULL_UP_REG3, READ_CBUS_REG(PAD_PULL_UP_REG3) & ~(1<<2) );	// Meson-pull-up-down_table.xlsx ( GPIOE_19 is PAD_PULL_UP_REG3---0x203e 2bits)

	//Adjust 1us timer base
	WRITE_CBUS_REG_BITS(PREG_CTLREG0_ADDR,CONFIG_CRYSTAL_MHZ,4,5);
	/*
        Select TimerE 1 us base
    	*/
	clrsetbits_le32(P_ISA_TIMER_MUX,0x7<<8,0x1<<8);
    	memory_pll_init(0,NULL);
	serial_puts("\nFirmware start at: ");
	serial_put_dword(get_timer(0));
#if CONFIG_ENABLE_SPL_DEBUG_ROM
    __udelay(100000);//wait for a uart input 
	if(serial_tstc())
	{
	    debug_rom(__FILE__,__LINE__);
	}
#else
    __udelay(1000);//delay 1 ms , wait pll ready	
#endif	
//	writel((0<<22)|1000000,P_WATCHDOG_TC);//enable Watchdog
	unsigned por_cfg;
#if CONFIG_ENABLE_SPL_DEBUG_ROM	
	if(ddr_init_test())
	    debug_rom(__FILE__,__LINE__);
#else
    do{
    }while(ddr_init_test());

#endif	    
	serial_puts("\nFirmware started, now starting u-boot...");
}
Exemple #7
0
 static void __efuse_read_dword( unsigned long addr, unsigned long *data )
 {
     unsigned long auto_rd_is_enabled = 0;

     if( READ_CBUS_REG(EFUSE_CNTL1) & ( 1 << CNTL1_AUTO_RD_ENABLE_BIT ) )
     {
         auto_rd_is_enabled = 1;
     }
     else
     {
         /* temporarily enable Read mode */
         WRITE_CBUS_REG_BITS( EFUSE_CNTL1, CNTL1_AUTO_RD_ENABLE_ON,
             CNTL1_AUTO_RD_ENABLE_BIT, CNTL1_AUTO_RD_ENABLE_SIZE );
     }

     /* write the address */
     WRITE_CBUS_REG_BITS( EFUSE_CNTL1, addr,
         CNTL1_BYTE_ADDR_BIT,  CNTL1_BYTE_ADDR_SIZE );
     /* set starting byte address */
     WRITE_CBUS_REG_BITS( EFUSE_CNTL1, CNTL1_BYTE_ADDR_SET_ON,
         CNTL1_BYTE_ADDR_SET_BIT, CNTL1_BYTE_ADDR_SET_SIZE );
     WRITE_CBUS_REG_BITS( EFUSE_CNTL1, CNTL1_BYTE_ADDR_SET_OFF,
         CNTL1_BYTE_ADDR_SET_BIT, CNTL1_BYTE_ADDR_SET_SIZE );

     /* start the read process */
     WRITE_CBUS_REG_BITS( EFUSE_CNTL1, CNTL1_AUTO_WR_START_ON,
         CNTL1_AUTO_RD_START_BIT, CNTL1_AUTO_RD_START_SIZE );
     WRITE_CBUS_REG_BITS( EFUSE_CNTL1, CNTL1_AUTO_WR_START_OFF,
         CNTL1_AUTO_RD_START_BIT, CNTL1_AUTO_RD_START_SIZE );
     /* dummy read */
     READ_CBUS_REG( EFUSE_CNTL1 );

     while ( READ_CBUS_REG(EFUSE_CNTL1) & ( 1 << CNTL1_AUTO_RD_BUSY_BIT ) )
     {
         udelay(1);
     }
     /* read the 32-bits value */
     ( *data ) = READ_CBUS_REG( EFUSE_CNTL2 );

     /* if auto read wasn't enabled and we enabled it, then disable it upon exit */
     if ( auto_rd_is_enabled == 0 )
     {
         WRITE_CBUS_REG_BITS( EFUSE_CNTL1, CNTL1_AUTO_RD_ENABLE_OFF,
             CNTL1_AUTO_RD_ENABLE_BIT, CNTL1_AUTO_RD_ENABLE_SIZE );
     }

     //printk(KERN_INFO "__efuse_read_dword: addr=%ld, data=0x%lx\n", addr, *data);
 }
static void __init LED_PWM_REG0_init(void)
{
#if 1 	// PWM_C
    printk(KERN_INFO "LED_PWM_REG0_init.\n");
	 SET_CBUS_REG_MASK(PERIPHS_PIN_MUX_2,(1<<2));
    WRITE_CBUS_REG(PWM_PWM_C, (0xff00<<16) |(0xff00<<0));
    WRITE_CBUS_REG(PWM_MISC_REG_CD, (1<<0)	// enable
																			|(0<<4)	// PWM_A_CLK_SEL: 0:XTAL;  1:ddr_pll_clk;  2:clk81;  3:sys_pll_clk;
																			|(0x7f<<8)	// PWM_A_CLK_DIV
																			|(1<<15)	// PWM_A_CLK_EN
																			);
#else
        // Enable VBG_EN
    WRITE_CBUS_REG_BITS(PREG_AM_ANALOG_ADDR, 1, 0, 1);
    // wire pm_gpioA_7_led_pwm = pin_mux_reg0[22];
    WRITE_CBUS_REG(LED_PWM_REG0,(0 << 31)   |       // disable the overall circuit
                                (0 << 30)   |       // 1:Closed Loop  0:Open Loop
                                (0 << 16)   |       // PWM total count
                                (0 << 13)   |       // Enable
                                (1 << 12)   |       // enable
                                (0 << 10)   |       // test
                                (7 << 7)    |       // CS0 REF, Voltage FeedBack: about 0.505V
                                (7 << 4)    |       // CS1 REF, Current FeedBack: about 0.505V
                                READ_CBUS_REG(LED_PWM_REG0)&0x0f);           // DIMCTL Analog dimmer
                                
    WRITE_CBUS_REG_BITS(LED_PWM_REG0,1,0,4); //adust cpu1.2v   to 1.26V     
#endif
}
static void set_hpll_clk_out(unsigned clk)
{
    switch(clk){
        case 1488:
            WRITE_CBUS_REG(HHI_VID_PLL_CNTL, 0x43e);
            break;
        case 1080:
            WRITE_CBUS_REG(HHI_VID_PLL_CNTL, 0x42d);
            break;
        case 1066:
            WRITE_CBUS_REG(HHI_VID_PLL_CNTL, 0x42a);
            break;
        case 1058:
            WRITE_CBUS_REG(HHI_VID_PLL_CNTL, 0x422);
            break;
        case 1086:
            WRITE_CBUS_REG(HHI_VID_PLL_CNTL, 0x43e);
            break;
        default:
            break;
    }
#ifdef CONFIG_ARCH_MESON6TV
    WRITE_CBUS_REG(HHI_VID_PLL_CNTL, READ_CBUS_REG(HHI_VID_PLL_CNTL) | (1 << 30));      // bit[30]: 1: Power Up, 0: Power Down, different from M6
#endif

}
unsigned sdio_check_interrupt(void)
{
        unsigned long status_irq;
        SDIO_Status_IRQ_Reg_t * status_irq_reg;
        status_irq = READ_CBUS_REG(SDIO_STATUS_IRQ);
        status_irq_reg = (void *)&status_irq;

        if (status_irq_reg->cmd_int) {
                status_irq_reg->cmd_int = 1;
                status_irq_reg->arc_timing_out_int_en = 0;
                status_irq_reg->timing_out_int = 1;
                WRITE_CBUS_REG(SDIO_STATUS_IRQ, status_irq);
                return SDIO_CMD_INT;
        }
        else if (status_irq_reg->timing_out_int) {
                status_irq_reg->timing_out_int = 1;
                status_irq_reg->timing_out_count = 0x1FFF;
                WRITE_CBUS_REG(SDIO_STATUS_IRQ, status_irq);
                return SDIO_TIMEOUT_INT;
        }
        else if (status_irq_reg->if_int) {
                status_irq_reg->if_int = 1;
                WRITE_CBUS_REG(SDIO_STATUS_IRQ, status_irq);
                return SDIO_IF_INT;
        }
        else if (status_irq_reg->soft_int)
                return SDIO_SOFT_INT;
        else
                return SDIO_NO_INT;
}
void sdio_clear_host_interrupt(unsigned int_resource)
{
        unsigned long status_irq;
        SDIO_Status_IRQ_Reg_t * status_irq_reg;
        status_irq = READ_CBUS_REG(SDIO_STATUS_IRQ);
        status_irq_reg = (void *)&status_irq;

        switch (int_resource) {
        case SDIO_IF_INT:
                status_irq_reg->if_int = 1;
                break;


        case SDIO_CMD_INT:
                status_irq_reg->cmd_int = 1;
                break;

        case SDIO_SOFT_INT:
                status_irq_reg->soft_int = 1;
                break;


        case SDIO_TIMEOUT_INT:
                status_irq_reg->timing_out_int = 1;
                status_irq_reg->timing_out_count = 0x1FFF;
                break;

        default:
                break;
        }

        WRITE_CBUS_REG(SDIO_STATUS_IRQ, status_irq);
}
Exemple #12
0
 static void __efuse_write_byte( unsigned long addr, unsigned long data )
 {
     unsigned long auto_wr_is_enabled = 0;

     if ( READ_CBUS_REG( EFUSE_CNTL1) & ( 1 << CNTL1_AUTO_WR_ENABLE_BIT ) )
     {
         auto_wr_is_enabled = 1;
     }
     else
     {
         /* temporarily enable Write mode */
         WRITE_CBUS_REG_BITS( EFUSE_CNTL1, CNTL1_AUTO_WR_ENABLE_ON,
             CNTL1_AUTO_WR_ENABLE_BIT, CNTL1_AUTO_WR_ENABLE_SIZE );
     }

     /* write the address */
     WRITE_CBUS_REG_BITS( EFUSE_CNTL1, addr,
         CNTL1_BYTE_ADDR_BIT, CNTL1_BYTE_ADDR_SIZE );
     /* set starting byte address */
     WRITE_CBUS_REG_BITS( EFUSE_CNTL1, CNTL1_BYTE_ADDR_SET_ON,
         CNTL1_BYTE_ADDR_SET_BIT, CNTL1_BYTE_ADDR_SET_SIZE );
     WRITE_CBUS_REG_BITS( EFUSE_CNTL1, CNTL1_BYTE_ADDR_SET_OFF,
         CNTL1_BYTE_ADDR_SET_BIT, CNTL1_BYTE_ADDR_SET_SIZE );

     /* write the byte */
     WRITE_CBUS_REG_BITS( EFUSE_CNTL1, data,
         CNTL1_BYTE_WR_DATA_BIT, CNTL1_BYTE_WR_DATA_SIZE );
     /* start the write process */
     WRITE_CBUS_REG_BITS( EFUSE_CNTL1, CNTL1_AUTO_WR_START_ON,
         CNTL1_AUTO_WR_START_BIT, CNTL1_AUTO_WR_START_SIZE );
     WRITE_CBUS_REG_BITS( EFUSE_CNTL1, CNTL1_AUTO_WR_START_OFF,
         CNTL1_AUTO_WR_START_BIT, CNTL1_AUTO_WR_START_SIZE );
     /* dummy read */
     READ_CBUS_REG( EFUSE_CNTL1 );

     while ( READ_CBUS_REG(EFUSE_CNTL1) & ( 1 << CNTL1_AUTO_WR_BUSY_BIT ) )
     {
         udelay(1);
     }

     /* if auto write wasn't enabled and we enabled it, then disable it upon exit */
     if (auto_wr_is_enabled == 0 )
     {
         WRITE_CBUS_REG_BITS( EFUSE_CNTL1, CNTL1_AUTO_WR_ENABLE_OFF,
             CNTL1_AUTO_WR_ENABLE_BIT, CNTL1_AUTO_WR_ENABLE_SIZE );
     }
 }
Exemple #13
0
void clk_switch(int flag)
{
    int i;

    if (flag) {
        for (i = CLK_COUNT - 1; i >= 0; i--) {
            if (clk_flag[i]) {
                if ((clks[i] == HHI_VID_CLK_CNTL)||(clks[i] == HHI_VIID_CLK_CNTL)) {
                    WRITE_CBUS_REG_BITS(clks[i], clk_flag[i], 19, 2);
                } else if (clks[i] == HHI_MPEG_CLK_CNTL) {
                    udelay(1000);
                    SET_CBUS_REG_MASK(clks[i], (1 << 8)); // normal

                    CLEAR_CBUS_REG_MASK(UART0_CONTROL, (1 << 19) | 0xFFF);
                    SET_CBUS_REG_MASK(UART0_CONTROL, (((uart_rate_backup / (115200 * 4)) - 1) & 0xfff));
                    CLEAR_CBUS_REG_MASK(UART1_CONTROL, (1 << 19) | 0xFFF);
                    SET_CBUS_REG_MASK(UART1_CONTROL, (((uart_rate_backup / (115200 * 4)) - 1) & 0xfff));
                    CLEAR_AOBUS_REG_MASK(AO_UART_CONTROL, (1 << 19) | 0xFFF);
                    WRITE_AOBUS_REG_BITS(AO_UART_CONTROL, ((uart_rate_backup / (115200 * 4)) - 1) & 0xfff, 0, 12);
                } else {
                    SET_CBUS_REG_MASK(clks[i], (1 << 8));
                }
                clk_flag[i] = 0;
                printf("clk %s(%x) on\n", clks_name[i], clks[i]);
            }
        }
    } else {
        for (i = 0; i < CLK_COUNT; i++) {
            if ((clks[i] == HHI_VID_CLK_CNTL)||(clks[i] == HHI_VIID_CLK_CNTL)) {
                clk_flag[i] = READ_CBUS_REG_BITS(clks[i], 19, 2);
                if (clk_flag[i]) {
                    CLEAR_CBUS_REG_MASK(clks[i], (1<<19)|(1<<20));
                }
            } else if (clks[i] == HHI_MPEG_CLK_CNTL) {
                if (READ_CBUS_REG(clks[i]) & (1 << 8)) {
                    clk_flag[i] = 1;

                    udelay(1000);
                    CLEAR_CBUS_REG_MASK(clks[i], (1 << 8)); // 24M

                    CLEAR_CBUS_REG_MASK(UART0_CONTROL, (1 << 19) | 0xFFF);
                    SET_CBUS_REG_MASK(UART0_CONTROL, (((xtal_uart_rate_backup / (115200 * 4)) - 1) & 0xfff));
                    CLEAR_CBUS_REG_MASK(UART1_CONTROL, (1 << 19) | 0xFFF);
                    SET_CBUS_REG_MASK(UART1_CONTROL, (((xtal_uart_rate_backup / (115200 * 4)) - 1) & 0xfff));
                    CLEAR_AOBUS_REG_MASK(AO_UART_CONTROL, (1 << 19) | 0xFFF);
                    WRITE_AOBUS_REG_BITS(AO_UART_CONTROL, ((xtal_uart_rate_backup / (115200 * 4)) - 1) & 0xfff, 0, 12);
                }
            } else {
                clk_flag[i] = READ_CBUS_REG_BITS(clks[i], 8, 1) ? 1 : 0;
                if (clk_flag[i]) {
                    CLEAR_CBUS_REG_MASK(clks[i], (1 << 8));
                }
            }
            if (clk_flag[i]) {
                printf("clk %s(%x) off\n", clks_name[i], clks[i]);
            }
        }
    }
}
Exemple #14
0
static void set_lcd_gamma_table(u16 *data, u32 rgb_mask)
{
	int i = 0;

	while (!(READ_CBUS_REG(L_GAMMA_CNTL_PORT) & (0x1 << ADR_RDY)));
		WRITE_CBUS_REG(L_GAMMA_ADDR_PORT, (0x1 << H_AUTO_INC) |
						    (0x1 << rgb_mask)   |
						    (0x0 << HADR));
	for (i = 0;i < 256; i++) {
		while (!( READ_CBUS_REG(L_GAMMA_CNTL_PORT) & (0x1 << WR_RDY) )) ;
			WRITE_CBUS_REG(L_GAMMA_DATA_PORT, data[i]);
	}
	while (!(READ_CBUS_REG(L_GAMMA_CNTL_PORT) & (0x1 << ADR_RDY)));
	WRITE_CBUS_REG(L_GAMMA_ADDR_PORT, (0x1 << H_AUTO_INC) |
					    (0x1 << rgb_mask)   |
					    (0x23 << HADR));
}
static cycle_t cycle_read_timerE(struct clocksource *cs)
{
    static cycle_t last = 0,old = 0;
    cycle_t cur = READ_CBUS_REG(ISA_TIMERE);
    last += (cur >= old) ? (cur - old) : (cur + (0x1000000 - old));
    old = cur;
	return (cycles_t) last;
}
// viu_channel_sel: 1 or 2
// viu_type_sel: 0: 0=ENCL, 1=ENCI, 2=ENCP, 3=ENCT.
int set_viu_path(unsigned viu_channel_sel, viu_type_e viu_type_sel)
{
    if((viu_channel_sel > 2) || (viu_channel_sel == 0))
        return -1;
    printk("VPU_VIU_VENC_MUX_CTRL: 0x%x\n", READ_CBUS_REG(VPU_VIU_VENC_MUX_CTRL));
    if(viu_channel_sel == 1){
        WRITE_CBUS_REG_BITS(VPU_VIU_VENC_MUX_CTRL, viu_type_sel, 0, 2);
        printk("viu chan = 1\n");
    }
    else{
        //viu_channel_sel ==2
        WRITE_CBUS_REG_BITS(VPU_VIU_VENC_MUX_CTRL, viu_type_sel, 2, 2);
        printk("viu chan = 2\n");
    }
    printk("VPU_VIU_VENC_MUX_CTRL: 0x%x\n", READ_CBUS_REG(VPU_VIU_VENC_MUX_CTRL));
    return 0;
}
static void reset_am_mipi_csi2_adapter(void)
{
    unsigned data32 = READ_CBUS_REG(CSI2_GEN_CTRL0);
    data32 &=((~0xf)<<CSI2_CFG_VIRTUAL_CHANNEL_EN);
    WRITE_CBUS_REG(CSI2_GEN_CTRL0,data32);  // disable virtual channel
    WRITE_CBUS_REG(CSI2_INTERRUPT_CTRL_STAT,   0x7<<CSI2_CFG_FIELD_DONE_INTERRUPT_CLR); // clear status,disable interrupt
    WRITE_CBUS_REG(CSI2_CLK_RESET, (1<<CSI2_CFG_SW_RESET)|(1<<CSI2_CFG_CLK_AUTO_GATE_OFF)); // disable auto gate and clock 
    return;
}
static void reset_bt656in_module(void)
{
	int temp_data;

	temp_data = READ_CBUS_REG(BT_CTRL);
	temp_data &= ~( 1 << BT_EN_BIT );
	WRITE_CBUS_REG(BT_CTRL, temp_data); //disable BT656 input

	// reset BT656in module.
	temp_data = READ_CBUS_REG(BT_CTRL);
	temp_data |= ( 1 << BT_SOFT_RESET );
	WRITE_CBUS_REG(BT_CTRL, temp_data);

	temp_data = READ_CBUS_REG(BT_CTRL);
	temp_data &= ~( 1 << BT_SOFT_RESET );
	WRITE_CBUS_REG(BT_CTRL, temp_data);

}
_mali_osk_errcode_t mali_platform_power_mode_change(mali_power_mode power_mode)
{
    /* turn off MALI clock gating */
    unsigned long flags;
    unsigned cpu_divider, mali_divider;
    unsigned ddr_pll_setting, sys_pll_setting;
    unsigned cpu_freq, ddr_freq;
    int mali_flag;

    switch (power_mode) {
        case MALI_POWER_MODE_LIGHT_SLEEP:
            /* turn on MALI clock gating */
			CLEAR_CBUS_REG_MASK(HHI_MALI_CLK_CNTL, 1 << 8);
			break;
	    case MALI_POWER_MODE_DEEP_SLEEP:
            /* turn on MALI clock gating */
            CLEAR_CBUS_REG_MASK(HHI_MALI_CLK_CNTL, 1 << 8);
            break;
        case MALI_POWER_MODE_ON:
            /* turn off MALI clock gating */
			local_irq_save(flags);
			CLEAR_CBUS_REG_MASK(HHI_MALI_CLK_CNTL, 1 << 8);

			sys_pll_setting = READ_MPEG_REG(HHI_SYS_PLL_CNTL);
			cpu_freq = ((sys_pll_setting&0x1ff)*24)>>(sys_pll_setting>>16); // assume 24M xtal
			cpu_divider = READ_MPEG_REG_BITS(HHI_SYS_CPU_CLK_CNTL, 2, 2);
			if (cpu_divider == 3)
				cpu_divider = 2; // now fix at /4
			cpu_freq >>= cpu_divider;

			ddr_pll_setting = READ_MPEG_REG(HHI_DDR_PLL_CNTL);
			ddr_freq = ((ddr_pll_setting&0x1ff)*24)>>((ddr_pll_setting>>16)&3);

			mali_divider = 1;
			while ((mali_divider * cpu_freq < ddr_freq) || (264 * mali_divider < ddr_freq)) // assume mali max 264M
				mali_divider++;
			mali_flag = ((mali_divider-1) != (READ_MPEG_REG(HHI_MALI_CLK_CNTL)&0x7f));
			if (mali_flag){
				WRITE_CBUS_REG(HHI_MALI_CLK_CNTL,
					(3 << 9)    |                   // select ddr pll as clock source
					((mali_divider-1) << 0)); // ddr clk / divider
				READ_CBUS_REG(HHI_MALI_CLK_CNTL); // delay
			}
			SET_CBUS_REG_MASK(HHI_MALI_CLK_CNTL, 1 << 8);
			local_irq_restore(flags);
			if (mali_flag)
				printk("(CTS_MALI_CLK) = %d/%d = %dMHz --- when mali gate on\n", ddr_freq, mali_divider, ddr_freq/mali_divider);

            mali_meson_poweron();
            break;
    }

    last_power_mode = power_mode;

    MALI_SUCCESS;
}
Exemple #20
0
 void local_dump_usb_reg()
{
	printf("hisun: usb addr= 0x%x val= 0x%x\n",
			P_USB_ADDR0,READ_CBUS_REG(USB_ADDR0));

	printf("hisun: usb addr= 0x%x val= 0x%x\n",
		P_USB_ADDR1,READ_CBUS_REG(USB_ADDR1));

	printf("hisun: usb addr= 0x%x val= 0x%x\n",
		P_USB_ADDR2,READ_CBUS_REG(USB_ADDR2));

	printf("hisun: usb addr= 0x%x val= 0x%x\n",
		P_USB_ADDR3,READ_CBUS_REG(USB_ADDR3));

	printf("hisun: usb addr= 0x%x val= 0x%x\n",
		P_USB_ADDR4,READ_CBUS_REG(USB_ADDR4));


}
static int aml_wdt_suspend(struct platform_device *pdev, pm_message_t state)
{
	reg_wdt_ctrl_saved = READ_CBUS_REG(WATCHDOG_TC);
	aml_wdt_set_enable(false);
	aml_wdt_keepalive(); /* i think it is no usage */
	del_timer(&ping_timer);
	user_pet = 0;
	user_pet_timer_count = 0;
	return 0;
}
static void save_pinmux(void)
{
	int i;
	for (i=0;i<6;i++)
		pinmux_backup[i] = READ_CBUS_REG(PERIPHS_PIN_MUX_0+i);
	for (i=0;i<MAX_PINMUX;i++){
		if (pinmux_data[i].enable){
			printk("%s %x\n", pinmux_data[i].name, pinmux_data[i].bits);
			clear_mio_mux(pinmux_data[i].reg, pinmux_data[i].bits);
		}
	}
}
Exemple #23
0
int get_adc_sample(int chan)
{
	int count;
	int value = -1;
	int sum;
	
	set_chan_list(chan, 1);
	set_avg_mode(chan, NO_AVG_MODE, SAMPLE_NUM_8);
	set_sample_mux(chan, g_chan_mux[chan]);
	set_detect_mux(g_chan_mux[chan]);
	set_idle_mux(g_chan_mux[chan]); // for revb
	enable_sample_engine();
	start_sample();

	// Read any CBUS register to delay one clock
	// cycle after starting the sampling engine
	// The bus is really fast and we may miss that it started
	{ count = READ_CBUS_REG(ISA_TIMERE); }

	count = 0;
	while (delta_busy() || sample_busy() || avg_busy()){
		if (++count > 10000){
			printf("ADC busy error.\n");
			goto adc_sample_end;
			}
	}
	
    stop_sample();
    
    sum = 0;
    count = 0;
    value = get_fifo_sample();

	while (get_fifo_cnt()){
        value = get_fifo_sample() & 0x3ff;
        if ((value != 0x1fe) && (value != 0x1ff)){
			sum += value & 0x3ff;
            count++;
        }
	}
	value = (count) ? (sum / count) : (-1);

adc_sample_end:
	
#if AML_ADC_SAMPLE_DEBUG
	printf("ch%d = %d, count=%d\n", chan, value, count);
#endif //AML_ADC_SAMPLE_DEBUG

	disable_sample_engine();
	set_sc_phase();
	return value;
}
void hdmirx_set_pinmux(void)
{
	WRITE_CBUS_REG(PERIPHS_PIN_MUX_0 , READ_CBUS_REG(PERIPHS_PIN_MUX_0 )|
				( (1 << 27)   |   // pm_gpioW_0_hdmirx_5V_A  
				(1 << 26)   |   // pm_gpioW_1_hdmirx_HPD_A 
				(1 << 25)   |   // pm_gpioW_2_hdmirx_scl_A 
				(1 << 24)   |   // pm_gpioW_3_hdmirx_sda_A 
				(1 << 23)   |   // pm_gpioW_4_hdmirx_5V_B  
				(1 << 22)   |   // pm_gpioW_5_hdmirx_HPD_B 
				(1 << 21)   |   // pm_gpioW_6_hdmirx_scl_B 
				(1 << 20)   |   // pm_gpioW_7_hdmirx_sda_B 
				(1 << 19)   |   // pm_gpioW_8_hdmirx_5V_C  
				(1 << 18)   |   // pm_gpioW_9_hdmirx_HPD_C 
				(1 << 17)   |   // pm_gpioW_10_hdmirx_scl_C
				(1 << 16)   |   // pm_gpioW_11_hdmirx_sda_C
				(1 << 15)   |   // pm_gpioW_12_hdmirx_5V_D 
				(1 << 14)   |   // pm_gpioW_13_hdmirx_HPD_D
				(1 << 13)   |   // pm_gpioW_14_hdmirx_scl_D
				(1 << 12)   |   // pm_gpioW_15_hdmirx_sda_D
				(1 << 11)));     // pm_gpioW_16_hdmirx_cec  
#ifdef USE_GPIO_FOR_HPD
    WRITE_CBUS_REG(PERIPHS_PIN_MUX_0, READ_CBUS_REG(PERIPHS_PIN_MUX_0 ) &
                (~((1<<26)|(1<<22)|(1<<18)|(1<<14))));
                
    WRITE_CBUS_REG(PREG_PAD_GPIO5_EN_N, READ_CBUS_REG(PREG_PAD_GPIO5_EN_N) &
                (~((1<<1)|(1<<5)|(1<<9)|(1<<13))));

    WRITE_CBUS_REG(PREG_PAD_GPIO5_O, READ_CBUS_REG(PREG_PAD_GPIO5_O) |
                ((1<<1)|(1<<5)|(1<<9)|(1<<13)));
#endif

#if 0
	WRITE_CBUS_REG(PERIPHS_PIN_MUX_1 , READ_CBUS_REG(PERIPHS_PIN_MUX_1 )|
				( (1 << 2)    |   // pm_gpioW_17_hdmirx_tmds_clk
				(1 << 1)    |   // pm_gpioW_18_hdmirx_pix_clk 
				(1 << 0)));      // pm_gpioW_19_hdmirx_audmeas 
#endif

}    
void sdio_close_host_interrupt(unsigned int_resource)
{
        unsigned long irq_config, status_irq;
        MSHW_IRQ_Config_Reg_t * irq_config_reg;
        SDIO_Status_IRQ_Reg_t * status_irq_reg;
        irq_config = READ_CBUS_REG(SDIO_IRQ_CONFIG);
        status_irq = READ_CBUS_REG(SDIO_STATUS_IRQ);
        irq_config_reg = (void *)&irq_config;
        status_irq_reg = (void *)&status_irq;

        switch (int_resource) {
        case SDIO_IF_INT:
                irq_config_reg->arc_if_int_en = 0;
                status_irq_reg->if_int = 1;
                break;

        case SDIO_CMD_INT:
                irq_config_reg->arc_cmd_int_en = 0;
                status_irq_reg->cmd_int = 1;
                break;

        case SDIO_SOFT_INT:
                irq_config_reg->arc_soft_int_en = 0;
                status_irq_reg->soft_int = 1;
                break;

        case SDIO_TIMEOUT_INT:
                status_irq_reg->arc_timing_out_int_en = 0;
                status_irq_reg->timing_out_int = 1;
                break;

        default:
                break;
        }

        WRITE_CBUS_REG(SDIO_IRQ_CONFIG, irq_config);
        WRITE_CBUS_REG(SDIO_STATUS_IRQ, status_irq);
}
int eth_clk_set(int selectclk,unsigned long clk_freq, unsigned long out_clk)
{
    int n = 1;
    int clk = READ_CBUS_REG(HHI_ETH_CLK_CNTL);
    printk("select eth clk-%d,source=%ld,out=%ld,reg=%x\n",selectclk, clk_freq, out_clk, clk);
    if (out_clk == 0)
    {
        WRITE_CBUS_REG(HHI_ETH_CLK_CNTL,
            clk & (~(1<<8)) //disable clk
        );
    }
    else
    {
        if(((clk_freq)%out_clk)!=0)
        {
            printk(KERN_ERR "ERROR:source clk must n times of out_clk=%ld ,source clk=%ld\n", out_clk, clk_freq);
            return -1;
        }
        else
        {
            n=(int)((clk_freq)/out_clk);
        }

        WRITE_CBUS_REG(HHI_ETH_CLK_CNTL,
            (n-1)<<0 |
            selectclk<<9 |
            1<<8 //enable clk
        );
    }

    //writel(0x70b,(0xc1100000+0x1076*4));  // enable Ethernet clocks   for other clock 600/12
    //writel(0x107,(0xc1100000+0x1076*4));  // enable Ethernet clocks   for sys clock 1200/3/8
    udelay(100);
    clk = READ_CBUS_REG(HHI_ETH_CLK_CNTL);
    printk("after clk set : reg=%x\n",clk);
    return 0;
}
Exemple #27
0
void saradc_enable(void)
{
	int i;

	//set adc clock as 1.28Mhz @sys=27MHz
	set_clock_divider(20);
	enable_clock();
	enable_adc();

	set_sample_mode(DIFF_MODE);
	set_tempsen(0);
	disable_fifo_irq();
	disable_continuous_sample();
	disable_chan0_delta();
	disable_chan1_delta();

	set_input_delay(10, INPUT_DELAY_TB_1US);
	set_sample_delay(10, SAMPLE_DELAY_TB_1US);
	set_block_delay(10, BLOCK_DELAY_TB_1US);
	
	// channels sampling mode setting
	for(i=0; i<AML_ADC_SARADC_CHAN_NUM; i++) {
		set_sample_sw(i, IDLE_SW);
		set_sample_mux(i, g_chan_mux[i]);
	}
	
	// idle mode setting
	set_idle_sw(IDLE_SW);
	set_idle_mux(g_chan_mux[AML_ADC_CHAN_0]);
	
	// detect mode setting
	set_detect_sw(DETECT_SW);
	set_detect_mux(g_chan_mux[AML_ADC_CHAN_0]);
	disable_detect_sw();
	disable_detect_pullup();
	set_detect_irq_pol(0);
	disable_detect_irq();
	set_sc_phase();
	enable_sample_engine();

#if AML_ADC_SAMPLE_DEBUG
	printf("ADCREG reg0 =%x\n",   READ_CBUS_REG(SAR_ADC_REG0));
	printf("ADCREG ch list =%x\n",READ_CBUS_REG(SAR_ADC_CHAN_LIST));
	printf("ADCREG avg  =%x\n",   READ_CBUS_REG(SAR_ADC_AVG_CNTL));
	printf("ADCREG reg3 =%x\n",   READ_CBUS_REG(SAR_ADC_REG3));
	printf("ADCREG ch72 sw =%x\n",READ_CBUS_REG(SAR_ADC_AUX_SW));
	printf("ADCREG ch10 sw =%x\n",READ_CBUS_REG(SAR_ADC_CHAN_10_SW));
	printf("ADCREG detect&idle=%x\n",READ_CBUS_REG(SAR_ADC_DETECT_IDLE_SW));
#endif //AML_ADC_SAMPLE_DEBUG

}
static void aml_audio_clock_gating_disable(void)
{
	struct snd_soc_codec* codec;
	//printk("***Entered %s:%s\n", __FILE__,__func__);
	//WRITE_CBUS_REG(HHI_GCLK_MPEG0, READ_CBUS_REG(HHI_GCLK_MPEG0)&~(1<<18));
	WRITE_CBUS_REG(HHI_GCLK_MPEG1, READ_CBUS_REG(HHI_GCLK_MPEG1)&~(1<<2)
								    //&~(0xFF<<6)
								    );
	//WRITE_CBUS_REG(HHI_GCLK_MPEG2, READ_CBUS_REG(HHI_GCLK_MPEG2)&~(1<<10));
	//WRITE_CBUS_REG(HHI_GCLK_OTHER, READ_CBUS_REG(HHI_GCLK_OTHER)&~(1<<10)
								    //&~(1<<18)
								    //&~(0x7<<14));
	mute_spk(codec,1);							    
	WRITE_APB_REG(APB_ADAC_POWER_CTRL_REG2, READ_APB_REG(APB_ADAC_POWER_CTRL_REG2)&(~(1<<7)));
	adac_latch();
	
}
Exemple #29
0
static int control_ts_on_csi_port(int tsin, int enable)
{
#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8
	unsigned int temp_data;
	if(tsin==2 && enable) {
		//TS2 is on CSI port.
		//power on mipi csi phy
		pr_error("power on mipi csi phy for TSIN2\n");
		WRITE_CBUS_REG(HHI_CSI_PHY_CNTL0,0xfdc1ff81);
		WRITE_CBUS_REG(HHI_CSI_PHY_CNTL1,0x3fffff);
		temp_data = READ_CBUS_REG(HHI_CSI_PHY_CNTL2);
		temp_data &= 0x7ff00000;
		temp_data |= 0x80000fc0;
		WRITE_CBUS_REG(HHI_CSI_PHY_CNTL2,temp_data);
	}
#endif
	return 0;
}
static void aml_audio_clock_gating_enable(void)
{
	struct snd_soc_codec* codec;
	printk("***Entered %s:%s\n", __FILE__,__func__);
	//WRITE_CBUS_REG(HHI_GCLK_MPEG0, READ_CBUS_REG(HHI_GCLK_MPEG0)|(1<<18));
	WRITE_CBUS_REG(HHI_GCLK_MPEG1, READ_CBUS_REG(HHI_GCLK_MPEG1)|(1<<2)
								    //|(0xFF<<6)
								    );
	//WRITE_CBUS_REG(HHI_GCLK_MPEG2, READ_CBUS_REG(HHI_GCLK_MPEG2)|(1<<10));
	//WRITE_CBUS_REG(HHI_GCLK_OTHER, READ_CBUS_REG(HHI_GCLK_OTHER)|(1<<10)
								    //|(1<<18)
								    //|(0x7<<14));
	WRITE_APB_REG(APB_ADAC_POWER_CTRL_REG2, READ_APB_REG(APB_ADAC_POWER_CTRL_REG2)|(1<<7));
	if(aml_m3_is_hp_pluged()){
		mute_spk(codec,1);	
	}
	else 
		mute_spk(codec,0);
	adac_latch();
}