void early_pll_switch(int flag)
{
int i;
if (flag) {
for (i = EARLY_PLL_COUNT - 1; i >= 0; i--) {
if (early_pll_flag[i]) {
if ((early_plls[i]==HHI_VID_PLL_CNTL)||(early_plls[i]==HHI_VIID_PLL_CNTL)){
CLEAR_CBUS_REG_MASK(early_plls[i], (1 << 30));
early_pll_flag[i] = 0;
}
else{
CLEAR_CBUS_REG_MASK(early_plls[i], (1 << 15));
early_pll_flag[i] = 0;
}
printf("late pll %s(%x) on\n", early_plls_name[i], early_plls[i]);
}
}
udelay(1000);
} else {
for (i = 0; i < EARLY_PLL_COUNT; i++) {
if ((early_plls[i]==HHI_VID_PLL_CNTL)||(early_plls[i]==HHI_VIID_PLL_CNTL))
early_pll_flag[i] = READ_CBUS_REG_BITS(early_plls[i], 30, 1) ? 0 : 1;
else
early_pll_flag[i] = READ_CBUS_REG_BITS(early_plls[i], 15, 1) ? 0 : 1;
if (early_pll_flag[i]) {
printf("early pll %s(%x) off\n", early_plls_name[i], early_plls[i]);
if ((early_plls[i]==HHI_VID_PLL_CNTL)||(early_plls[i]==HHI_VIID_PLL_CNTL))
SET_CBUS_REG_MASK(early_plls[i], (1 << 30));
else
SET_CBUS_REG_MASK(early_plls[i], (1 << 15));
}
}
}
}
void clk_switch(int flag)
{
int i;
if (flag) {
for (i = CLK_COUNT - 1; i >= 0; i--) {
if (clk_flag[i]) {
if ((clks[i] == HHI_VID_CLK_CNTL)||(clks[i] == HHI_VIID_CLK_CNTL)) {
WRITE_CBUS_REG_BITS(clks[i], clk_flag[i], 19, 2);
} else if (clks[i] == HHI_MPEG_CLK_CNTL) {
udelay(1000);
SET_CBUS_REG_MASK(clks[i], (1 << 8)); // normal
CLEAR_CBUS_REG_MASK(UART0_CONTROL, (1 << 19) | 0xFFF);
SET_CBUS_REG_MASK(UART0_CONTROL, (((uart_rate_backup / (115200 * 4)) - 1) & 0xfff));
CLEAR_CBUS_REG_MASK(UART1_CONTROL, (1 << 19) | 0xFFF);
SET_CBUS_REG_MASK(UART1_CONTROL, (((uart_rate_backup / (115200 * 4)) - 1) & 0xfff));
CLEAR_AOBUS_REG_MASK(AO_UART_CONTROL, (1 << 19) | 0xFFF);
WRITE_AOBUS_REG_BITS(AO_UART_CONTROL, ((uart_rate_backup / (115200 * 4)) - 1) & 0xfff, 0, 12);
} else {
SET_CBUS_REG_MASK(clks[i], (1 << 8));
}
clk_flag[i] = 0;
printf("clk %s(%x) on\n", clks_name[i], clks[i]);
}
}
} else {
for (i = 0; i < CLK_COUNT; i++) {
if ((clks[i] == HHI_VID_CLK_CNTL)||(clks[i] == HHI_VIID_CLK_CNTL)) {
clk_flag[i] = READ_CBUS_REG_BITS(clks[i], 19, 2);
if (clk_flag[i]) {
CLEAR_CBUS_REG_MASK(clks[i], (1<<19)|(1<<20));
}
} else if (clks[i] == HHI_MPEG_CLK_CNTL) {
if (READ_CBUS_REG(clks[i]) & (1 << 8)) {
clk_flag[i] = 1;
udelay(1000);
CLEAR_CBUS_REG_MASK(clks[i], (1 << 8)); // 24M
CLEAR_CBUS_REG_MASK(UART0_CONTROL, (1 << 19) | 0xFFF);
SET_CBUS_REG_MASK(UART0_CONTROL, (((xtal_uart_rate_backup / (115200 * 4)) - 1) & 0xfff));
CLEAR_CBUS_REG_MASK(UART1_CONTROL, (1 << 19) | 0xFFF);
SET_CBUS_REG_MASK(UART1_CONTROL, (((xtal_uart_rate_backup / (115200 * 4)) - 1) & 0xfff));
CLEAR_AOBUS_REG_MASK(AO_UART_CONTROL, (1 << 19) | 0xFFF);
WRITE_AOBUS_REG_BITS(AO_UART_CONTROL, ((xtal_uart_rate_backup / (115200 * 4)) - 1) & 0xfff, 0, 12);
}
} else {
clk_flag[i] = READ_CBUS_REG_BITS(clks[i], 8, 1) ? 1 : 0;
if (clk_flag[i]) {
CLEAR_CBUS_REG_MASK(clks[i], (1 << 8));
}
}
if (clk_flag[i]) {
printf("clk %s(%x) off\n", clks_name[i], clks[i]);
}
}
}
}
inline void get_real_display_size(unsigned int *w, unsigned int *h)
{
unsigned int hstart,hend,vstart,vend;
hstart = READ_CBUS_REG_BITS(VPP_POSTBLEND_VD1_H_START_END,16,12);
hend = READ_CBUS_REG_BITS(VPP_POSTBLEND_VD1_H_START_END,0,12);
*w = hend -hstart + 1;
vstart = READ_CBUS_REG_BITS(VPP_POSTBLEND_VD1_V_START_END,16,12);
vend = READ_CBUS_REG_BITS(VPP_POSTBLEND_VD1_V_START_END,0,12);
*h = vend -vstart + 1;
}
unsigned long get_xtal_clock(void)
{
unsigned long clk;
clk = READ_CBUS_REG_BITS(PREG_CTLREG0_ADDR, 4, 5);
clk = clk * 1000 * 1000;
return clk;
}
static void it660x_send_buff_to_display_fifo(vframe_t * info)
{
if((amit660xin_dec_info.active_pixel == 720)&&(amit660xin_dec_info.para.fmt_info.fmt == TVIN_SIG_FMT_HDMI_1920x1080I_60Hz )){
unsigned char field_status = READ_CBUS_REG_BITS(VDIN_COM_STATUS0, 0, 1);
if(((READ_CBUS_REG(VDIN_WR_CTRL)>>24)&0x7) == 0x5){
field_status = field_status?0:1;
}
if(field_status == 1){
info->type = VIDTYPE_VIU_SINGLE_PLANE | VIDTYPE_VIU_422 | VIDTYPE_VIU_FIELD | VIDTYPE_INTERLACE_BOTTOM ;
}
else{
info->type = VIDTYPE_VIU_SINGLE_PLANE | VIDTYPE_VIU_422 | VIDTYPE_VIU_FIELD | VIDTYPE_INTERLACE_TOP ;
}
}
void pll_switch(int flag)
{
int i;
if (flag) {
for (i = PLL_COUNT - 1; i >= 0; i--) {
if (pll_flag[i]) {
printf("pll %s(%x) on\n", plls_name[i], plls[i]);
if ((plls[i]==HHI_VID_PLL_CNTL)||(plls[i]==HHI_VIID_PLL_CNTL)){
CLEAR_CBUS_REG_MASK(plls[i], (1 << 30));
pll_flag[i] = 0;
}
else{
CLEAR_CBUS_REG_MASK(plls[i], (1 << 15));
pll_flag[i] = 0;
}
}
}
udelay(1000);
} else {
for (i = 0; i < PLL_COUNT; i++) {
if ((plls[i]==HHI_VID_PLL_CNTL)||(plls[i]==HHI_VIID_PLL_CNTL))
pll_flag[i] = READ_CBUS_REG_BITS(plls[i], 30, 1) ? 0 : 1;
else
pll_flag[i] = READ_CBUS_REG_BITS(plls[i], 15, 1) ? 0 : 1;
if (pll_flag[i]) {
printf("pll %s(%x) off\n", plls_name[i], plls[i]);
if ((plls[i]==HHI_VID_PLL_CNTL)||(plls[i]==HHI_VIID_PLL_CNTL)){
SET_CBUS_REG_MASK(plls[i], (1 << 30));
}
else{
SET_CBUS_REG_MASK(plls[i], (1 << 15));
}
}
}
}
}
/*
* enable/disable the watchdog reset
*/
static inline void aml_wdt_set_enable(bool enable)
{
/* NOTES: if we only write the enalbe bit, the other bits of the register
* will be reset to zero, so we must save the other bits value before we
* write the enable bit.
*/
unsigned int timeout = READ_CBUS_REG_BITS(WATCHDOG_TC, 0, 22);
reset_enable = enable;
/* fix reboot by robin.zhu */
if (enable) {
aml_write_reg32(P_AO_RTI_STATUS_REG0, 0);
}
WRITE_CBUS_REG(WATCHDOG_RESET, 0);
WRITE_CBUS_REG(WATCHDOG_TC, ((enable ? 1 : 0) << WATCHDOG_ENABLE_BIT) | timeout);
}
static void aml_wdt_hw_init(bool enable, unsigned int timeout)
{
unsigned int val = 0;
enable = aml_wdt_get_enable();
/* fix reboot by robin.zhu */
if (enable) {
aml_write_reg32(P_AO_RTI_STATUS_REG0, 0);
}
val = (enable ? 1 : 0) << WATCHDOG_ENABLE_BIT;
timeout = READ_CBUS_REG_BITS(WATCHDOG_TC, 0, 22);
if ((timeout/0x186a0) < AML_WDT_STARTUP_TIMEOUT)
timeout = 0x186a0 * AML_WDT_STARTUP_TIMEOUT;
val |= timeout;
WRITE_CBUS_REG(WATCHDOG_RESET, 0);
WRITE_CBUS_REG(WATCHDOG_TC, val);
}
void early_clk_switch(int flag)
{
int i;
struct clk *sys_clk;
if (flag) {
for (i = EARLY_CLK_COUNT - 1; i >= 0; i--) {
if (early_clk_flag[i]) {
if ((early_clks[i] == HHI_VID_CLK_CNTL)||(early_clks[i] == HHI_VIID_CLK_CNTL)) {
WRITE_CBUS_REG_BITS(early_clks[i], early_clk_flag[i], 19, 2);
}
#ifdef EARLY_SUSPEND_USE_XTAL
else if (early_clks[i] == HHI_MPEG_CLK_CNTL) {
udelay(1000);
SET_CBUS_REG_MASK(early_clks[i], (1 << 8)); // clk81 back to normal
CLEAR_CBUS_REG_MASK(UART0_CONTROL, (1 << 19) | 0xFFF);
SET_CBUS_REG_MASK(UART0_CONTROL, (((uart_rate_backup / (115200 * 4)) - 1) & 0xfff));
CLEAR_CBUS_REG_MASK(UART1_CONTROL, (1 << 19) | 0xFFF);
SET_CBUS_REG_MASK(UART1_CONTROL, (((uart_rate_backup / (115200 * 4)) - 1) & 0xfff));
CLEAR_AOBUS_REG_MASK(AO_UART_CONTROL, (1 << 19) | 0xFFF);
WRITE_AOBUS_REG_BITS(AO_UART_CONTROL, ((uart_rate_backup / (115200 * 4)) - 1) & 0xfff, 0, 12);
}
#endif
else {
SET_CBUS_REG_MASK(early_clks[i], (1 << 8));
}
printf("late clk %s(%x) on\n", early_clks_name[i], early_clks[i]);
early_clk_flag[i] = 0;
}
}
} else {
//sys_clk = clk_get_sys("clk81", NULL);
uart_rate_backup = 200*1000*1000;//sys_clk->rate;
//sys_clk = clk_get_sys("clk_xtal", NULL);
xtal_uart_rate_backup = 24*1000*1000;//sys_clk->rate;
for (i = 0; i < EARLY_CLK_COUNT; i++) {
if ((early_clks[i] == HHI_VID_CLK_CNTL)||(early_clks[i] == HHI_VIID_CLK_CNTL)) {
early_clk_flag[i] = READ_CBUS_REG_BITS(early_clks[i], 19, 2);
if (early_clk_flag[i]) {
CLEAR_CBUS_REG_MASK(early_clks[i], (1<<19)|(1<<20));
}
}
#ifdef EARLY_SUSPEND_USE_XTAL
else if (early_clks[i] == HHI_MPEG_CLK_CNTL) {
early_clk_flag[i] = 1;
udelay(1000);
CLEAR_CBUS_REG_MASK(early_clks[i], (1 << 8)); // 24M
CLEAR_CBUS_REG_MASK(UART0_CONTROL, (1 << 19) | 0xFFF);
SET_CBUS_REG_MASK(UART0_CONTROL, (((xtal_uart_rate_backup / (115200 * 4)) - 1) & 0xfff));
CLEAR_CBUS_REG_MASK(UART1_CONTROL, (1 << 19) | 0xFFF);
SET_CBUS_REG_MASK(UART1_CONTROL, (((xtal_uart_rate_backup / (115200 * 4)) - 1) & 0xfff));
CLEAR_AOBUS_REG_MASK(AO_UART_CONTROL, (1 << 19) | 0xFFF);
WRITE_AOBUS_REG_BITS(AO_UART_CONTROL, ((xtal_uart_rate_backup / (115200 * 4)) - 1) & 0xfff, 0, 12);
}
#endif
else {
early_clk_flag[i] = READ_CBUS_REG_BITS(early_clks[i], 8, 1) ? 1 : 0;
if (early_clk_flag[i]) {
CLEAR_CBUS_REG_MASK(early_clks[i], (1 << 8));
}
}
if (early_clk_flag[i]) {
printf("early clk %s(%x) off\n", early_clks_name[i], early_clks[i]);
}
}
}
}
/*
* return watchdog timer timeout in second.
*/
static inline unsigned int aml_wdt_gettimeout(void)
{
return (READ_CBUS_REG_BITS(WATCHDOG_TC, 0, 22) / 0x186a0);
}
/*
* set watchdog timer timeout.
* the watchdog timer issues a chip reset when the watchdog timer timeout.
* @timeout watchdog reset timeout in second
* @todo timeout limits supported.
*/
static inline void aml_wdt_settimeout(unsigned int timeout)
{
unsigned int enable = READ_CBUS_REG_BITS(WATCHDOG_TC, WATCHDOG_ENABLE_BIT, 1);
WRITE_CBUS_REG(WATCHDOG_RESET, 0);
WRITE_CBUS_REG(WATCHDOG_TC, (enable << WATCHDOG_ENABLE_BIT) | (0x186a0 * timeout));
}
/*
* get the watchdog reset status
*/
static inline bool aml_wdt_get_enable(void)
{
return (READ_CBUS_REG_BITS(WATCHDOG_TC, WATCHDOG_ENABLE_BIT, 1) ? true : false);
}
