static int txp_download_fw_wait(struct txp_softc *sc) { u_int32_t i, r; for (i = 0; i < 10000; i++) { r = READ_REG(sc, TXP_ISR); if (r & TXP_INT_A2H_0) break; DELAY(50); } if (!(r & TXP_INT_A2H_0)) { if_printf(&sc->sc_arpcom.ac_if, "fw wait failed comm0\n"); return (-1); } WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0); r = READ_REG(sc, TXP_A2H_0); if (r != STAT_WAITING_FOR_SEGMENT) { if_printf(&sc->sc_arpcom.ac_if, "fw not waiting for segment\n"); return (-1); } return (0); }
static void grtm_hw_get_implementation(struct grtm_priv *pDev, struct grtm_ioc_hw *hwcfg) { struct grtm_regs *regs = pDev->regs; unsigned int cfg = READ_REG(pDev, ®s->cfg); hwcfg->cs = (cfg & GRTM_CFG_SC) ? 1:0; hwcfg->sp = (cfg & GRTM_CFG_SP) ? 1:0; hwcfg->ce = (cfg & GRTM_CFG_CE) ? 1:0; hwcfg->nrz = (cfg & GRTM_CFG_NRZ) ? 1:0; hwcfg->psr = (cfg & GRTM_CFG_PSR) ? 1:0; hwcfg->te = (cfg & GRTM_CFG_TE) ? 1:0; hwcfg->rsdep = (cfg & GRTM_CFG_RSDEP)>>GRTM_CFG_RSDEP_BIT; hwcfg->rs = (cfg & GRTM_CFG_RS)>>GRTM_CFG_RS_BIT; hwcfg->aasm = (cfg & GRTM_CFG_AASM) ? 1:0; hwcfg->fecf = (cfg & GRTM_CFG_FECF) ? 1:0; hwcfg->ocf = (cfg & GRTM_CFG_OCF) ? 1:0; hwcfg->evc = (cfg & GRTM_CFG_EVC) ? 1:0; hwcfg->idle = (cfg & GRTM_CFG_IDLE) ? 1:0; hwcfg->fsh = (cfg & GRTM_CFG_FSH) ? 1:0; hwcfg->mcg = (cfg & GRTM_CFG_MCG) ? 1:0; hwcfg->iz = (cfg & GRTM_CFG_IZ) ? 1:0; hwcfg->fhec = (cfg & GRTM_CFG_FHEC) ? 1:0; hwcfg->aos = (cfg & GRTM_CFG_AOS) ? 1:0; hwcfg->cif = (cfg & GRTM_CFG_CIF) ? 1:0; hwcfg->ocfb = (cfg & GRTM_CFG_OCFB) ? 1:0; cfg = READ_REG(pDev, ®s->dma_cfg); hwcfg->blk_size = (cfg & GRTM_DMA_CFG_BLKSZ) >> GRTM_DMA_CFG_BLKSZ_BIT; hwcfg->fifo_size= (cfg & GRTM_DMA_CFG_FIFOSZ) >> GRTM_DMA_CFG_FIFOSZ_BIT; }
int rgu_dram_reserved(int enable) { volatile unsigned int tmp, ret = 0; if(1 == enable) { /* enable ddr reserved mode */ tmp = READ_REG(MTK_WDT_MODE); tmp |= (MTK_WDT_MODE_DDR_RESERVE|MTK_WDT_MODE_KEY); WRITE_REG(tmp, MTK_WDT_MODE); } else if(0 == enable) { /* disable ddr reserved mode, set reset mode, disable watchdog output reset signal */ tmp = READ_REG(MTK_WDT_MODE); tmp &= (~MTK_WDT_MODE_DDR_RESERVE); tmp |= MTK_WDT_MODE_KEY; WRITE_REG(tmp, MTK_WDT_MODE); } else { print("Wrong input %d, should be 1(enable) or 0(disable) in %s\n", enable, __func__); ret = -1; } print("RGU %s:MTK_WDT_MODE(%x)\n", __func__,tmp); return ret; }
void USART3_IRQHandler() { UART_HandleTypeDef* huart = &uart_handle; uint32_t isrflags = READ_REG(huart->Instance->SR); uint32_t cr1its = READ_REG(huart->Instance->CR1); uint32_t cr3its = READ_REG(huart->Instance->CR3); uint32_t errorflags = 0x00U; /* If no error occurs */ errorflags = (isrflags & (uint32_t)(USART_SR_PE | USART_SR_FE | USART_SR_ORE | USART_SR_NE)); if (errorflags == RESET) { /* UART in mode Receiver -------------------------------------------------*/ if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) { CircleBuffer_WriteByte(&rx_, huart->Instance->DR & 0x00ff); return; } } /* If some errors occur */ if ((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET) || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET))) { /* UART parity error interrupt occurred ----------------------------------*/ if (((isrflags & USART_SR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET)) { huart->ErrorCode |= HAL_UART_ERROR_PE; } /* UART noise error interrupt occurred -----------------------------------*/ if (((isrflags & USART_SR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) { huart->ErrorCode |= HAL_UART_ERROR_NE; } /* UART frame error interrupt occurred -----------------------------------*/ if (((isrflags & USART_SR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) { huart->ErrorCode |= HAL_UART_ERROR_FE; } /* UART Over-Run interrupt occurred --------------------------------------*/ if (((isrflags & USART_SR_ORE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) { huart->ErrorCode |= HAL_UART_ERROR_ORE; } } /* UART in mode Transmitter * ------------------------------------------------*/ if (((isrflags & USART_SR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET)) { huart->Instance->DR = CircleBuffer_ReadByte(&tx_); if (CircleBuffer_GetCount(&tx_) == 0) { CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE); } return; } }
/** * Handle events from the ENC28J60. */ void enc_action(void) { uint8_t reg = READ_REG(ENC_EIR); if (reg & ENC_EIR_PKTIF) { while (READ_REG(ENC_EPKTCNT) > 0) { enc_receive_packet(); } } }
u8 spi_byte(SPI_TypeDef *spi, u8 byte) { if(READ_BIT(spi->CR1, SPI_CR1_SPE | SPI_CR1_MSTR) == (SPI_CR1_SPE | SPI_CR1_MSTR)) { READ_REG(spi->DR); while(!READ_BIT(spi->SR, SPI_SR_TXE)); WRITE_REG(spi->DR, byte); while(!READ_BIT(spi->SR, SPI_SR_RXNE)); } return (u8)READ_REG(spi->DR); }
static void ar7_wdt_prescale(u32 value) { WRITE_REG(ar7_wdt->prescale_lock, 0x5a5a); if ((READ_REG(ar7_wdt->prescale_lock) & 3) == 1) { WRITE_REG(ar7_wdt->prescale_lock, 0xa5a5); if ((READ_REG(ar7_wdt->prescale_lock) & 3) == 3) { WRITE_REG(ar7_wdt->prescale, value); return; } } pr_err("failed to unlock WDT prescale reg\n"); }
static void ar7_wdt_kick(u32 value) { WRITE_REG(ar7_wdt->kick_lock, 0x5555); if ((READ_REG(ar7_wdt->kick_lock) & 3) == 1) { WRITE_REG(ar7_wdt->kick_lock, 0xaaaa); if ((READ_REG(ar7_wdt->kick_lock) & 3) == 3) { WRITE_REG(ar7_wdt->kick, value); return; } } printk(KERN_ERR DRVNAME ": failed to unlock WDT kick reg\n"); }
static void ar7_wdt_change(u32 value) { WRITE_REG(ar7_wdt->change_lock, 0x6666); if ((READ_REG(ar7_wdt->change_lock) & 3) == 1) { WRITE_REG(ar7_wdt->change_lock, 0xbbbb); if ((READ_REG(ar7_wdt->change_lock) & 3) == 3) { WRITE_REG(ar7_wdt->change, value); return; } } pr_err("failed to unlock WDT change reg\n"); }
static void ar7_wdt_kick(u32 value) { WRITE_REG(ar7_wdt->kick_lock, 0x5555); if ((READ_REG(ar7_wdt->kick_lock) & 3) == 1) { WRITE_REG(ar7_wdt->kick_lock, 0xaaaa); if ((READ_REG(ar7_wdt->kick_lock) & 3) == 3) { WRITE_REG(ar7_wdt->kick, value); return; } } pr_err("failed to unlock WDT kick reg\n"); }
int rf69_set_crc_enable(struct spi_device *spi, enum optionOnOff optionOnOff) { #ifdef DEBUG dev_dbg(&spi->dev, "set: crc enable"); #endif switch (optionOnOff) { case optionOn: return WRITE_REG(REG_PACKETCONFIG1, (READ_REG(REG_PACKETCONFIG1) | MASK_PACKETCONFIG1_CRC_ON)); case optionOff: return WRITE_REG(REG_PACKETCONFIG1, (READ_REG(REG_PACKETCONFIG1) & ~MASK_PACKETCONFIG1_CRC_ON)); default: dev_dbg(&spi->dev, "set: illegal input param"); return -EINVAL; } }
int rf69_set_packet_format(struct spi_device *spi, enum packetFormat packetFormat) { #ifdef DEBUG dev_dbg(&spi->dev, "set: packet format"); #endif switch (packetFormat) { case packetLengthVar: return WRITE_REG(REG_PACKETCONFIG1, (READ_REG(REG_PACKETCONFIG1) | MASK_PACKETCONFIG1_PAKET_FORMAT_VARIABLE)); case packetLengthFix: return WRITE_REG(REG_PACKETCONFIG1, (READ_REG(REG_PACKETCONFIG1) & ~MASK_PACKETCONFIG1_PAKET_FORMAT_VARIABLE)); default: dev_dbg(&spi->dev, "set: illegal input param"); return -EINVAL; } }
int rf69_set_modulation(struct spi_device *spi, enum modulation modulation) { #ifdef DEBUG dev_dbg(&spi->dev, "set: modulation"); #endif switch (modulation) { case OOK: return WRITE_REG(REG_DATAMODUL, (READ_REG(REG_DATAMODUL) & ~MASK_DATAMODUL_MODULATION_TYPE) | DATAMODUL_MODULATION_TYPE_OOK); case FSK: return WRITE_REG(REG_DATAMODUL, (READ_REG(REG_DATAMODUL) & ~MASK_DATAMODUL_MODULATION_TYPE) | DATAMODUL_MODULATION_TYPE_FSK); default: dev_dbg(&spi->dev, "set: illegal input param"); return -EINVAL; } }
int rf69_set_fifo_fill_condition(struct spi_device *spi, enum fifoFillCondition fifoFillCondition) { #ifdef DEBUG dev_dbg(&spi->dev, "set: fifo fill condition"); #endif switch (fifoFillCondition) { case always: return WRITE_REG(REG_SYNC_CONFIG, (READ_REG(REG_SYNC_CONFIG) | MASK_SYNC_CONFIG_FIFO_FILL_CONDITION)); case afterSyncInterrupt: return WRITE_REG(REG_SYNC_CONFIG, (READ_REG(REG_SYNC_CONFIG) & ~MASK_SYNC_CONFIG_FIFO_FILL_CONDITION)); default: dev_dbg(&spi->dev, "set: illegal input param"); return -EINVAL; } }
int rf69_set_antenna_impedance(struct spi_device *spi, enum antennaImpedance antennaImpedance) { #ifdef DEBUG dev_dbg(&spi->dev, "set: antenna impedance"); #endif switch (antennaImpedance) { case fiftyOhm: return WRITE_REG(REG_LNA, (READ_REG(REG_LNA) & ~MASK_LNA_ZIN)); case twohundretOhm: return WRITE_REG(REG_LNA, (READ_REG(REG_LNA) | MASK_LNA_ZIN)); default: dev_dbg(&spi->dev, "set: illegal input param"); return -EINVAL; } }
int rf69_set_amplifier_2(struct spi_device *spi, enum optionOnOff optionOnOff) { #ifdef DEBUG dev_dbg(&spi->dev, "set: amp #2"); #endif switch (optionOnOff) { case optionOn: return WRITE_REG(REG_PALEVEL, (READ_REG(REG_PALEVEL) | MASK_PALEVEL_PA2)); case optionOff: return WRITE_REG(REG_PALEVEL, (READ_REG(REG_PALEVEL) & ~MASK_PALEVEL_PA2)); default: dev_dbg(&spi->dev, "set: illegal input param"); return -EINVAL; } }
void dqsi_gw_dly_coarse_factor_handler(char *factor_value) { int curr_val = atoi(factor_value); WRITE_REG((READ_REG(DRAMC_DQSCTL0/* 0xDC */) & 0xFF000000) /* Reserve original values for DRAMC_DQSCTL0[24:31] */ | ((curr_val & 0xFFF) << 0) /* DQS0CTL: DRAMC_DQSCTL0[0:11], 12 bits */ | ((curr_val & 0xFFF) << 12), /* DQS1CTL: DRAMC_DQSCTL0[12:23], 12 bits */ DRAMC_DQSCTL0/* 0xDC */); WRITE_REG((READ_REG(DRAMC_DQSCTL1/* 0xE0 */) & 0xFF000000) /* Reserve original values for DRAMC_DQSCTL1[24:31] */ | ((curr_val & 0xFFF) << 0) /* DQS2CTL: DRAMC_DQSCTL1[0:11], 12 bits */ | ((curr_val & 0xFFF) << 12), /* DQS3CTL: DRAMC_DQSCTL1[12:23], 12 bits */ DRAMC_DQSCTL1/* 0xE0 */); }
/** * @brief Retrieve the Firewall configuration. * @param fw_config: Firewall configuration, type is same as initialization structure * @note This API can't be executed inside a code area protected by the Firewall * when the Firewall is enabled * @note If NVDSL register is different from 0, that is, if the non volatile data segment * is defined, this API can't be executed when the Firewall is enabled. * @note User should resort to __HAL_FIREWALL_GET_PREARM() macro to retrieve FPA bit status * @retval None */ void HAL_FIREWALL_GetConfig(FIREWALL_InitTypeDef * fw_config) { /* Enable Firewall clock, in case no Firewall configuration has been carried out up to this point */ __HAL_RCC_FIREWALL_CLK_ENABLE(); /* Retrieve code segment protection setting */ fw_config->CodeSegmentStartAddress = (READ_REG(FIREWALL->CSSA) & FW_CSSA_ADD); fw_config->CodeSegmentLength = (READ_REG(FIREWALL->CSL) & FW_CSL_LENG); /* Retrieve non volatile data segment protection setting */ fw_config->NonVDataSegmentStartAddress = (READ_REG(FIREWALL->NVDSSA) & FW_NVDSSA_ADD); fw_config->NonVDataSegmentLength = (READ_REG(FIREWALL->NVDSL) & FW_NVDSL_LENG); /* Retrieve volatile data segment protection setting */ fw_config->VDataSegmentStartAddress = (READ_REG(FIREWALL->VDSSA) & FW_VDSSA_ADD); fw_config->VDataSegmentLength = (READ_REG(FIREWALL->VDSL) & FW_VDSL_LENG); /* Retrieve volatile data execution setting */ fw_config->VolatileDataExecution = (READ_REG(FIREWALL->CR) & FW_CR_VDE); /* Retrieve volatile data shared setting */ fw_config->VolatileDataShared = (READ_REG(FIREWALL->CR) & FW_CR_VDS); return; }
int rf69_set_tx_start_condition(struct spi_device *spi, enum txStartCondition txStartCondition) { #ifdef DEBUG dev_dbg(&spi->dev, "set: start condition"); #endif switch (txStartCondition) { case fifoLevel: return WRITE_REG(REG_FIFO_THRESH, (READ_REG(REG_FIFO_THRESH) & ~MASK_FIFO_THRESH_TXSTART)); case fifoNotEmpty: return WRITE_REG(REG_FIFO_THRESH, (READ_REG(REG_FIFO_THRESH) | MASK_FIFO_THRESH_TXSTART)); default: dev_dbg(&spi->dev, "set: illegal input param"); return -EINVAL; } }
static void hiir_config(void) { int value = 0; /* TODO: ASIC config pin share */ #if 0 value = READ_REG(IOCONFIG); value = 0; WRITE_REG(IOCONFIG, value); #endif WRITE_REG(IR_ENABLE, 0x01); while(READ_REG(IR_BUSY)) { hiir_dbg("IR_BUSY. Wait...\n"); //udelay(1); } value = (hiir_dev.dev_parm.codetype << 14); value |= (hiir_dev.dev_parm.code_len - 1) << 8; value |= (hiir_dev.dev_parm.frequence - 1); WRITE_REG(IR_CONFIG, value); value = hiir_dev.dev_parm.leads_min << 16; value |= hiir_dev.dev_parm.leads_max; WRITE_REG(CNT_LEADS, value); value = hiir_dev.dev_parm.leade_min << 16; value |= hiir_dev.dev_parm.leade_max; WRITE_REG(CNT_LEADE, value); value = hiir_dev.dev_parm.sleade_min << 16; value |= hiir_dev.dev_parm.sleade_max; WRITE_REG(CNT_SLEADE, value); value = hiir_dev.dev_parm.cnt0_b_min << 16; value |= hiir_dev.dev_parm.cnt0_b_max; WRITE_REG(CNT0_B, value); value = hiir_dev.dev_parm.cnt1_b_min << 16; value |= hiir_dev.dev_parm.cnt1_b_max; WRITE_REG(CNT1_B, value); WRITE_REG(IR_INTM, 0x00); WRITE_REG(IR_START, 0x00); //hiir_dbg("current config is...\n"); //hiir_show_reg(); }
int rf69_set_ook_threshold_type(struct spi_device *spi, enum thresholdType thresholdType) { #ifdef DEBUG dev_dbg(&spi->dev, "set: threshold type"); #endif switch (thresholdType) { case fixed: return WRITE_REG(REG_OOKPEAK, ((READ_REG(REG_OOKPEAK) & ~MASK_OOKPEAK_THRESTYPE) | OOKPEAK_THRESHTYPE_FIXED)); case peak: return WRITE_REG(REG_OOKPEAK, ((READ_REG(REG_OOKPEAK) & ~MASK_OOKPEAK_THRESTYPE) | OOKPEAK_THRESHTYPE_PEAK)); case average: return WRITE_REG(REG_OOKPEAK, ((READ_REG(REG_OOKPEAK) & ~MASK_OOKPEAK_THRESTYPE) | OOKPEAK_THRESHTYPE_AVERAGE)); default: dev_dbg(&spi->dev, "set: illegal input param"); return -EINVAL; } }
static void ar7_wdt_disable(u32 value) { WRITE_REG(ar7_wdt->disable_lock, 0x7777); if ((READ_REG(ar7_wdt->disable_lock) & 3) == 1) { WRITE_REG(ar7_wdt->disable_lock, 0xcccc); if ((READ_REG(ar7_wdt->disable_lock) & 3) == 2) { WRITE_REG(ar7_wdt->disable_lock, 0xdddd); if ((READ_REG(ar7_wdt->disable_lock) & 3) == 3) { WRITE_REG(ar7_wdt->disable, value); return; } } } pr_err("failed to unlock WDT disable reg\n"); }
int rf69_set_data_mode(struct spi_device *spi, enum dataMode dataMode) { #ifdef DEBUG dev_dbg(&spi->dev, "set: data mode"); #endif switch (dataMode) { case packet: return WRITE_REG(REG_DATAMODUL, (READ_REG(REG_DATAMODUL) & ~MASK_DATAMODUL_MODE) | DATAMODUL_MODE_PACKET); case continuous: return WRITE_REG(REG_DATAMODUL, (READ_REG(REG_DATAMODUL) & ~MASK_DATAMODUL_MODE) | DATAMODUL_MODE_CONTINUOUS); case continuousNoSync: return WRITE_REG(REG_DATAMODUL, (READ_REG(REG_DATAMODUL) & ~MASK_DATAMODUL_MODE) | DATAMODUL_MODE_CONTINUOUS_NOSYNC); default: dev_dbg(&spi->dev, "set: illegal input param"); return -EINVAL; } }
int rf69_set_adressFiltering(struct spi_device *spi, enum addressFiltering addressFiltering) { #ifdef DEBUG dev_dbg(&spi->dev, "set: address filtering"); #endif switch (addressFiltering) { case filteringOff: return WRITE_REG(REG_PACKETCONFIG1, ((READ_REG(REG_PACKETCONFIG1) & ~MASK_PACKETCONFIG1_ADDRESSFILTERING) | PACKETCONFIG1_ADDRESSFILTERING_OFF)); case nodeAddress: return WRITE_REG(REG_PACKETCONFIG1, ((READ_REG(REG_PACKETCONFIG1) & ~MASK_PACKETCONFIG1_ADDRESSFILTERING) | PACKETCONFIG1_ADDRESSFILTERING_NODE)); case nodeOrBroadcastAddress: return WRITE_REG(REG_PACKETCONFIG1, ((READ_REG(REG_PACKETCONFIG1) & ~MASK_PACKETCONFIG1_ADDRESSFILTERING) | PACKETCONFIG1_ADDRESSFILTERING_NODEBROADCAST)); default: dev_dbg(&spi->dev, "set: illegal input param"); return -EINVAL; } }
/** * Receive a single packet. * The contents will be placed in uip_buf, and uIP is called * as appropriate. */ void enc_receive_packet(void) { /* Receive a single packet */ uint8_t header[6]; uint8_t *status = header + 2; WRITE_REG(ENC_ERDPTL, enc_next_packet & 0xFF); WRITE_REG(ENC_ERDPTH, (enc_next_packet >> 8) & 0xFF); enc_rbm(header, 6); /* Update next packet pointer */ enc_next_packet = header[0] | (header[1] << 8); uint16_t data_count = status[0] | (status[1] << 8); if (status[2] & (1 << 7)) { uip_len = data_count; enc_rbm(uip_buf, data_count); if( BUF->type == htons(UIP_ETHTYPE_IP) ) { uip_arp_ipin(); uip_input(); if( uip_len > 0 ) { uip_arp_out(); enc_send_packet(uip_buf, uip_len); uip_len = 0; } } else if( BUF->type == htons(UIP_ETHTYPE_ARP) ) { uip_arp_arpin(); if( uip_len > 0 ) { //uip_arp_out(); enc_send_packet(uip_buf, uip_len); uip_len = 0; } } } uint16_t erxst = READ_REG(ENC_ERXSTL) | (READ_REG(ENC_ERXSTH) << 8); /* Mark packet as read */ if (enc_next_packet == erxst) { WRITE_REG(ENC_ERXRDPTL, READ_REG(ENC_ERXNDL)); WRITE_REG(ENC_ERXRDPTH, READ_REG(ENC_ERXNDH)); } else { WRITE_REG(ENC_ERXRDPTL, (enc_next_packet-1) & 0xFF); WRITE_REG(ENC_ERXRDPTH, ((enc_next_packet-1) >> 8) & 0xFF); } SET_REG_BITS(ENC_ECON2, ENC_ECON2_PKTDEC); }
/** * @brief Set the RXFIFO threshold. * @param hsmartcard SMARTCARD handle. * @param Threshold RX FIFO threshold value * This parameter can be one of the following values: * @arg @ref SMARTCARD_RXFIFO_THRESHOLD_1_8 * @arg @ref SMARTCARD_RXFIFO_THRESHOLD_1_4 * @arg @ref SMARTCARD_RXFIFO_THRESHOLD_1_2 * @arg @ref SMARTCARD_RXFIFO_THRESHOLD_3_4 * @arg @ref SMARTCARD_RXFIFO_THRESHOLD_7_8 * @arg @ref SMARTCARD_RXFIFO_THRESHOLD_8_8 * @retval HAL status */ HAL_StatusTypeDef HAL_SMARTCARDEx_SetRxFifoThreshold(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Threshold) { uint32_t tmpcr1 = 0; /* Check parameters */ assert_param(IS_UART_FIFO_INSTANCE(hsmartcard->Instance)); assert_param(IS_SMARTCARD_RXFIFO_THRESHOLD(Threshold)); /* Process Locked */ __HAL_LOCK(hsmartcard); hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY; /* Save actual SMARTCARD configuration */ tmpcr1 = READ_REG(hsmartcard->Instance->CR1); /* Disable SMARTCARD */ __HAL_SMARTCARD_DISABLE(hsmartcard); /* Update RX threshold configuration */ MODIFY_REG(hsmartcard->Instance->CR3, USART_CR3_RXFTCFG, Threshold); /* Determine the number of data to process during RX/TX ISR execution */ SMARTCARDEx_SetNbDataToProcess(hsmartcard); /* Restore SMARTCARD configuration */ MODIFY_REG(hsmartcard->Instance->CR1, USART_CR1_UE, tmpcr1); hsmartcard->gState = HAL_SMARTCARD_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hsmartcard); return HAL_OK; }
/** * @brief Return the FLASH User Option Byte value. * @retval The FLASH User Option Bytes values * IWDG_SW(Bit4), WWDG_SW(Bit 5), nRST_STOP(Bit 6), nRST_STDY(Bit 7), * FZ_IWDG_STOP(Bit 17), FZ_IWDG_SDBY(Bit 18), ST_RAM_SIZE(Bit[19:20]), * ePcROP_EN(Bit 21), SWAP_BANK_OPT(Bit 31) . */ static uint32_t FLASH_OB_GetUser(void) { uint32_t userConfig = READ_REG(FLASH->OPTSR_CUR); userConfig &= (~(FLASH_OPTSR_BOR_LEV | FLASH_OPTSR_RDP)); return userConfig; }
/** * @brief Enable the FIFO mode. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode(UART_HandleTypeDef *huart) { uint32_t tmpcr1; /* Check parameters */ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); /* Process Locked */ __HAL_LOCK(huart); huart->gState = HAL_UART_STATE_BUSY; /* Save actual UART configuration */ tmpcr1 = READ_REG(huart->Instance->CR1); /* Disable UART */ __HAL_UART_DISABLE(huart); /* Enable FIFO mode */ SET_BIT(tmpcr1, USART_CR1_FIFOEN); huart->FifoMode = UART_FIFOMODE_ENABLE; /* Restore UART configuration */ WRITE_REG(huart->Instance->CR1, tmpcr1); /* Determine the number of data to process during RX/TX ISR execution */ UARTEx_SetNbDataToProcess(huart); huart->gState = HAL_UART_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(huart); return HAL_OK; }
/** * @brief Set the RXFIFO threshold. * @param huart UART handle. * @param Threshold RX FIFO threshold value * This parameter can be one of the following values: * @arg @ref UART_RXFIFO_THRESHOLD_1_8 * @arg @ref UART_RXFIFO_THRESHOLD_1_4 * @arg @ref UART_RXFIFO_THRESHOLD_1_2 * @arg @ref UART_RXFIFO_THRESHOLD_3_4 * @arg @ref UART_RXFIFO_THRESHOLD_7_8 * @arg @ref UART_RXFIFO_THRESHOLD_8_8 * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold) { uint32_t tmpcr1; /* Check the parameters */ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); assert_param(IS_UART_RXFIFO_THRESHOLD(Threshold)); /* Process Locked */ __HAL_LOCK(huart); huart->gState = HAL_UART_STATE_BUSY; /* Save actual UART configuration */ tmpcr1 = READ_REG(huart->Instance->CR1); /* Disable UART */ __HAL_UART_DISABLE(huart); /* Update RX threshold configuration */ MODIFY_REG(huart->Instance->CR3, USART_CR3_RXFTCFG, Threshold); /* Determine the number of data to process during RX/TX ISR execution */ UARTEx_SetNbDataToProcess(huart); /* Restore UART configuration */ WRITE_REG(huart->Instance->CR1, tmpcr1); huart->gState = HAL_UART_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(huart); return HAL_OK; }
/** * @brief Disable the FIFO mode. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart) { uint32_t tmpcr1; /* Check parameters */ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); /* Process Locked */ __HAL_LOCK(huart); huart->gState = HAL_UART_STATE_BUSY; /* Save actual UART configuration */ tmpcr1 = READ_REG(huart->Instance->CR1); /* Disable UART */ __HAL_UART_DISABLE(huart); /* Enable FIFO mode */ CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN); huart->FifoMode = UART_FIFOMODE_DISABLE; /* Restore UART configuration */ WRITE_REG(huart->Instance->CR1, tmpcr1); huart->gState = HAL_UART_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(huart); return HAL_OK; }