paddr_t
p9000_mmap(void *v, off_t offset, int prot)
{
struct p9000_softc *sc = v;
if (offset & PGOFSET)
return (-1);
if (offset >= 0 && offset < sc->sc_sunfb.sf_fbsize) {
return (REG2PHYS(&sc->sc_phys, offset) | PMAP_NC);
}
return (-1);
}
paddr_t
cgfour_mmap(void *v, off_t offset, int prot)
{
struct cgfour_softc *sc = v;
if (offset & PGOFSET)
return (-1);
if (offset >= 0 && offset < sc->sc_sunfb.sf_fbsize) {
return (REG2PHYS(&sc->sc_phys,
PFOUR_COLOR_OFF_COLOR + offset) | PMAP_NC);
}
return (-1);
}
paddr_t
cgeight_mmap(void *v, off_t offset, int prot)
{
struct cgeight_softc *sc = v;
if (offset & PGOFSET)
return (-1);
/* Allow mapping of the 24-bit color planes */
if (offset >= 0 && offset < round_page(24 * sc->sc_sunfb.sf_fbsize)) {
return (REG2PHYS(&sc->sc_phys,
offset + PFOUR_COLOR_OFF_COLOR) | PMAP_NC);
}
return (-1);
}
paddr_t
tcx_mmap(void *v, off_t offset, int prot)
{
struct tcx_softc *sc = v;
int regno;
if (offset & PGOFSET || offset < 0)
return (-1);
/* Allow mapping as a dumb framebuffer from offset 0 */
if (sc->sc_sunfb.sf_depth == 8 && offset < sc->sc_sunfb.sf_fbsize)
regno = 0; /* copy of TCX_REG_DFB8 */
else if (sc->sc_sunfb.sf_depth != 8 &&
offset < sc->sc_sunfb.sf_fbsize * 4)
regno = 1; /* copy of TCX_REG_RDFB32 */
else
return (-1);
return (REG2PHYS(&sc->sc_phys[regno], offset) | PMAP_NC);
}
paddr_t
cgtwelve_mmap(void *v, off_t offset, int prot)
{
struct cgtwelve_softc *sc = v;
if (offset & PGOFSET || offset < 0)
return (-1);
/*
* Note that mmap() will invoke this function only if we are NOT
* in emulation mode, so we can assume 32 bit mode safely here.
*/
if (offset < sc->sc_sunfb.sf_fbsize * 32) {
return (REG2PHYS(&sc->sc_phys,
(sc->sc_highres ? CG12_OFF_INTEN_HR :
CG12_OFF_INTEN) + offset) | PMAP_NC);
}
return (-1);
}
paddr_t
p9100_mmap(void *v, off_t offset, int prot)
{
struct p9100_softc *sc = v;
struct rom_reg *rr;
if ((offset & PAGE_MASK) != 0)
return (-1);
switch (sc->sc_mapmode) {
case WSDISPLAYIO_MODE_MAPPED:
/*
* We provide the following mapping:
* 000000 - 0000ff control registers
* 002000 - 003fff command registers
* 800000 - 9fffff vram
*/
rr = &sc->sc_phys[P9100_REG_CTL];
if (offset >= 0 && offset < rr->rr_len)
break;
offset -= 0x2000;
rr = &sc->sc_phys[P9100_REG_CMD];
if (offset >= 0 && offset < rr->rr_len)
break;
offset -= (0x800000 - 0x2000);
/* FALLTHROUGH */
case WSDISPLAYIO_MODE_DUMBFB:
rr = &sc->sc_phys[P9100_REG_VRAM];
if (offset >= 0 && offset < sc->sc_vramsize)
break;
/* FALLTHROUGH */
default:
return (-1);
}
return (REG2PHYS(rr, offset) | PMAP_NC);
}