void ath9k_hw_abort_tx_dma(struct ath_hw *ah) { int i, q; REG_WRITE(ah, AR_Q_TXD, AR_Q_TXD_M); REG_SET_BIT(ah, AR_PCU_MISC, AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF); REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH); REG_SET_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF); for (q = 0; q < AR_NUM_QCU; q++) { for (i = 0; i < 1000; i++) { if (i) udelay(5); if (!ath9k_hw_numtxpending(ah, q)) break; } } REG_CLR_BIT(ah, AR_PCU_MISC, AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF); REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH); REG_CLR_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF); REG_WRITE(ah, AR_Q_TXD, 0); }
void ath9k_hw_abort_tx_dma(struct ath_hw *ah) { int maxdelay = 1000; int i, q; if (ah->curchan) { if (IS_CHAN_HALF_RATE(ah->curchan)) maxdelay *= 2; else if (IS_CHAN_QUARTER_RATE(ah->curchan)) maxdelay *= 4; } REG_WRITE(ah, AR_Q_TXD, AR_Q_TXD_M); REG_SET_BIT(ah, AR_PCU_MISC, AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF); REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH); REG_SET_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF); for (q = 0; q < AR_NUM_QCU; q++) { for (i = 0; i < maxdelay; i++) { if (i) udelay(5); if (!ath9k_hw_numtxpending(ah, q)) break; } } REG_CLR_BIT(ah, AR_PCU_MISC, AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF); REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH); REG_CLR_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF); REG_WRITE(ah, AR_Q_TXD, 0); }
/** * init mcu clock. * config system clock: FCLK HCLK PCLK * * @param[in] void * * @return none * * @note none * @authors deeve * @date 2015/4/12 */ void clock_init(void) { u32 i; REG_SET_VALUE(LOCKTIME, LOCKTIME_DEFAULT); REG_SET_VALUE(CLKDIVN, S3C2440_CLKDIV); /* 如果HDIVN非0,CPU的总线模式应该从“fast bus mode”变为“asynchronous bus mode” */ __asm__( "mrc p15, 0, r1, c1, c0, 0\n" /* read ctrl register */ "orr r1, r1, #0xc0000000\n" /* Asynchronous */ "mcr p15, 0, r1, c1, c0, 0\n" /* write ctrl register */ :::"r1" ); REG_SET_VALUE(UPLLCON, S3C2440_UPLL_CLK); /*for some delay*/ for (i = 0; i < 100; i++); REG_SET_VALUE(MPLLCON, S3C2440_MPLL_CLK); /*for some delay*/ for (i = 0; i < 8000; i++); //REG_SET_VALUE(CLKCON, CLKCON_DEFAULT); REG_CLR_BIT(CAMDIVN, CAMDIVN_HCLK3_HALF_BIT); REG_CLR_BIT(CAMDIVN, CAMDIVN_HCLK4_HALF_BIT); }
/* * This can stop or re-enables RX. * * If bool is set this will kill any frame which is currently being * transferred between the MAC and baseband and also prevent any new * frames from getting started. */ bool ath9k_hw_setrxabort(struct ath_hw *ah, bool set) { u32 reg; if (set) { REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)); if (!ath9k_hw_wait(ah, AR_OBS_BUS_1, AR_OBS_BUS_1_RX_STATE, 0, AH_WAIT_TIMEOUT)) { REG_CLR_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)); reg = REG_READ(ah, AR_OBS_BUS_1); ath_err(ath9k_hw_common(ah), "RX failed to go idle in 10 ms RXSM=0x%x\n", reg); return false; } } else { REG_CLR_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)); } return true; }
void ar9003_mci_2g5g_switch(struct ath_hw *ah, bool wait_done) { struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci; if (mci->update_2g5g) { if (mci->is_2g) { ar9003_mci_send_2g5g_status(ah, true); ar9003_mci_send_lna_transfer(ah, true); udelay(5); REG_CLR_BIT(ah, AR_MCI_TX_CTRL, AR_MCI_TX_CTRL_DISABLE_LNA_UPDATE); REG_CLR_BIT(ah, AR_PHY_GLB_CONTROL, AR_BTCOEX_CTRL_BT_OWN_SPDT_CTRL); if (!(mci->config & ATH_MCI_CONFIG_DISABLE_OSLA)) { REG_SET_BIT(ah, AR_BTCOEX_CTRL, AR_BTCOEX_CTRL_ONE_STEP_LOOK_AHEAD_EN); } } else { ar9003_mci_send_lna_take(ah, true); udelay(5); REG_SET_BIT(ah, AR_MCI_TX_CTRL, AR_MCI_TX_CTRL_DISABLE_LNA_UPDATE); REG_SET_BIT(ah, AR_PHY_GLB_CONTROL, AR_BTCOEX_CTRL_BT_OWN_SPDT_CTRL); REG_CLR_BIT(ah, AR_BTCOEX_CTRL, AR_BTCOEX_CTRL_ONE_STEP_LOOK_AHEAD_EN); ar9003_mci_send_2g5g_status(ah, true); } } }
void ar9003_mci_2g5g_switch(struct ath_hw *ah, bool force) { struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci; if (!mci->update_2g5g && !force) return; if (mci->is_2g) { ar9003_mci_send_2g5g_status(ah, true); ar9003_mci_send_lna_transfer(ah, true); udelay(5); REG_CLR_BIT(ah, AR_MCI_TX_CTRL, AR_MCI_TX_CTRL_DISABLE_LNA_UPDATE); REG_CLR_BIT(ah, AR_PHY_GLB_CONTROL, AR_BTCOEX_CTRL_BT_OWN_SPDT_CTRL); if (!(mci->config & ATH_MCI_CONFIG_DISABLE_OSLA)) ar9003_mci_osla_setup(ah, true); } else { ar9003_mci_send_lna_take(ah, true); udelay(5); REG_SET_BIT(ah, AR_MCI_TX_CTRL, AR_MCI_TX_CTRL_DISABLE_LNA_UPDATE); REG_SET_BIT(ah, AR_PHY_GLB_CONTROL, AR_BTCOEX_CTRL_BT_OWN_SPDT_CTRL); ar9003_mci_osla_setup(ah, false); ar9003_mci_send_2g5g_status(ah, true); } }
void emac_disable_flowctrl(void) { REG_CLR_BIT(EMAC_GMACFLOWCONTROL_REG, EMAC_TRANSMIT_FLOW_CONTROL_ENABLE); REG_CLR_BIT(EMAC_GMACFLOWCONTROL_REG, EMAC_RECEIVE_FLOW_CONTROL_ENABLE); REG_CLR_BIT(EMAC_GMACFLOWCONTROL_REG, EMAC_DISABLE_ZERO_QUANTA_PAUSE); REG_SET_FIELD(EMAC_GMACFLOWCONTROL_REG, EMAC_PAUSE_TIME, 0); REG_SET_FIELD(EMAC_GMACFLOWCONTROL_REG, EMAC_PAUSE_LOW_THRESHOLD, 0); }
void ath9k_hw_loadnf(struct ath_hal *ah, struct ath9k_channel *chan) { struct ath9k_nfcal_hist *h; int i, j; int32_t val; const u32 ar5416_cca_regs[6] = { AR_PHY_CCA, AR_PHY_CH1_CCA, AR_PHY_CH2_CCA, AR_PHY_EXT_CCA, AR_PHY_CH1_EXT_CCA, AR_PHY_CH2_EXT_CCA }; u8 chainmask; if (AR_SREV_9280(ah)) chainmask = 0x1B; else chainmask = 0x3F; #ifdef ATH_NF_PER_CHAN h = chan->nfCalHist; #else h = ah->nfCalHist; #endif for (i = 0; i < NUM_NF_READINGS; i++) { if (chainmask & (1 << i)) { val = REG_READ(ah, ar5416_cca_regs[i]); val &= 0xFFFFFE00; val |= (((u32) (h[i].privNF) << 1) & 0x1ff); REG_WRITE(ah, ar5416_cca_regs[i], val); } } REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_ENABLE_NF); REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NO_UPDATE_NF); REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF); for (j = 0; j < 1000; j++) { if ((REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) == 0) break; udelay(10); } for (i = 0; i < NUM_NF_READINGS; i++) { if (chainmask & (1 << i)) { val = REG_READ(ah, ar5416_cca_regs[i]); val &= 0xFFFFFE00; val |= (((u32) (-50) << 1) & 0x1ff); REG_WRITE(ah, ar5416_cca_regs[i], val); } } }
void hw_aes_hash_disable(const bool waitOnFinish) { if (waitOnFinish) hw_aes_hash_wait_on_inactive(); REG_CLR_BIT(AES_HASH, CRYPTO_CTRL_REG, CRYPTO_MORE_IN); GLOBAL_INT_DISABLE(); REG_CLR_BIT(CRG_TOP, CLK_AMBA_REG, AES_CLK_ENABLE); GLOBAL_INT_RESTORE(); NVIC_DisableIRQ(CRYPTO_IRQn); }
void hw_aes_hash_disable(const bool waitOnFinish) { if (waitOnFinish) hw_aes_hash_wait_on_inactive(); hw_aes_hash_disable_interrupt_source(); AES_HASH->CRYPTO_CLRIRQ_REG = 1; GLOBAL_INT_DISABLE(); REG_CLR_BIT(CRG_TOP, CLK_AMBA_REG, AES_CLK_ENABLE); GLOBAL_INT_RESTORE(); REG_CLR_BIT(AES_HASH, CRYPTO_CTRL_REG, CRYPTO_MORE_IN); }
void rtc_clk_wait_for_slow_cycle(void) { REG_CLR_BIT(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING | TIMG_RTC_CALI_START); REG_CLR_BIT(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_RDY); REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_CLK_SEL, RTC_CAL_RTC_MUX); /* Request to run calibration for 0 slow clock cycles. * RDY bit will be set on the nearest slow clock cycle. */ REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_MAX, 0); REG_SET_BIT(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START); ets_delay_us(1); /* RDY needs some time to go low */ while (!GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_RDY)) { ets_delay_us(1); } }
static int ath9k_rng_data_read(struct ath_softc *sc, u32 *buf, u32 buf_size) { int i, j; u32 v1, v2, rng_last = sc->rng_last; struct ath_hw *ah = sc->sc_ah; ath9k_ps_wakeup(sc); REG_RMW_FIELD(ah, AR_PHY_TEST, AR_PHY_TEST_BBB_OBS_SEL, 1); REG_CLR_BIT(ah, AR_PHY_TEST, AR_PHY_TEST_RX_OBS_SEL_BIT5); REG_RMW_FIELD(ah, AR_PHY_TEST_CTL_STATUS, AR_PHY_TEST_CTL_RX_OBS_SEL, 0); for (i = 0, j = 0; i < buf_size; i++) { v1 = REG_READ(ah, AR_PHY_TST_ADC) & 0xffff; v2 = REG_READ(ah, AR_PHY_TST_ADC) & 0xffff; /* wait for data ready */ if (v1 && v2 && rng_last != v1 && v1 != v2 && v1 != 0xffff && v2 != 0xffff) buf[j++] = (v1 << 16) | v2; rng_last = v2; } ath9k_ps_restore(sc); sc->rng_last = rng_last; return j << 2; }
static void ar9003_mci_osla_setup(struct ath_hw *ah, bool enable) { struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci; u32 thresh; if (!enable) { REG_CLR_BIT(ah, AR_BTCOEX_CTRL, AR_BTCOEX_CTRL_ONE_STEP_LOOK_AHEAD_EN); return; } REG_RMW_FIELD(ah, AR_MCI_SCHD_TABLE_2, AR_MCI_SCHD_TABLE_2_HW_BASED, 1); REG_RMW_FIELD(ah, AR_MCI_SCHD_TABLE_2, AR_MCI_SCHD_TABLE_2_MEM_BASED, 1); if (!(mci->config & ATH_MCI_CONFIG_DISABLE_AGGR_THRESH)) { thresh = MS(mci->config, ATH_MCI_CONFIG_AGGR_THRESH); REG_RMW_FIELD(ah, AR_BTCOEX_CTRL, AR_BTCOEX_CTRL_AGGR_THRESH, thresh); REG_RMW_FIELD(ah, AR_BTCOEX_CTRL, AR_BTCOEX_CTRL_TIME_TO_NEXT_BT_THRESH_EN, 1); } else REG_RMW_FIELD(ah, AR_BTCOEX_CTRL, AR_BTCOEX_CTRL_TIME_TO_NEXT_BT_THRESH_EN, 0); REG_RMW_FIELD(ah, AR_BTCOEX_CTRL, AR_BTCOEX_CTRL_ONE_STEP_LOOK_AHEAD_EN, 1); }
void emac_mac_init(void) { REG_SET_BIT(EMAC_GMACCONFIG_REG, EMAC_GMACDUPLEX); REG_SET_BIT(EMAC_GMACCONFIG_REG, EMAC_GMACMIIGMII); REG_CLR_BIT(EMAC_GMACCONFIG_REG, EMAC_GMACFESPEED); REG_SET_BIT(EMAC_GMACFRAMEFILTER_REG, EMAC_PROMISCUOUS_MODE); }
void ar9003_mci_set_power_awake(struct ath_hw *ah) { u32 btcoex_ctrl2, diag_sw; int i; u8 lna_ctrl, bt_sleep; for (i = 0; i < AH_WAIT_TIMEOUT; i++) { btcoex_ctrl2 = REG_READ(ah, AR_BTCOEX_CTRL2); if (btcoex_ctrl2 != 0xdeadbeef) break; udelay(AH_TIME_QUANTUM); } REG_WRITE(ah, AR_BTCOEX_CTRL2, (btcoex_ctrl2 | BIT(23))); for (i = 0; i < AH_WAIT_TIMEOUT; i++) { diag_sw = REG_READ(ah, AR_DIAG_SW); if (diag_sw != 0xdeadbeef) break; udelay(AH_TIME_QUANTUM); } REG_WRITE(ah, AR_DIAG_SW, (diag_sw | BIT(27) | BIT(19) | BIT(18))); lna_ctrl = REG_READ(ah, AR_OBS_BUS_CTRL) & 0x3; bt_sleep = REG_READ(ah, AR_MCI_RX_STATUS) & AR_MCI_RX_REMOTE_SLEEP; REG_WRITE(ah, AR_BTCOEX_CTRL2, btcoex_ctrl2); REG_WRITE(ah, AR_DIAG_SW, diag_sw); if (bt_sleep && (lna_ctrl == 2)) { REG_SET_BIT(ah, AR_BTCOEX_RC, 0x1); REG_CLR_BIT(ah, AR_BTCOEX_RC, 0x1); udelay(50); } }
void emac_enable_clk(bool enable) { if (enable == true) { REG_SET_BIT(EMAC_CLK_EN_REG, EMAC_CLK_EN); } else { REG_CLR_BIT(EMAC_CLK_EN_REG, EMAC_CLK_EN); } }
void ath9k_hw_startpcureceive(struct ath_hw *ah, bool is_scanning) { ath9k_enable_mib_counters(ah); ath9k_ani_reset(ah, is_scanning); REG_CLR_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)); }
void SystemClass::setCpuFrequency(CpuFrequency freq) { if (freq == eCF_160MHz) REG_SET_BIT(0x3ff00014, BIT(0)); else REG_CLR_BIT(0x3ff00014, BIT(0)); ets_update_cpu_frequency(freq); }
void IRAM_ATTR pm_off(void) { DEBUG ("%s\n", __func__); /* suspend UARTs */ for (int i = 0; i < 3; ++i) { REG_SET_BIT(UART_FLOW_CONF_REG(i), UART_FORCE_XOFF); uart_tx_wait_idle(i); } /* set all power down flags */ uint32_t pd_flags = RTC_SLEEP_PD_DIG | RTC_SLEEP_PD_RTC_PERIPH | RTC_SLEEP_PD_RTC_SLOW_MEM | RTC_SLEEP_PD_RTC_FAST_MEM | RTC_SLEEP_PD_RTC_MEM_FOLLOW_CPU | RTC_SLEEP_PD_VDDSDIO; rtc_sleep_config_t config = RTC_SLEEP_CONFIG_DEFAULT(pd_flags); config.wifi_pd_en = 1; config.rom_mem_pd_en = 1; config.lslp_meminf_pd = 1; /* Save current frequency and switch to XTAL */ rtc_cpu_freq_t cpu_freq = rtc_clk_cpu_freq_get(); rtc_clk_cpu_freq_set(RTC_CPU_FREQ_XTAL); /* set deep sleep duration to forever */ rtc_sleep_set_wakeup_time(rtc_time_get() + ~0x0UL); /* configure deep sleep */ rtc_sleep_init(config); rtc_sleep_start(RTC_TIMER_TRIG_EN, 0); /* Restore CPU frequency */ rtc_clk_cpu_freq_set(cpu_freq); /* resume UARTs */ for (int i = 0; i < 3; ++i) { REG_CLR_BIT(UART_FLOW_CONF_REG(i), UART_FORCE_XOFF); REG_SET_BIT(UART_FLOW_CONF_REG(i), UART_FORCE_XON); REG_CLR_BIT(UART_FLOW_CONF_REG(i), UART_FORCE_XON); } }
void esp_mpi_release_hardware( void ) { REG_SET_BIT(DPORT_RSA_PD_CTRL_REG, DPORT_RSA_PD); /* don't reset digital signature unit, as this resets AES also */ REG_SET_BIT(DPORT_PERI_RST_EN_REG, DPORT_PERI_EN_RSA); REG_CLR_BIT(DPORT_PERI_CLK_EN_REG, DPORT_PERI_EN_RSA); _lock_release(&mpi_lock); }
void esp_mpi_acquire_hardware( void ) { /* newlib locks lazy initialize on ESP-IDF */ _lock_acquire(&mpi_lock); REG_SET_BIT(DPORT_PERI_CLK_EN_REG, DPORT_PERI_EN_RSA); /* also clear reset on digital signature, otherwise RSA is held in reset */ REG_CLR_BIT(DPORT_PERI_RST_EN_REG, DPORT_PERI_EN_RSA | DPORT_PERI_EN_DIGITAL_SIGNATURE); REG_CLR_BIT(DPORT_RSA_PD_CTRL_REG, DPORT_RSA_PD); while(REG_READ(RSA_CLEAN_REG) != 1); // Note: from enabling RSA clock to here takes about 1.3us #ifdef CONFIG_MBEDTLS_MPI_USE_INTERRUPT rsa_isr_initialise(); #endif }
int ar9003_mci_end_reset(struct ath_hw *ah, struct ath9k_channel *chan, struct ath9k_hw_cal_data *caldata) { struct ath9k_hw_mci *mci_hw = &ah->btcoex_hw.mci; if (!mci_hw->ready) return 0; if (!IS_CHAN_2GHZ(chan) || (mci_hw->bt_state != MCI_BT_SLEEP)) goto exit; if (!ar9003_mci_check_int(ah, AR_MCI_INTERRUPT_RX_MSG_REMOTE_RESET) && !ar9003_mci_check_int(ah, AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE)) goto exit; /* * BT is sleeping. Check if BT wakes up during * WLAN calibration. If BT wakes up during * WLAN calibration, need to go through all * message exchanges again and recal. */ REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_RAW, (AR_MCI_INTERRUPT_RX_MSG_REMOTE_RESET | AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE)); ar9003_mci_remote_reset(ah, true); ar9003_mci_send_sys_waking(ah, true); udelay(1); if (IS_CHAN_2GHZ(chan)) ar9003_mci_send_lna_transfer(ah, true); mci_hw->bt_state = MCI_BT_AWAKE; REG_CLR_BIT(ah, AR_PHY_TIMING4, 1 << AR_PHY_TIMING_CONTROL4_DO_GAIN_DC_IQ_CAL_SHIFT); if (caldata) { caldata->done_txiqcal_once = false; caldata->done_txclcal_once = false; caldata->rtt_done = false; } if (!ath9k_hw_init_cal(ah, chan)) return -EIO; REG_SET_BIT(ah, AR_PHY_TIMING4, 1 << AR_PHY_TIMING_CONTROL4_DO_GAIN_DC_IQ_CAL_SHIFT); exit: ar9003_mci_enable_interrupt(ah); return 0; }
s32 timer_hw_stop_timer(u32 timer_no) { s32 ret = ETOS_INVALID_PARAM; switch (timer_no) { case 0: REG_CLR_BIT(TCON, TCON_TIMER0_START_BIT); ret = ETOS_RET_OK; break; case 1: case 2: case 3: case 4: REG_CLR_BIT(TCON, TCON_TIMERx_START_BIT(timer_no)); ret = ETOS_RET_OK; break; default: break; } return ret; }
// Lua: setcpufreq(mhz) // mhz is either CPU80MHZ od CPU160MHZ static int node_setcpufreq(lua_State* L) { // http://www.esp8266.com/viewtopic.php?f=21&t=1369 uint32_t new_freq = luaL_checkinteger(L, 1); if (new_freq == CPU160MHZ){ REG_SET_BIT(0x3ff00014, BIT(0)); os_update_cpu_frequency(CPU160MHZ); } else { REG_CLR_BIT(0x3ff00014, BIT(0)); os_update_cpu_frequency(CPU80MHZ); } new_freq = ets_get_cpu_frequency(); lua_pushinteger(L, new_freq); return 1; }
s32 timer_hw_start_timer(u32 timer_no) { s32 ret = ETOS_INVALID_PARAM; switch (timer_no) { case 0: ret = ETOS_NOT_SUPPORT; break; case 1: ret = ETOS_NOT_SUPPORT; break; case 2: ret = ETOS_NOT_SUPPORT; break; case 3: ret = ETOS_NOT_SUPPORT; break; case 4: REG_SET_BIT(TCON, TCON_TIMERx_MANUAL_UPDATE_BIT(4)); REG_CLR_BIT(TCON, TCON_TIMERx_OUTPUT_INVERTER_BIT(4)); ret = board_interrupt_register_intr_routine(INT_TIMER4_NO, module_timer_isr_idic, (void *)timer_no); ret += interrupt_hw_clear_intr(INT_TIMER4_NO); ret += interrupt_hw_unmask_intr(INT_TIMER4_NO); REG_SET_BIT(TCON, TCON_TIMERx_START_BIT(4)); REG_CLR_BIT(TCON, TCON_TIMERx_MANUAL_UPDATE_BIT(4)); REG_SET_BIT(TCON, TCON_TIMER4_AUTO_RELOAD_BIT); break; default: break; } return ret; }
static void set_txpower(void) { if (!fem_config.started) { return; } /* CHL is always 0 on RX */ REG_CLR_BIT(RFCU_POWER, RF_PORT_EN_BLE_REG, RF_PORT4_RX); REG_CLR_BIT(RFCU_POWER, RF_PORT_EN_FTDF_REG, RF_PORT4_RX); if (fem_config.tx_power_ble) { REG_SET_BIT(RFCU_POWER, RF_PORT_EN_BLE_REG, RF_PORT4_TX); } if (fem_config.tx_power_ftdf) { REG_SET_BIT(RFCU_POWER, RF_PORT_EN_FTDF_REG, RF_PORT4_TX); } if (fem_config.tx_power_ble || fem_config.tx_power_ftdf) { /* TX Power high. Configure GPIO for DCF. Enable DCF on TX. */ hw_gpio_set_pin_function(dg_configFEM_SKY66112_11_CHL_PORT, dg_configFEM_SKY66112_11_CHL_PIN, HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_PORT4_DCF); } else { /* TX Power low. Stop DCF, set GPIO to low */ hw_gpio_configure_pin(dg_configFEM_SKY66112_11_CHL_PORT, dg_configFEM_SKY66112_11_CHL_PIN, HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_GPIO, false); } }
void ath9k_hw_start_nfcal(struct ath_hw *ah, bool update) { if (ah->caldata) ah->caldata->nfcal_pending = true; REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_ENABLE_NF); if (update) REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NO_UPDATE_NF); else REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NO_UPDATE_NF); REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF); }
void ath9k_hw_start_nfcal(struct ath_hw *ah, bool update) { if (ah->caldata) set_bit(NFCAL_PENDING, &ah->caldata->cal_flags); REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_ENABLE_NF); if (update) REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NO_UPDATE_NF); else REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NO_UPDATE_NF); REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF); }
static bool ar9285_clc(struct ath_hw *ah, struct ath9k_channel *chan) { REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE); if (IS_CHAN_HT20(chan)) { REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_PARALLEL_CAL_ENABLE); REG_SET_BIT(ah, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN); REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL); REG_CLR_BIT(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_CAL_ENABLE); REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL); if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, 0, AH_WAIT_TIMEOUT)) { DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, "offset " "calibration failed to complete in " "1ms; noisy ??\n"); return false; } REG_CLR_BIT(ah, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN); REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_PARALLEL_CAL_ENABLE); REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE); } REG_CLR_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC); REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL); REG_SET_BIT(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_CAL_ENABLE); REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL); if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, 0, AH_WAIT_TIMEOUT)) { DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, "offset calibration " "failed to complete in 1ms; noisy ??\n"); return false; } REG_SET_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC); REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE); REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL); return true; }
void hw_aes_hash_store_keys(hw_aes_key_size key_size, const uint8 *aes_keys, hw_aes_hash_key_exp_t key_exp) { volatile uint32 *kmem_ptr = &AES_HASH->CRYPTO_KEYS_START; unsigned int key_wrds; if (key_exp == HW_AES_DO_NOT_PERFORM_KEY_EXPANSION) { /* Key expansion is provided by the software */ REG_CLR_BIT(AES_HASH, CRYPTO_CTRL_REG, CRYPTO_AES_KEXP); key_wrds = (key_size == HW_AES_256) ? 60 : (key_size == HW_AES_192) ? 52 : 44; } else { /* Key expansion needs to be performed by the engine */ REG_SET_BIT(AES_HASH, CRYPTO_CTRL_REG, CRYPTO_AES_KEXP); key_wrds = (key_size == HW_AES_256) ? 8 : (key_size == HW_AES_192) ? 6 : 4; } do { *(kmem_ptr++) = hw_aes_hash_construct_word(aes_keys); aes_keys += 4; key_wrds--; } while (key_wrds > 0); }