Exemple #1
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const struct reg_script pch_early_init_script[] = {
	/* Setup southbridge BARs */
	REG_PCI_WRITE32(RCBA, RCBA_BASE_ADDRESS | 1),
	REG_PCI_WRITE32(PMBASE, ACPI_BASE_ADDRESS | 1),
	REG_PCI_WRITE8(ACPI_CNTL, ACPI_EN),
	REG_PCI_WRITE32(GPIO_BASE, GPIO_BASE_ADDRESS | 1),
	REG_PCI_WRITE8(GPIO_CNTL, GPIO_EN),

	/* Set COM1/COM2 decode range */
	REG_PCI_WRITE16(LPC_IO_DEC, 0x0010),
	/* Enable legacy decode ranges */
	REG_PCI_WRITE16(LPC_EN, CNF1_LPC_EN | CNF2_LPC_EN | GAMEL_LPC_EN |
			COMA_LPC_EN | KBC_LPC_EN | MC_LPC_EN),

	/* Enable IOAPIC */
	REG_MMIO_WRITE16(RCBA_BASE_ADDRESS + OIC, 0x0100),
	/* Read back for posted write */
	REG_MMIO_READ16(RCBA_BASE_ADDRESS + OIC),

	/* Set HPET address and enable it */
	REG_MMIO_RMW32(RCBA_BASE_ADDRESS + HPTC, ~3, (1 << 7)),
	/* Read back for posted write */
	REG_MMIO_READ32(RCBA_BASE_ADDRESS + HPTC),
	/* Enable HPET to start counter */
	REG_MMIO_OR32(HPET_BASE_ADDRESS + 0x10, (1 << 0)),

	/* Disable reset */
	REG_MMIO_OR32(RCBA_BASE_ADDRESS + GCS, (1 << 5)),
	/* TCO timer halt */
	REG_IO_OR16(ACPI_BASE_ADDRESS + TCO1_CNT, TCO_TMR_HLT),
Exemple #2
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	REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x6020, 1 << 0),	/* UMA GFX */
	REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x63fc, 1 << 0),	/* VTDTRK */
	REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x6800, 1 << 31),
	REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x7000, 1 << 31),
	REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x77fc, 1 << 0),
	REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x50fc, 0x8f),
	REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x7ffc, 1 << 0),
	REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x5880, 1 << 5),
	REG_MMIO_WRITE8(MCH_BASE_ADDRESS + 0x50fc, 0x8f),	/* MC */

	REG_SCRIPT_END
};

const struct reg_script pch_finalize_script[] = {
	/* Set SPI opcode menu */
	REG_MMIO_WRITE16(RCBA_BASE_ADDRESS + SPIBAR_OFFSET + SPIBAR_PREOP,
			 SPI_OPPREFIX),
	REG_MMIO_WRITE16(RCBA_BASE_ADDRESS + SPIBAR_OFFSET + SPIBAR_OPTYPE,
			 SPI_OPTYPE),
	REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + SPIBAR_OFFSET +
			 SPIBAR_OPMENU_LOWER, SPI_OPMENU_LOWER),
	REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + SPIBAR_OFFSET +
			 SPIBAR_OPMENU_UPPER, SPI_OPMENU_UPPER),

	/* Lock SPIBAR */
	REG_MMIO_OR32(RCBA_BASE_ADDRESS + SPIBAR_OFFSET + SPIBAR_HSFS,
		      SPIBAR_HSFS_FLOCKDN),

	/* TC Lockdown */
	REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x0050, (1 << 31)),

	/* BIOS Interface Lockdown */