REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x1114, (1 << 15) | (1 << 14)),
/* Setup SERIRQ, enable continuous mode */
REG_PCI_OR8(SERIRQ_CNTL, (1 << 7) | (1 << 6)),
#if !CONFIG_SERIRQ_CONTINUOUS_MODE
REG_PCI_RMW8(SERIRQ_CNTL, ~(1 << 6), 0),
#endif
REG_SCRIPT_END
};
/* Magic register settings for power management */
static const struct reg_script pch_pm_init_script[] = {
REG_PCI_WRITE8(0xa9, 0x46),
REG_MMIO_RMW32(RCBA_BASE_ADDRESS + 0x232c, ~1, 0),
REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x1100, 0x0000c13f),
REG_MMIO_RMW32(RCBA_BASE_ADDRESS + 0x2320, ~0x60, 0x10),
REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3314, 0x00012fff),
REG_MMIO_RMW32(RCBA_BASE_ADDRESS + 0x3318, ~0x000f0330, 0x0dcf0400),
REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3324, 0x04000000),
REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3368, 0x00041400),
REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3388, 0x3f8ddbff),
REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x33ac, 0x00007001),
REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x33b0, 0x00181900),
REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x33c0, 0x00060A00),
REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x33d0, 0x06200840),
REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3a28, 0x01010101),
REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3a2c, 0x040c0404),
REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3a9c, 0x9000000a),
REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x2b1c, 0x03808033),
REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x2b34, 0x80000009),
REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3348, 0x022ddfff),
REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x334c, 0x00000001),
#include "chip.h"
static const struct reg_script ehci_init_script[] = {
/* Enable S0 PLL shutdown
* D29:F0:7A[12,10,7,6,4,3,2,1]=11111111b */
REG_PCI_OR16(0x7a, 0x14de),
/* Enable SB local clock gating
* D29:F0:7C[14,3,2]=111b (14 set in clock gating step) */
REG_PCI_OR32(0x7c, 0x0000000c),
REG_PCI_OR32(0x8c, 0x00000001),
/* Enable dynamic clock gating 0x4001=0xCE */
REG_IOSF_RMW(IOSF_PORT_USBPHY, 0x4001, 0xFFFFFF00, 0xCE),
/* Magic RCBA register set sequence */
/* RCBA + 0x200=0x1 */
REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x200, 0x00000001),
/* RCBA + 0x204=0x2 */
REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x204, 0x00000002),
/* RCBA + 0x208=0x0 */
REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x208, 0x00000000),
/* RCBA + 0x240[4,3,2,1,0]=00000b */
REG_MMIO_RMW32(RCBA_BASE_ADDRESS + 0x240, ~0x0000001f, 0),
/* RCBA + 0x318[9,8,6,5,4,3,2,1,0]=000000111b */
REG_MMIO_RMW32(RCBA_BASE_ADDRESS + 0x318, ~0x00000378, 0x00000007),
/* RCBA + 0x31c[3,2,1,0]=0011b */
REG_MMIO_RMW32(RCBA_BASE_ADDRESS + 0x31c, ~0x0000000c, 0x00000003),
REG_SCRIPT_END
};
static const struct reg_script ehci_clock_gating_script[] = {
/* Enable SB local clock gating */
REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x77fc, 1 << 0),
REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x50fc, 0x8f),
REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x7ffc, 1 << 0),
REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x5880, 1 << 5),
REG_MMIO_WRITE8(MCH_BASE_ADDRESS + 0x50fc, 0x8f), /* MC */
REG_SCRIPT_END
};
const struct reg_script pch_finalize_script[] = {
/* Set SPI opcode menu */
REG_MMIO_WRITE16(RCBA_BASE_ADDRESS + SPIBAR_OFFSET + SPIBAR_PREOP,
SPI_OPPREFIX),
REG_MMIO_WRITE16(RCBA_BASE_ADDRESS + SPIBAR_OFFSET + SPIBAR_OPTYPE,
SPI_OPTYPE),
REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + SPIBAR_OFFSET +
SPIBAR_OPMENU_LOWER, SPI_OPMENU_LOWER),
REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + SPIBAR_OFFSET +
SPIBAR_OPMENU_UPPER, SPI_OPMENU_UPPER),
/* Lock SPIBAR */
REG_MMIO_OR32(RCBA_BASE_ADDRESS + SPIBAR_OFFSET + SPIBAR_HSFS,
SPIBAR_HSFS_FLOCKDN),
/* TC Lockdown */
REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x0050, (1 << 31)),
/* BIOS Interface Lockdown */
REG_MMIO_OR32(RCBA_BASE_ADDRESS + GCS, (1 << 0)),
/* Function Disable SUS Well Lockdown */
REG_MMIO_OR8(RCBA_BASE_ADDRESS + FDSW, (1 << 7)),
const struct reg_script pch_interrupt_init_script[] = {
/*
* GFX INTA -> PIRQA (MSI)
* D28IP_P1IP PCIE INTA -> PIRQA
* D29IP_E1P EHCI INTA -> PIRQD
* D20IP_XHCI XHCI INTA -> PIRQC (MSI)
* D31IP_SIP SATA INTA -> PIRQF (MSI)
* D31IP_SMIP SMBUS INTB -> PIRQG
* D31IP_TTIP THRT INTC -> PIRQA
* D27IP_ZIP HDA INTA -> PIRQG (MSI)
*/
/* Device interrupt pin register (board specific) */
REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D31IP,
(INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
(INTB << D31IP_SMIP) | (INTA << D31IP_SIP)),
REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D29IP, (INTA << D29IP_E1P)),
REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D28IP,
(INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) |
(INTB << D28IP_P4IP)),
REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D27IP, (INTA << D27IP_ZIP)),
REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D26IP, (INTA << D26IP_E2P)),
REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D22IP, (NOINT << D22IP_MEI1IP)),
REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D20IP, (INTA << D20IP_XHCI)),
/* Device interrupt route registers */
REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D31IR, /* LPC */
DIR_ROUTE(PIRQG, PIRQC, PIRQB, PIRQA)),
REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D29IR, /* EHCI */
DIR_ROUTE(PIRQD, PIRQD, PIRQD, PIRQD)),
const struct reg_script uart_init[] = {
/* Set MMIO BAR */
REG_PCI_WRITE32(PCI_BASE_ADDRESS_0, CONFIG_TTYS0_BASE),
/* Enable Memory access and Bus Master */
REG_PCI_OR32(PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER),
/* Initialize LTR */
REG_MMIO_RMW32(CONFIG_TTYS0_BASE + SIO_REG_PPR_GEN,
~SIO_REG_PPR_GEN_LTR_MODE_MASK, 0),
REG_MMIO_RMW32(CONFIG_TTYS0_BASE + SIO_REG_PPR_RST,
~(SIO_REG_PPR_RST_ASSERT), 0),
/* Take UART out of reset */
REG_MMIO_OR32(CONFIG_TTYS0_BASE + SIO_REG_PPR_RST,
SIO_REG_PPR_RST_ASSERT),
/* Set M and N divisor inputs and enable clock */
REG_MMIO_WRITE32(CONFIG_TTYS0_BASE + SIO_REG_PPR_CLOCK,
SIO_REG_PPR_CLOCK_EN | SIO_REG_PPR_CLOCK_UPDATE |
(SIO_REG_PPR_CLOCK_N_DIV << 16) |
(SIO_REG_PPR_CLOCK_M_DIV << 1)),
REG_SCRIPT_END
};
void pch_uart_init(void)
{
/* Program IOBP CB000154h[12,9:8,4:0] = 1001100011111b */
u32 gpiodf = 0x131f;
#if defined(__SIMPLE_DEVICE__)
pci_devfn_t dev;
#else
struct device *dev;
#endif
/* Put UART in byte access mode for 16550 compatibility */
