int main(void) { switch_on(); DDRB = MASK_MERGE(~0 * DD_INPUT, 1 << OC0B_BIT | 1 << 2, ~0 * DD_OUTPUT); /* Unused pins pulled up to avoid floating inputs using excess power. Input pins floating. */ REG_MOD(PORTB, ~(1 << OC0B_BIT | 1 << 2), MASK_MERGE(~0 * PORT_PULLUP, 1 << AIN0_BIT | 1 << BAT_BIT, ~0 * PORT_FLOAT)); DIDR0 = ~0; BIT_MOD(ADCSRA, ADEN, 0); REG_MOD(ADMUX, MUX_MASK << MUX0, BAT_ADC << MUX0); BIT_MOD(ADCSRB, ACME, 1); ACSR = 0 << ACD | 0 << ACBG | ACIS_TOGGLE << ACIS0; BIT_MOD(ACSR, ACI, 1); WDTCR = 1 << WDTIE | WDP_16MS; BIT_MOD(ACSR, ACIE, 1); sei(); while(1) { sleep_mode(); } }
static void dss_dpll_power_enable(struct dss_video_pll *vpll) { REG_MOD(vpll->clkctrl_base, 2, 31, 30); /* PLL_POWER_ON_ALL */ /* * DRA7x PLL CTRL's PLL_PWR_STATUS seems to always return 0, * so we have to use fixed delay here. */ msleep(1); }
static void dss_dpll_power_disable(struct dss_video_pll *vpll) { REG_MOD(vpll->clkctrl_base, 0, 31, 30); /* PLL_POWER_OFF */ }
static void dss_dpll_disable_scp_clk(struct dss_video_pll *vpll) { REG_MOD(vpll->clkctrl_base, 0, 14, 14); /* CIO_CLK_ICG */ }