void hw_aes_hash_restart(const uint32 sourceAddress, const uint32 dataSize,
const bool moreDataToCome)
{
hw_aes_hash_cfg_dma((const uint8 *)sourceAddress, NULL, (unsigned int)dataSize);
REG_SETF(AES_HASH, CRYPTO_CTRL_REG, CRYPTO_MORE_IN, moreDataToCome);
hw_aes_hash_start();
}
static void reboot(void)
{
/*
* Reset platform
*/
__disable_irq();
REG_SETF(CRG_TOP, SYS_CTRL_REG, SW_RESET, 1);
}
int hw_fem_set_bias(uint16_t voltage)
{
uint16_t value;
if (voltage < 1200 || voltage > 1975)
{
return -1;
}
value = (voltage - 1200) / 27.5;
#ifdef dg_configFEM_SKY66112_11_FEM_BIAS_V18P
REG_SETF(DCDC, DCDC_V18P_0_REG, DCDC_V18P_VOLTAGE, value);
return 0;
#elif defined(dg_configFEM_SKY66112_11_FEM_BIAS_V18)
REG_SETF(DCDC, DCDC_V18_0_REG, DCDC_V18_VOLTAGE, value);
return 0;
#else
return -2;
#endif
}
int hw_fem_set_bias2(uint16_t voltage)
{
uint16_t value;
if (voltage < 1200 || voltage > 1975)
{
return -1;
}
value = (voltage - 1200) / 27.5;
// /* Value is actually one lower than computed */
// if (value > 0)
// value--;
#ifdef dg_configFEM_SKY66112_11_FEM_BIAS2_V18P
REG_SETF(DCDC, DCDC_V18P_0_REG, DCDC_V18P_VOLTAGE, value);
#elif defined(dg_configFEM_SKY66112_11_FEM_BIAS2_V18)
REG_SETF(DCDC, DCDC_V18_0_REG, DCDC_V18_VOLTAGE, value);
#else
return -2;
#endif
return 0;
}
static __RETAINED_CODE void configure_cache(void)
{
bool flush = false;
GLOBAL_INT_DISABLE();
if (dg_configCACHEABLE_QSPI_AREA_LEN != -1)
{
uint32_t cache_len;
/* dg_configCACHEABLE_QSPI_AREA_LEN must be 64KB-aligned */
ASSERT_WARNING((dg_configCACHEABLE_QSPI_AREA_LEN & 0xFFFF) == 0);
/*
* dg_configCACHEABLE_QSPI_AREA_LEN shouldn't set any bits that do not fit in
* CACHE_CTRL2_REG.CACHE_LEN (9 bits wide) after shifting out the lower 16 bits
*/
ASSERT_WARNING((dg_configCACHEABLE_QSPI_AREA_LEN & 0x1FF0000)
== dg_configCACHEABLE_QSPI_AREA_LEN);
/*
* set cacheable area
*
* setting CACHE_CTRL2_REG.CACHE_LEN to N, actually sets the size of the cacheable
* area to (N + 1) * 64KB
* special cases:
* N == 0 --> no caching
* N == 1 --> 128KB are cached, i.e. no way to cache only 64KB
*/
cache_len = dg_configCACHEABLE_QSPI_AREA_LEN >> 16;
/* cannot cache only 64KB! */
ASSERT_WARNING(cache_len != 1);
if (cache_len > 1)
{
cache_len--;
}
REG_SETF(CACHE, CACHE_CTRL2_REG, CACHE_LEN, cache_len);
}
void hw_fem_start(void)
{
GLOBAL_INT_DISABLE();
fem_config.started = true;
uint8_t set_delay;
uint8_t reset_delay;
uint16_t rf_port_en;
/******************************************************
* Setup GPIOs
*/
/* CSD GPIO Config */
#if defined(dg_configFEM_SKY66112_11_CSD_PORT) && defined(dg_configFEM_SKY66112_11_CSD_PIN)
# if dg_configFEM_SKY66112_11_CSD_USE_DCF == 0
/* Manually set CSD (Enable FEM) */
hw_gpio_configure_pin(dg_configFEM_SKY66112_11_CSD_PORT, dg_configFEM_SKY66112_11_CSD_PIN,
HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_GPIO, true);
# else
/* Use DCF for CSD */
hw_gpio_set_pin_function(dg_configFEM_SKY66112_11_CSD_PORT, dg_configFEM_SKY66112_11_CSD_PIN,
HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_PORT2_DCF);
# endif
#endif
/* Timer 27 GPIO (DCF Port 0). Used for TX EN */
hw_gpio_set_pin_function(dg_configFEM_SKY66112_11_CTX_PORT, dg_configFEM_SKY66112_11_CTX_PIN,
HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_PORT0_DCF);
/* Timer 28 (DCF Port 1). Used for RX EN */
hw_gpio_set_pin_function(dg_configFEM_SKY66112_11_CRX_PORT, dg_configFEM_SKY66112_11_CRX_PIN,
HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_PORT1_DCF);
/* Antenna selection */
#if defined(dg_configFEM_SKY66112_11_ANTSEL_PORT) && defined(dg_configFEM_SKY66112_11_ANTSEL_PIN)
hw_gpio_configure_pin(dg_configFEM_SKY66112_11_ANTSEL_PORT, dg_configFEM_SKY66112_11_ANTSEL_PIN,
HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_GPIO, fem_config.antsel);
#endif
/******************************************************
* Setup RF_ANT_TRIM GPIOs
*/
/* RF_ANT_TRIM_0 Config */
#if defined(dg_configFEM_SKY66112_11_ANT_TRIM_0_PORT) && defined(dg_configFEM_SKY66112_11_ANT_TRIM_0_PIN)
hw_gpio_set_pin_function(dg_configFEM_SKY66112_11_ANT_TRIM_0_PORT, dg_configFEM_SKY66112_11_ANT_TRIM_0_PIN,
HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_RF_ANT_TRIM0);
#endif
/* RF_ANT_TRIM_1 Config */
#if defined(dg_configFEM_SKY66112_11_ANT_TRIM_1_PORT) && defined(dg_configFEM_SKY66112_11_ANT_TRIM_1_PIN)
hw_gpio_set_pin_function(dg_configFEM_SKY66112_11_ANT_TRIM_1_PORT, dg_configFEM_SKY66112_11_ANT_TRIM_1_PIN,
HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_RF_ANT_TRIM1);
#endif
/* RF_ANT_TRIM_2 Config */
#if defined(dg_configFEM_SKY66112_11_ANT_TRIM_2_PORT) && defined(dg_configFEM_SKY66112_11_ANT_TRIM_2_PIN)
hw_gpio_set_pin_function(dg_configFEM_SKY66112_11_ANT_TRIM_2_PORT, dg_configFEM_SKY66112_11_ANT_TRIM_2_PIN,
HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_RF_ANT_TRIM2);
#endif
/******************************************************
* Setup DCFs
*/
/* assign values to the timer registers for CTX/CRX (in usec) */
REG_SETF(RFCU_POWER, RF_CNTRL_TIMER_27_REG, SET_OFFSET, dg_configFEM_SKY66112_11_TXSET_DCF);
REG_SETF(RFCU_POWER, RF_CNTRL_TIMER_27_REG, RESET_OFFSET, dg_configFEM_SKY66112_11_TXRESET_DCF);
REG_SETF(RFCU_POWER, RF_CNTRL_TIMER_28_REG, SET_OFFSET, dg_configFEM_SKY66112_11_RXSET_DCF);
REG_SETF(RFCU_POWER, RF_CNTRL_TIMER_28_REG, RESET_OFFSET, dg_configFEM_SKY66112_11_RXRESET_DCF);
rf_port_en = 0x6; /* Start with Port 0: TX, Port 1: RX */
/* Compute set/reset delays to use for CSD, CPS, CHL DCFs: For setting delay,
* smaller of TXSET, RXSET, and for resetting delay, larger of TXSET, RXSET
*/
#if dg_configFEM_SKY66112_11_RXSET_DCF > dg_configFEM_SKY66112_11_TXSET_DCF
set_delay = dg_configFEM_SKY66112_11_TXSET_DCF;
#else
set_delay = dg_configFEM_SKY66112_11_RXSET_DCF;
#endif
#if dg_configFEM_SKY66112_11_RXRESET_DCF > dg_configFEM_SKY66112_11_TXRESET_DCF
reset_delay = dg_configFEM_SKY66112_11_RXRESET_DCF;
#else
reset_delay = dg_configFEM_SKY66112_11_TXRESET_DCF;
#endif
/* CSD DCF (if enabled) configuration */
#if defined(dg_configFEM_SKY66112_11_CSD_PORT) && defined(dg_configFEM_SKY66112_11_CSD_PIN)
# if dg_configFEM_SKY66112_11_CSD_USE_DCF != 0
REG_SETF(RFCU_POWER, RF_CNTRL_TIMER_29_REG, SET_OFFSET, set_delay);
REG_SETF(RFCU_POWER, RF_CNTRL_TIMER_29_REG, RESET_OFFSET, reset_delay);
/* enable DCF Signals for Port 2 (CSD) for both rx/tx */
rf_port_en |= 0x30;
# endif /* dg_configFEM_SKY66112_11_CSD_USE_DCF != 0 */
#endif
/* Set bypass (CPS) DCF timers (but don't enable yet) */
REG_SETF(RFCU_POWER, RF_CNTRL_TIMER_30_REG, SET_OFFSET, set_delay);
REG_SETF(RFCU_POWER, RF_CNTRL_TIMER_30_REG, RESET_OFFSET, reset_delay);
/* Set TX Power (CHL) DCF timers (but don't enable yet) */
REG_SETF(RFCU_POWER, RF_CNTRL_TIMER_31_REG, SET_OFFSET, dg_configFEM_SKY66112_11_TXSET_DCF);
REG_SETF(RFCU_POWER, RF_CNTRL_TIMER_31_REG, RESET_OFFSET, dg_configFEM_SKY66112_11_TXRESET_DCF);
/* Enable DCFs */
#if dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A
RFCU_POWER->RF_PORT_EN_REG = rf_port_en;
hw_fem_set_txpower(fem_config.tx_power);
#else
RFCU_POWER->RF_PORT_EN_BLE_REG = rf_port_en;
RFCU_POWER->RF_PORT_EN_FTDF_REG = rf_port_en;
set_txpower();
#endif
set_bypass();
GLOBAL_INT_RESTORE();
}
/**
* Apply trim values from OTP.
*
* @brief Writes the trim values located in the OTP to the corresponding system registers.
*
* @param[out] tcs_array The valid <address, value> pairs are placed in this buffer.
* @param[out] valid_entries The number of valid pairs.
*
* @return True if at least one trim value has been applied, else false.
*
*/
static bool apply_trim_values_from_otp(uint32_t *tcs_array, uint32_t *valid_entries)
{
uint32_t address;
uint32_t inverted_address;
uint32_t value;
uint32_t inverted_value;
uint32_t *p;
int i;
int index = 0;
int vdd = 0;
int retries = 0;
bool forward_reading = true;
bool res = false;
p = (uint32_t *)(OTP_HEADER_BASE_ADDR_IN_OTP + TCS_SECTION_OFFSET);
for (i = 0; i < TCS_SECTION_LENGTH; i++)
{
do
{
address = *p;
p++;
inverted_address = *p;
p++;
value = *p;
p++;
inverted_value = *p;
p++;
if ((address == 0) && (value == 0))
{
break;
}
// Check validity
if ((address != ~inverted_address) || (value != ~inverted_value))
{
// Change LDO core voltage level and retry
vdd++;
vdd &= 0x3;
REG_SETF(CRG_TOP, LDO_CTRL1_REG, LDO_CORE_SETVDD, vdd);
// Wait for the voltage to settle...
SysTick->CTRL = 0;
SysTick->LOAD = 500; // 500 * (62.5 * 4) = 125usec
SysTick->VAL = 0;
SysTick->CTRL = 0x5; // Start using system clock
while ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0) {}
// Adjust the read pointer
p -= 4;
}
retries++;
if (retries == 32)
{
// Unrecoverable problem! Assert in development mode
ASSERT_WARNING(0);
// Unrecoverable problem! Issue a HW reset.
hw_cpm_reset_system();
}
}
while ((address != ~inverted_address) || (value != ~inverted_value));
retries = 0;
// Read the complete TCS area but skip empty entries.
if ((address == 0) && (value == 0))
{
if ((BLACK_ORCA_TARGET_IC >= BLACK_ORCA_IC_VERSION(A, E))
|| ((dg_configUSE_AUTO_CHIP_DETECTION == 1)
&& (CHIP_IS_AE || CHIP_IS_BA)))
{
if (!forward_reading)
{
break;
}
forward_reading = false;
p = (uint32_t *)(OTP_HEADER_BASE_ADDR_IN_OTP + TCS_SECTION_OFFSET);
p += (TCS_SECTION_LENGTH - 1) * 4;
}
else
{
(void)forward_reading;
}
continue;
}
if (!forward_reading)
{
p -= 8;
}
sys_tcs_store_pair(address, value);
tcs_array[(index * 2) + 0] = address;
tcs_array[(index * 2) + 1] = value;
*valid_entries = index + 1;
index++;
res = true;
}
return res;
}
