void dce_crtc_switch_to_clk_src(struct dce_hwseq *hws,
struct clock_source *clk_src,
unsigned int tg_inst)
{
if (clk_src->id == CLOCK_SOURCE_ID_DP_DTO || clk_src->dp_clk_src) {
REG_UPDATE(PIXEL_RATE_CNTL[tg_inst],
DP_DTO0_ENABLE, 1);
} else if (clk_src->id >= CLOCK_SOURCE_COMBO_PHY_PLL0) {
uint32_t rate_source = clk_src->id - CLOCK_SOURCE_COMBO_PHY_PLL0;
REG_UPDATE_2(PHYPLL_PIXEL_RATE_CNTL[tg_inst],
PHYPLL_PIXEL_RATE_SOURCE, rate_source,
PIXEL_RATE_PLL_SOURCE, 0);
REG_UPDATE(PIXEL_RATE_CNTL[tg_inst],
DP_DTO0_ENABLE, 0);
} else if (clk_src->id <= CLOCK_SOURCE_ID_PLL2) {
uint32_t rate_source = clk_src->id - CLOCK_SOURCE_ID_PLL0;
REG_UPDATE_2(PIXEL_RATE_CNTL[tg_inst],
PIXEL_RATE_SOURCE, rate_source,
DP_DTO0_ENABLE, 0);
if (REG(PHYPLL_PIXEL_RATE_CNTL[tg_inst]))
REG_UPDATE(PHYPLL_PIXEL_RATE_CNTL[tg_inst],
PIXEL_RATE_PLL_SOURCE, 1);
} else {
DC_ERR("Unknown clock source. clk_src id: %d, TG_inst: %d",
clk_src->id, tg_inst);
}
}
void dpp1_set_cursor_attributes(
struct dpp *dpp_base,
const struct dc_cursor_attributes *attr)
{
struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
enum dc_cursor_color_format color_format = attr->color_format;
REG_UPDATE_2(CURSOR0_CONTROL,
CUR0_MODE, color_format,
CUR0_EXPANSION_MODE, 0);
if (color_format == CURSOR_MODE_MONO) {
/* todo: clarify what to program these to */
REG_UPDATE(CURSOR0_COLOR0,
CUR0_COLOR0, 0x00000000);
REG_UPDATE(CURSOR0_COLOR1,
CUR0_COLOR1, 0xFFFFFFFF);
}
/* TODO: Fixed vs float */
REG_UPDATE_3(FORMAT_CONTROL,
CNVC_BYPASS, 0,
FORMAT_CONTROL__ALPHA_EN, 1,
FORMAT_EXPANSION_MODE, 0);
}
static bool setup_scaling_configuration(
struct dce_transform *xfm_dce,
const struct scaler_data *data)
{
REG_SET(SCL_BYPASS_CONTROL, 0, SCL_BYPASS_MODE, 0);
if (data->taps.h_taps + data->taps.v_taps <= 2) {
/* Set bypass */
if (xfm_dce->xfm_mask->SCL_PSCL_EN != 0)
REG_UPDATE_2(SCL_MODE, SCL_MODE, 0, SCL_PSCL_EN, 0);
else
REG_UPDATE(SCL_MODE, SCL_MODE, 0);
return false;
}
REG_SET_2(SCL_TAP_CONTROL, 0,
SCL_H_NUM_OF_TAPS, data->taps.h_taps - 1,
SCL_V_NUM_OF_TAPS, data->taps.v_taps - 1);
if (data->format <= PIXEL_FORMAT_GRPH_END)
REG_UPDATE(SCL_MODE, SCL_MODE, 1);
else
REG_UPDATE(SCL_MODE, SCL_MODE, 2);
if (xfm_dce->xfm_mask->SCL_PSCL_EN != 0)
REG_UPDATE(SCL_MODE, SCL_PSCL_EN, 1);
/* 1 - Replace out of bound pixels with edge */
REG_SET(SCL_CONTROL, 0, SCL_BOUNDARY_MODE, 1);
return true;
}
void hubbub1_update_dchub(
struct hubbub *hubbub,
struct dchub_init_data *dh_data)
{
if (REG(DCHUBBUB_SDPIF_FB_TOP) == 0) {
ASSERT(false);
/*should not come here*/
return;
}
/* TODO: port code from dal2 */
switch (dh_data->fb_mode) {
case FRAME_BUFFER_MODE_ZFB_ONLY:
/*For ZFB case need to put DCHUB FB BASE and TOP upside down to indicate ZFB mode*/
REG_UPDATE(DCHUBBUB_SDPIF_FB_TOP,
SDPIF_FB_TOP, 0);
REG_UPDATE(DCHUBBUB_SDPIF_FB_BASE,
SDPIF_FB_BASE, 0x0FFFF);
REG_UPDATE(DCHUBBUB_SDPIF_AGP_BASE,
SDPIF_AGP_BASE, dh_data->zfb_phys_addr_base >> 22);
REG_UPDATE(DCHUBBUB_SDPIF_AGP_BOT,
SDPIF_AGP_BOT, dh_data->zfb_mc_base_addr >> 22);
REG_UPDATE(DCHUBBUB_SDPIF_AGP_TOP,
SDPIF_AGP_TOP, (dh_data->zfb_mc_base_addr +
dh_data->zfb_size_in_byte - 1) >> 22);
break;
case FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL:
/*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/
REG_UPDATE(DCHUBBUB_SDPIF_AGP_BASE,
SDPIF_AGP_BASE, dh_data->zfb_phys_addr_base >> 22);
REG_UPDATE(DCHUBBUB_SDPIF_AGP_BOT,
SDPIF_AGP_BOT, dh_data->zfb_mc_base_addr >> 22);
REG_UPDATE(DCHUBBUB_SDPIF_AGP_TOP,
SDPIF_AGP_TOP, (dh_data->zfb_mc_base_addr +
dh_data->zfb_size_in_byte - 1) >> 22);
break;
case FRAME_BUFFER_MODE_LOCAL_ONLY:
/*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/
REG_UPDATE(DCHUBBUB_SDPIF_AGP_BASE,
SDPIF_AGP_BASE, 0);
REG_UPDATE(DCHUBBUB_SDPIF_AGP_BOT,
SDPIF_AGP_BOT, 0X03FFFF);
REG_UPDATE(DCHUBBUB_SDPIF_AGP_TOP,
SDPIF_AGP_TOP, 0);
break;
default:
break;
}
dh_data->dchub_initialzied = true;
dh_data->dchub_info_valid = false;
}
static void dce110_se_setup_dp_audio(
struct stream_encoder *enc)
{
struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
/* --- DP Audio packet configurations --- */
/* ATP Configuration */
REG_SET(DP_SEC_AUD_N, 0,
DP_SEC_AUD_N, DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT);
/* Async/auto-calc timestamp mode */
REG_SET(DP_SEC_TIMESTAMP, 0, DP_SEC_TIMESTAMP_MODE,
DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC);
/* --- The following are the registers
* copied from the SetupHDMI --- */
/* AFMT_AUDIO_PACKET_CONTROL */
REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
/* AFMT_AUDIO_PACKET_CONTROL2 */
/* Program the ATP and AIP next */
REG_UPDATE_2(AFMT_AUDIO_PACKET_CONTROL2,
AFMT_AUDIO_LAYOUT_OVRD, 0,
AFMT_60958_OSF_OVRD, 0);
/* AFMT_INFOFRAME_CONTROL0 */
REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
/* AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK */
REG_UPDATE(AFMT_60958_0, AFMT_60958_CS_CLOCK_ACCURACY, 0);
}
static void release_engine(
struct dce_i2c_hw *dce_i2c_hw)
{
bool safe_to_reset;
/* Restore original HW engine speed */
set_speed(dce_i2c_hw, dce_i2c_hw->original_speed);
/* Release I2C */
REG_UPDATE(DC_I2C_ARBITRATION, DC_I2C_SW_DONE_USING_I2C_REG, 1);
/* Reset HW engine */
{
uint32_t i2c_sw_status = 0;
REG_GET(DC_I2C_SW_STATUS, DC_I2C_SW_STATUS, &i2c_sw_status);
/* if used by SW, safe to reset */
safe_to_reset = (i2c_sw_status == 1);
}
if (safe_to_reset)
REG_UPDATE_2(DC_I2C_CONTROL,
DC_I2C_SOFT_RESET, 1,
DC_I2C_SW_STATUS_RESET, 1);
else
REG_UPDATE(DC_I2C_CONTROL, DC_I2C_SW_STATUS_RESET, 1);
/* HW I2c engine - clock gating feature */
if (!dce_i2c_hw->engine_keep_power_up_count)
REG_UPDATE_N(SETUP, 1, FN(SETUP, DC_I2C_DDC1_ENABLE), 0);
}
void hubp1_cursor_set_attributes(
struct hubp *hubp,
const struct dc_cursor_attributes *attr)
{
struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
enum cursor_pitch hw_pitch = hubp1_get_cursor_pitch(attr->pitch);
enum cursor_lines_per_chunk lpc = hubp1_get_lines_per_chunk(
attr->width, attr->color_format);
hubp->curs_attr = *attr;
REG_UPDATE(CURSOR_SURFACE_ADDRESS_HIGH,
CURSOR_SURFACE_ADDRESS_HIGH, attr->address.high_part);
REG_UPDATE(CURSOR_SURFACE_ADDRESS,
CURSOR_SURFACE_ADDRESS, attr->address.low_part);
REG_UPDATE_2(CURSOR_SIZE,
CURSOR_WIDTH, attr->width,
CURSOR_HEIGHT, attr->height);
REG_UPDATE_3(CURSOR_CONTROL,
CURSOR_MODE, attr->color_format,
CURSOR_PITCH, hw_pitch,
CURSOR_LINES_PER_CHUNK, lpc);
REG_SET_2(CURSOR_SETTINS, 0,
/* no shift of the cursor HDL schedule */
CURSOR0_DST_Y_OFFSET, 0,
/* used to shift the cursor chunk request deadline */
CURSOR0_CHUNK_HDL_ADJUST, 3);
}
static void dce110_stream_encoder_update_hdmi_info_packets(
struct stream_encoder *enc,
const struct encoder_info_frame *info_frame)
{
struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
if (enc110->se_mask->HDMI_AVI_INFO_CONT &&
enc110->se_mask->HDMI_AVI_INFO_SEND) {
if (info_frame->avi.valid) {
const uint32_t *content =
(const uint32_t *) &info_frame->avi.sb[0];
REG_WRITE(AFMT_AVI_INFO0, content[0]);
REG_WRITE(AFMT_AVI_INFO1, content[1]);
REG_WRITE(AFMT_AVI_INFO2, content[2]);
REG_WRITE(AFMT_AVI_INFO3, content[3]);
REG_UPDATE(AFMT_AVI_INFO3, AFMT_AVI_INFO_VERSION,
info_frame->avi.hb1);
REG_UPDATE_2(HDMI_INFOFRAME_CONTROL0,
HDMI_AVI_INFO_SEND, 1,
HDMI_AVI_INFO_CONT, 1);
REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE,
VBI_LINE_0 + 2);
} else {
REG_UPDATE_2(HDMI_INFOFRAME_CONTROL0,
HDMI_AVI_INFO_SEND, 0,
HDMI_AVI_INFO_CONT, 0);
}
}
if (enc110->se_mask->HDMI_AVI_INFO_CONT &&
enc110->se_mask->HDMI_AVI_INFO_SEND) {
dce110_update_hdmi_info_packet(enc110, 0, &info_frame->vendor);
dce110_update_hdmi_info_packet(enc110, 1, &info_frame->gamut);
dce110_update_hdmi_info_packet(enc110, 2, &info_frame->spd);
dce110_update_hdmi_info_packet(enc110, 3, &info_frame->hdrsmd);
}
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
if (enc110->se_mask->HDMI_DB_DISABLE) {
/* for bring up, disable dp double TODO */
if (REG(HDMI_DB_CONTROL))
REG_UPDATE(HDMI_DB_CONTROL, HDMI_DB_DISABLE, 1);
dce110_update_hdmi_info_packet(enc110, 0, &info_frame->avi);
dce110_update_hdmi_info_packet(enc110, 1, &info_frame->vendor);
dce110_update_hdmi_info_packet(enc110, 2, &info_frame->gamut);
dce110_update_hdmi_info_packet(enc110, 3, &info_frame->spd);
dce110_update_hdmi_info_packet(enc110, 4, &info_frame->hdrsmd);
}
#endif
}
static void setup_stereo_sync(
struct stream_encoder *enc,
int tg_inst, bool enable)
{
struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, tg_inst);
REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, !enable);
}
static void hubp1_disconnect(struct hubp *hubp)
{
struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
REG_UPDATE(DCHUBP_CNTL,
HUBP_TTU_DISABLE, 1);
REG_UPDATE(CURSOR_CONTROL,
CURSOR_ENABLE, 0);
}
static void dpp1_set_degamma_format_float(
struct dpp *dpp_base,
bool is_float)
{
struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
if (is_float) {
REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_INPUT_FORMAT, 3);
REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, 1);
} else {
REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_INPUT_FORMAT, 2);
REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, 0);
}
}
static void dce110_stream_encoder_dp_blank(
struct stream_encoder *enc)
{
struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
uint32_t retries = 0;
uint32_t reg1 = 0;
uint32_t max_retries = DP_BLANK_MAX_RETRY * 10;
/* Note: For CZ, we are changing driver default to disable
* stream deferred to next VBLANK. If results are positive, we
* will make the same change to all DCE versions. There are a
* handful of panels that cannot handle disable stream at
* HBLANK and will result in a white line flash across the
* screen on stream disable. */
REG_GET(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, ®1);
if ((reg1 & 0x1) == 0)
/*stream not enabled*/
return;
/* Specify the video stream disable point
* (2 = start of the next vertical blank) */
REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, 2);
/* Larger delay to wait until VBLANK - use max retry of
* 10us*3000=30ms. This covers 16.6ms of typical 60 Hz mode +
* a little more because we may not trust delay accuracy.
*/
max_retries = DP_BLANK_MAX_RETRY * 150;
/* disable DP stream */
REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0);
/* the encoder stops sending the video stream
* at the start of the vertical blanking.
* Poll for DP_VID_STREAM_STATUS == 0
*/
REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS,
0,
10, max_retries);
ASSERT(retries <= max_retries);
/* Tell the DP encoder to ignore timing from CRTC, must be done after
* the polling. If we set DP_STEER_FIFO_RESET before DP stream blank is
* complete, stream status will be stuck in video stream enabled state,
* i.e. DP_VID_STREAM_STATUS stuck at 1.
*/
REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, true);
}
static void dce110_se_enable_dp_audio(
struct stream_encoder *enc)
{
struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
/* Enable Audio packets */
REG_UPDATE(DP_SEC_CNTL, DP_SEC_ASP_ENABLE, 1);
/* Program the ATP and AIP next */
REG_UPDATE_2(DP_SEC_CNTL,
DP_SEC_ATP_ENABLE, 1,
DP_SEC_AIP_ENABLE, 1);
/* Program STREAM_ENABLE after all the other enables. */
REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
}
void bios_set_scratch_critical_state(
struct dc_bios *bios,
bool state)
{
uint32_t critial_state = state ? 1 : 0;
REG_UPDATE(BIOS_SCRATCH_6, S6_CRITICAL_STATE, critial_state);
}
void hubbub1_soft_reset(struct hubbub *hubbub, bool reset)
{
uint32_t reset_en = reset ? 1 : 0;
REG_UPDATE(DCHUBBUB_SOFT_RESET,
DCHUBBUB_GLOBAL_SOFT_RESET, reset_en);
}
static void dce110_stream_encoder_stop_dp_info_packets(
struct stream_encoder *enc)
{
/* stop generic packets on DP */
struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
uint32_t value = 0;
if (enc110->se_mask->DP_SEC_AVI_ENABLE) {
REG_SET_7(DP_SEC_CNTL, 0,
DP_SEC_GSP0_ENABLE, 0,
DP_SEC_GSP1_ENABLE, 0,
DP_SEC_GSP2_ENABLE, 0,
DP_SEC_GSP3_ENABLE, 0,
DP_SEC_AVI_ENABLE, 0,
DP_SEC_MPG_ENABLE, 0,
DP_SEC_STREAM_ENABLE, 0);
}
/* this register shared with audio info frame.
* therefore we need to keep master enabled
* if at least one of the fields is not 0 */
value = REG_READ(DP_SEC_CNTL);
if (value)
REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
}
bool dcn10_dmcu_load_iram(struct dmcu *dmcu,
unsigned int start_offset,
const char *src,
unsigned int bytes)
{
struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
unsigned int count = 0;
REG_UPDATE(DMCU_CTRL, DMCU_ENABLE, 1);
/* Enable write access to IRAM */
REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL,
IRAM_HOST_ACCESS_EN, 1,
IRAM_WR_ADDR_AUTO_INC, 1);
REG_WAIT(DMU_MEM_PWR_CNTL, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10);
REG_WRITE(DMCU_IRAM_WR_CTRL, start_offset);
for (count = 0; count < bytes; count++)
REG_WRITE(DMCU_IRAM_WR_DATA, src[count]);
/* Disable write access to IRAM to allow dynamic sleep state */
REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL,
IRAM_HOST_ACCESS_EN, 0,
IRAM_WR_ADDR_AUTO_INC, 0);
return true;
}
static void execute_transaction(
struct dce_i2c_hw *dce_i2c_hw)
{
REG_UPDATE_N(SETUP, 5,
FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_DATA_DRIVE_EN), 0,
FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_CLK_DRIVE_EN), 0,
FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_DATA_DRIVE_SEL), 0,
FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_INTRA_TRANSACTION_DELAY), 0,
FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_INTRA_BYTE_DELAY), 0);
REG_UPDATE_5(DC_I2C_CONTROL,
DC_I2C_SOFT_RESET, 0,
DC_I2C_SW_STATUS_RESET, 0,
DC_I2C_SEND_RESET, 0,
DC_I2C_GO, 0,
DC_I2C_TRANSACTION_COUNT, dce_i2c_hw->transaction_count - 1);
/* start I2C transfer */
REG_UPDATE(DC_I2C_CONTROL, DC_I2C_GO, 1);
/* all transactions were executed and HW buffer became empty
* (even though it actually happens when status becomes DONE)
*/
dce_i2c_hw->transaction_count = 0;
dce_i2c_hw->buffer_used_bytes = 0;
}
/* initialize HW state */
void dce_aud_hw_init(
struct audio *audio)
{
uint32_t value;
struct dce_audio *aud = DCE_AUD(audio);
/* we only need to program the following registers once, so we only do
it for the inst 0*/
if (audio->inst != 0)
return;
/* Suport R5 - 32khz
* Suport R6 - 44.1khz
* Suport R7 - 48khz
*/
/*disable clock gating before write to endpoint register*/
value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL);
set_reg_field_value(value, 1,
AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
CLOCK_GATING_DISABLE);
AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value);
REG_UPDATE(AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES,
AUDIO_RATE_CAPABILITIES, 0x70);
/*Keep alive bit to verify HW block in BU. */
REG_UPDATE_2(AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES,
CLKSTOP, 1,
EPSS, 1);
set_reg_field_value(value, 0,
AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
CLOCK_GATING_DISABLE);
AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value);
}
void hubp1_clk_cntl(struct hubp *hubp, bool enable)
{
struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
uint32_t clk_enable = enable ? 1 : 0;
REG_UPDATE(HUBP_CLK_CNTL, HUBP_CLOCK_ENABLE, clk_enable);
}
void hubp1_program_requestor(
struct hubp *hubp,
struct _vcs_dpi_display_rq_regs_st *rq_regs)
{
struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
REG_UPDATE(HUBPRET_CONTROL,
DET_BUF_PLANE1_BASE_ADDRESS, rq_regs->plane1_base_address);
REG_SET_4(DCN_EXPANSION_MODE, 0,
DRQ_EXPANSION_MODE, rq_regs->drq_expansion_mode,
PRQ_EXPANSION_MODE, rq_regs->prq_expansion_mode,
MRQ_EXPANSION_MODE, rq_regs->mrq_expansion_mode,
CRQ_EXPANSION_MODE, rq_regs->crq_expansion_mode);
REG_SET_8(DCHUBP_REQ_SIZE_CONFIG, 0,
CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size,
MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size,
META_CHUNK_SIZE, rq_regs->rq_regs_l.meta_chunk_size,
MIN_META_CHUNK_SIZE, rq_regs->rq_regs_l.min_meta_chunk_size,
DPTE_GROUP_SIZE, rq_regs->rq_regs_l.dpte_group_size,
MPTE_GROUP_SIZE, rq_regs->rq_regs_l.mpte_group_size,
SWATH_HEIGHT, rq_regs->rq_regs_l.swath_height,
PTE_ROW_HEIGHT_LINEAR, rq_regs->rq_regs_l.pte_row_height_linear);
REG_SET_8(DCHUBP_REQ_SIZE_CONFIG_C, 0,
CHUNK_SIZE_C, rq_regs->rq_regs_c.chunk_size,
MIN_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_chunk_size,
META_CHUNK_SIZE_C, rq_regs->rq_regs_c.meta_chunk_size,
MIN_META_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_meta_chunk_size,
DPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.dpte_group_size,
MPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.mpte_group_size,
SWATH_HEIGHT_C, rq_regs->rq_regs_c.swath_height,
PTE_ROW_HEIGHT_LINEAR_C, rq_regs->rq_regs_c.pte_row_height_linear);
}
static void hubp1_set_hubp_blank_en(struct hubp *hubp, bool blank)
{
struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
uint32_t blank_en = blank ? 1 : 0;
REG_UPDATE(DCHUBP_CNTL, HUBP_BLANK_EN, blank_en);
}
static void dce_underlay_clock_enable(struct dce_hwseq *hws)
{
/* todo: why do we need this at boot? is dce_enable_fe_clock enough? */
if (REG(DCFEV_CLOCK_CONTROL))
REG_UPDATE(DCFEV_CLOCK_CONTROL,
DCFEV_CLOCK_ENABLE, 1);
}
static void dig_connect_to_otg(
struct stream_encoder *enc,
int tg_inst)
{
struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
REG_UPDATE(DIG_FE_CNTL, DIG_SOURCE_SELECT, tg_inst);
}
static void oppn10_set_stereo_polarity(
struct output_pixel_processor *opp,
bool enable, bool rightEyePolarity)
{
struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp);
REG_UPDATE(FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, enable);
}
static void hubp1_disable_control(struct hubp *hubp, bool disable_hubp)
{
struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
uint32_t disable = disable_hubp ? 1 : 0;
REG_UPDATE(DCHUBP_CNTL,
HUBP_DISABLE, disable);
}
static void dcn10_dmcu_set_psr_enable(struct dmcu *dmcu, bool enable, bool wait)
{
struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
unsigned int dmcu_max_retry_on_wait_reg_ready = 801;
unsigned int dmcu_wait_reg_ready_interval = 100;
unsigned int retryCount;
uint32_t psr_state = 0;
/* waitDMCUReadyForCmd */
REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0,
dmcu_wait_reg_ready_interval,
dmcu_max_retry_on_wait_reg_ready);
/* setDMCUParam_Cmd */
if (enable)
REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,
PSR_ENABLE);
else
REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,
PSR_EXIT);
/* notifyDMCUMsg */
REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
/* Below loops 1000 x 500us = 500 ms.
* Exit PSR may need to wait 1-2 frames to power up. Timeout after at
* least a few frames. Should never hit the max retry assert below.
*/
if (wait == true) {
for (retryCount = 0; retryCount <= 1000; retryCount++) {
dcn10_get_dmcu_psr_state(dmcu, &psr_state);
if (enable) {
if (psr_state != 0)
break;
} else {
if (psr_state == 0)
break;
}
udelay(500);
}
/* assert if max retry hit */
ASSERT(retryCount <= 1000);
}
}
void dce110_se_audio_mute_control(
struct stream_encoder *enc,
bool mute)
{
struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, !mute);
}
static void dce110_stream_encoder_set_avmute(
struct stream_encoder *enc,
bool enable)
{
struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
unsigned int value = enable ? 1 : 0;
REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, value);
}
static void dce110_stream_encoder_update_dp_info_packets(
struct stream_encoder *enc,
const struct encoder_info_frame *info_frame)
{
struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
uint32_t value = 0;
if (info_frame->vsc.valid)
dce110_update_generic_info_packet(
enc110,
0, /* packetIndex */
&info_frame->vsc);
if (info_frame->spd.valid)
dce110_update_generic_info_packet(
enc110,
2, /* packetIndex */
&info_frame->spd);
if (info_frame->hdrsmd.valid)
dce110_update_generic_info_packet(
enc110,
3, /* packetIndex */
&info_frame->hdrsmd);
/* enable/disable transmission of packet(s).
* If enabled, packet transmission begins on the next frame
*/
REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, info_frame->vsc.valid);
REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, info_frame->spd.valid);
REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, info_frame->hdrsmd.valid);
/* This bit is the master enable bit.
* When enabling secondary stream engine,
* this master bit must also be set.
* This register shared with audio info frame.
* Therefore we need to enable master bit
* if at least on of the fields is not 0
*/
value = REG_READ(DP_SEC_CNTL);
if (value)
REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
}
