static bool setup_engine( struct dce_i2c_hw *dce_i2c_hw) { uint32_t i2c_setup_limit = I2C_SETUP_TIME_LIMIT_DCE; if (dce_i2c_hw->setup_limit != 0) i2c_setup_limit = dce_i2c_hw->setup_limit; /* Program pin select */ REG_UPDATE_6(DC_I2C_CONTROL, DC_I2C_GO, 0, DC_I2C_SOFT_RESET, 0, DC_I2C_SEND_RESET, 0, DC_I2C_SW_STATUS_RESET, 1, DC_I2C_TRANSACTION_COUNT, 0, DC_I2C_DDC_SELECT, dce_i2c_hw->engine_id); /* Program time limit */ if (dce_i2c_hw->send_reset_length == 0) { /*pre-dcn*/ REG_UPDATE_N(SETUP, 2, FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_TIME_LIMIT), i2c_setup_limit, FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_ENABLE), 1); } /* Program HW priority * set to High - interrupt software I2C at any time * Enable restart of SW I2C that was interrupted by HW * disable queuing of software while I2C is in use by HW */ REG_UPDATE_2(DC_I2C_ARBITRATION, DC_I2C_NO_QUEUED_SW_GO, 0, DC_I2C_SW_PRIORITY, DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_NORMAL); return true; }
static bool setup_engine( struct i2c_engine *i2c_engine) { struct i2c_hw_engine_dce110 *hw_engine = FROM_I2C_ENGINE(i2c_engine); /* Program pin select */ REG_UPDATE_6( DC_I2C_CONTROL, DC_I2C_GO, 0, DC_I2C_SOFT_RESET, 0, DC_I2C_SEND_RESET, 0, DC_I2C_SW_STATUS_RESET, 1, DC_I2C_TRANSACTION_COUNT, 0, DC_I2C_DDC_SELECT, hw_engine->engine_id); /* Program time limit */ REG_UPDATE_N( SETUP, 2, FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_TIME_LIMIT), I2C_SETUP_TIME_LIMIT, FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_ENABLE), 1); /* Program HW priority * set to High - interrupt software I2C at any time * Enable restart of SW I2C that was interrupted by HW * disable queuing of software while I2C is in use by HW */ REG_UPDATE_2( DC_I2C_ARBITRATION, DC_I2C_NO_QUEUED_SW_GO, 0, DC_I2C_SW_PRIORITY, DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_NORMAL); return true; }
void hubp1_program_tiling( struct hubp *hubp, const union dc_tiling_info *info, const enum surface_pixel_format pixel_format) { struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); REG_UPDATE_6(DCSURF_ADDR_CONFIG, NUM_PIPES, log_2(info->gfx9.num_pipes), NUM_BANKS, log_2(info->gfx9.num_banks), PIPE_INTERLEAVE, info->gfx9.pipe_interleave, NUM_SE, log_2(info->gfx9.num_shader_engines), NUM_RB_PER_SE, log_2(info->gfx9.num_rb_per_se), MAX_COMPRESSED_FRAGS, log_2(info->gfx9.max_compressed_frags)); REG_UPDATE_4(DCSURF_TILING_CONFIG, SW_MODE, info->gfx9.swizzle, META_LINEAR, info->gfx9.meta_linear, RB_ALIGNED, info->gfx9.rb_aligned, PIPE_ALIGNED, info->gfx9.pipe_aligned); }
static void dce110_se_setup_hdmi_audio( struct stream_encoder *enc, const struct audio_crtc_info *crtc_info) { struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); struct audio_clock_info audio_clock_info = {0}; uint32_t max_packets_per_line; /* For now still do calculation, although this field is ignored when above HDMI_PACKET_GEN_VERSION set to 1 */ max_packets_per_line = calc_max_audio_packets_per_line(crtc_info); /* HDMI_AUDIO_PACKET_CONTROL */ REG_UPDATE_2(HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, max_packets_per_line, HDMI_AUDIO_DELAY_EN, 1); /* AFMT_AUDIO_PACKET_CONTROL */ REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1); /* AFMT_AUDIO_PACKET_CONTROL2 */ REG_UPDATE_2(AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_LAYOUT_OVRD, 0, AFMT_60958_OSF_OVRD, 0); /* HDMI_ACR_PACKET_CONTROL */ REG_UPDATE_3(HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1, HDMI_ACR_SOURCE, 0, HDMI_ACR_AUDIO_PRIORITY, 0); /* Program audio clock sample/regeneration parameters */ get_audio_clock_info(crtc_info->color_depth, crtc_info->requested_pixel_clock, crtc_info->calculated_pixel_clock, &audio_clock_info); dm_logger_write(enc->ctx->logger, LOG_HW_AUDIO, "\n%s:Input::requested_pixel_clock = %d" \ "calculated_pixel_clock = %d \n", __func__, \ crtc_info->requested_pixel_clock, \ crtc_info->calculated_pixel_clock); /* HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK */ REG_UPDATE(HDMI_ACR_32_0, HDMI_ACR_CTS_32, audio_clock_info.cts_32khz); /* HDMI_ACR_32_1__HDMI_ACR_N_32_MASK */ REG_UPDATE(HDMI_ACR_32_1, HDMI_ACR_N_32, audio_clock_info.n_32khz); /* HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK */ REG_UPDATE(HDMI_ACR_44_0, HDMI_ACR_CTS_44, audio_clock_info.cts_44khz); /* HDMI_ACR_44_1__HDMI_ACR_N_44_MASK */ REG_UPDATE(HDMI_ACR_44_1, HDMI_ACR_N_44, audio_clock_info.n_44khz); /* HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK */ REG_UPDATE(HDMI_ACR_48_0, HDMI_ACR_CTS_48, audio_clock_info.cts_48khz); /* HDMI_ACR_48_1__HDMI_ACR_N_48_MASK */ REG_UPDATE(HDMI_ACR_48_1, HDMI_ACR_N_48, audio_clock_info.n_48khz); /* Video driver cannot know in advance which sample rate will be used by HD Audio driver HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE field is programmed below in interruppt callback */ /* AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK & AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK */ REG_UPDATE_2(AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1, AFMT_60958_CS_CLOCK_ACCURACY, 0); /* AFMT_60958_1 AFMT_60958_CS_CHALNNEL_NUMBER_R */ REG_UPDATE(AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2); /*AFMT_60958_2 now keep this settings until * Programming guide comes out*/ REG_UPDATE_6(AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3, AFMT_60958_CS_CHANNEL_NUMBER_3, 4, AFMT_60958_CS_CHANNEL_NUMBER_4, 5, AFMT_60958_CS_CHANNEL_NUMBER_5, 6, AFMT_60958_CS_CHANNEL_NUMBER_6, 7, AFMT_60958_CS_CHANNEL_NUMBER_7, 8); }
static void set_spatial_dither( struct dcn10_opp *oppn10, const struct bit_depth_reduction_params *params) { /*Disable spatial (random) dithering*/ REG_UPDATE_7(FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 0, FMT_SPATIAL_DITHER_MODE, 0, FMT_SPATIAL_DITHER_DEPTH, 0, FMT_TEMPORAL_DITHER_EN, 0, FMT_HIGHPASS_RANDOM_ENABLE, 0, FMT_FRAME_RANDOM_ENABLE, 0, FMT_RGB_RANDOM_ENABLE, 0); /* only use FRAME_COUNTER_MAX if frameRandom == 1*/ if (params->flags.FRAME_RANDOM == 1) { if (params->flags.SPATIAL_DITHER_DEPTH == 0 || params->flags.SPATIAL_DITHER_DEPTH == 1) { REG_UPDATE_2(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, 15, FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, 2); } else if (params->flags.SPATIAL_DITHER_DEPTH == 2) { REG_UPDATE_2(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, 3, FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, 1); } else { return; } } else { REG_UPDATE_2(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, 0, FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, 0); } /*Set seed for random values for * spatial dithering for R,G,B channels*/ REG_SET(FMT_DITHER_RAND_R_SEED, 0, FMT_RAND_R_SEED, params->r_seed_value); REG_SET(FMT_DITHER_RAND_G_SEED, 0, FMT_RAND_G_SEED, params->g_seed_value); REG_SET(FMT_DITHER_RAND_B_SEED, 0, FMT_RAND_B_SEED, params->b_seed_value); /* FMT_OFFSET_R_Cr 31:16 0x0 Setting the zero * offset for the R/Cr channel, lower 4LSB * is forced to zeros. Typically set to 0 * RGB and 0x80000 YCbCr. */ /* FMT_OFFSET_G_Y 31:16 0x0 Setting the zero * offset for the G/Y channel, lower 4LSB is * forced to zeros. Typically set to 0 RGB * and 0x80000 YCbCr. */ /* FMT_OFFSET_B_Cb 31:16 0x0 Setting the zero * offset for the B/Cb channel, lower 4LSB is * forced to zeros. Typically set to 0 RGB and * 0x80000 YCbCr. */ REG_UPDATE_6(FMT_BIT_DEPTH_CONTROL, /*Enable spatial dithering*/ FMT_SPATIAL_DITHER_EN, params->flags.SPATIAL_DITHER_ENABLED, /* Set spatial dithering mode * (default is Seed patterrn AAAA...) */ FMT_SPATIAL_DITHER_MODE, params->flags.SPATIAL_DITHER_MODE, /*Set spatial dithering bit depth*/ FMT_SPATIAL_DITHER_DEPTH, params->flags.SPATIAL_DITHER_DEPTH, /*Disable High pass filter*/ FMT_HIGHPASS_RANDOM_ENABLE, params->flags.HIGHPASS_RANDOM, /*Reset only at startup*/ FMT_FRAME_RANDOM_ENABLE, params->flags.FRAME_RANDOM, /*Set RGB data dithered with x^28+x^3+1*/ FMT_RGB_RANDOM_ENABLE, params->flags.RGB_RANDOM); }