//*****************************************************************************
//
// Perform an ECB encryption operation.
//
//*****************************************************************************
bool
AESECBEncrypt(uint32_t ui32Keysize, uint32_t *pui32Src, uint32_t *pui32Dst,
uint32_t *pui32Key, uint32_t ui32Length)
{
//
// Perform a soft reset.
//
ROM_AESReset(AES_BASE);
//
// Configure the AES module.
//
ROM_AESConfigSet(AES_BASE, (ui32Keysize | AES_CFG_DIR_ENCRYPT |
AES_CFG_MODE_ECB));
//
// Write the key.
//
ROM_AESKey1Set(AES_BASE, pui32Key, ui32Keysize);
//
// Perform the encryption.
//
ROM_AESDataProcess(AES_BASE, pui32Src, pui32Dst, ui32Length);
return(true);
}
static int AesAlign16(Aes* aes, byte* out, const byte* in, word32 sz, word32 dir, word32 mode)
{
wolfSSL_TI_lockCCM() ;
ROM_AESReset(AES_BASE);
ROM_AESConfigSet(AES_BASE, (aes->keylen | dir |
(mode==AES_CFG_MODE_CTR_NOCTR ? AES_CFG_MODE_CTR : mode)));
ROM_AESIVSet(AES_BASE, aes->reg);
ROM_AESKey1Set(AES_BASE, aes->key, aes->keylen);
if((dir == AES_CFG_DIR_DECRYPT)&& (mode == AES_CFG_MODE_CBC))
/* if input and output same will overwrite input iv */
XMEMCPY(aes->tmp, in + sz - AES_BLOCK_SIZE, AES_BLOCK_SIZE);
ROM_AESDataProcess(AES_BASE, (uint32_t *)in, (uint32_t *)out, sz);
wolfSSL_TI_unlockCCM() ;
/* store iv for next call */
if(mode == AES_CFG_MODE_CBC) {
if(dir == AES_CFG_DIR_ENCRYPT)
XMEMCPY(aes->reg, out + sz - AES_BLOCK_SIZE, AES_BLOCK_SIZE);
else
XMEMCPY(aes->reg, aes->tmp, AES_BLOCK_SIZE);
}
if(mode == AES_CFG_MODE_CTR) {
do {
int i ;
for (i = AES_BLOCK_SIZE - 1; i >= 0; i--) {
if (++((byte *)aes->reg)[i])
break ;
}
sz -= AES_BLOCK_SIZE ;
} while((int)sz > 0) ;
}
return 0 ;
}
//*****************************************************************************
//
// Perform an decryption operation.
//
//*****************************************************************************
bool
AES128ECBDecrypt(uint32_t *pui32Src, uint32_t *pui32Dst, uint32_t *pui32Key,
uint32_t ui32Length, bool bUseDMA)
{
//
// Perform a soft reset.
//
ROM_AESReset(AES_BASE);
//
// Clear the interrupt flags.
//
g_bContextInIntFlag = false;
g_bDataInIntFlag = false;
g_bContextOutIntFlag = false;
g_bDataOutIntFlag = false;
g_bContextInDMADoneIntFlag = false;
g_bDataInDMADoneIntFlag = false;
g_bContextOutDMADoneIntFlag = false;
g_bDataOutDMADoneIntFlag = false;
//
// Enable all interrupts.
//
ROM_AESIntEnable(AES_BASE, (AES_INT_CONTEXT_IN | AES_INT_CONTEXT_OUT |
AES_INT_DATA_IN | AES_INT_DATA_OUT));
//
// Configure the AES module.
//
ROM_AESConfigSet(AES_BASE, (AES_CFG_KEY_SIZE_128BIT | AES_CFG_DIR_DECRYPT |
AES_CFG_MODE_ECB));
//
// Write the key.
//
ROM_AESKey1Set(AES_BASE, pui32Key, AES_CFG_KEY_SIZE_128BIT);
//
// Depending on the argument, perform the decryption
// with or without uDMA.
//
if(bUseDMA)
{
//
// Enable DMA interrupts.
//
ROM_AESIntEnable(AES_BASE, (AES_INT_DMA_CONTEXT_IN |
AES_INT_DMA_DATA_IN |
AES_INT_DMA_CONTEXT_OUT |
AES_INT_DMA_DATA_OUT));
//
// Setup the DMA module to copy data in.
//
ROM_uDMAChannelAssign(UDMA_CH14_AES0DIN);
ROM_uDMAChannelAttributeDisable(UDMA_CH14_AES0DIN,
UDMA_ATTR_ALTSELECT |
UDMA_ATTR_USEBURST |
UDMA_ATTR_HIGH_PRIORITY |
UDMA_ATTR_REQMASK);
ROM_uDMAChannelControlSet(UDMA_CH14_AES0DIN | UDMA_PRI_SELECT,
UDMA_SIZE_32 | UDMA_SRC_INC_32 |
UDMA_DST_INC_NONE | UDMA_ARB_4 |
UDMA_DST_PROT_PRIV);
ROM_uDMAChannelTransferSet(UDMA_CH14_AES0DIN | UDMA_PRI_SELECT,
UDMA_MODE_BASIC, (void *)pui32Dst,
(void *)(AES_BASE + AES_O_DATA_IN_0),
LengthRoundUp(ui32Length) / 4);
UARTprintf("Data in DMA request enabled.\n");
//
// Setup the DMA module to copy the data out.
//
ROM_uDMAChannelAssign(UDMA_CH15_AES0DOUT);
ROM_uDMAChannelAttributeDisable(UDMA_CH15_AES0DOUT,
UDMA_ATTR_ALTSELECT |
UDMA_ATTR_USEBURST |
UDMA_ATTR_HIGH_PRIORITY |
UDMA_ATTR_REQMASK);
ROM_uDMAChannelControlSet(UDMA_CH15_AES0DOUT | UDMA_PRI_SELECT,
UDMA_SIZE_32 | UDMA_SRC_INC_NONE |
UDMA_DST_INC_32 | UDMA_ARB_4 |
UDMA_SRC_PROT_PRIV);
ROM_uDMAChannelTransferSet(UDMA_CH15_AES0DOUT | UDMA_PRI_SELECT,
UDMA_MODE_BASIC,
(void *)(AES_BASE + AES_O_DATA_IN_0),
(void *)pui32Src,
LengthRoundUp(ui32Length) / 4);
UARTprintf("Data out DMA request enabled.\n");
//
// Write the length registers to start the process.
//
ROM_AESLengthSet(AES_BASE, (uint64_t)ui32Length);
//
// Enable the DMA channels to start the transfers. This must be done after
// writing the length to prevent data from copying before the context is
// truly ready.
//
ROM_uDMAChannelEnable(UDMA_CH14_AES0DIN);
ROM_uDMAChannelEnable(UDMA_CH15_AES0DOUT);
//
// Enable DMA requests
//
ROM_AESDMAEnable(AES_BASE, AES_DMA_DATA_IN | AES_DMA_DATA_OUT);
//
// Wait for the data in DMA done interrupt.
//
while(!g_bDataInDMADoneIntFlag)
{
}
//
// Wait for the data out DMA done interrupt.
//
while(!g_bDataOutDMADoneIntFlag)
{
}
}
else
{
//
// Perform the decryption.
//
ROM_AESDataProcess(AES_BASE, pui32Src, pui32Dst, ui32Length);
}
return(true);
}