void ROM_MapBank(u32 bank, u8* ptr)
{
u32 hi_slow = SNES_FastROM ? 0 : MPTR_SLOW;
if (SNES_HiROM)
{
for (; bank < 0x80; bank += ROM_NumBanks)
{
if (bank < 0x7E)
{
MEM_PTR(bank, 0x0000) = MPTR_SLOW | MPTR_READONLY | (u32)&ptr[0x0000];
MEM_PTR(bank, 0x2000) = MPTR_SLOW | MPTR_READONLY | (u32)&ptr[0x2000];
MEM_PTR(bank, 0x4000) = MPTR_SLOW | MPTR_READONLY | (u32)&ptr[0x4000];
MEM_PTR(bank, 0x6000) = MPTR_SLOW | MPTR_READONLY | (u32)&ptr[0x6000];
MEM_PTR(bank, 0x8000) = MPTR_SLOW | MPTR_READONLY | (u32)&ptr[0x8000];
MEM_PTR(bank, 0xA000) = MPTR_SLOW | MPTR_READONLY | (u32)&ptr[0xA000];
MEM_PTR(bank, 0xC000) = MPTR_SLOW | MPTR_READONLY | (u32)&ptr[0xC000];
MEM_PTR(bank, 0xE000) = MPTR_SLOW | MPTR_READONLY | (u32)&ptr[0xE000];
}
MEM_PTR(0x80 + bank, 0x0000) = hi_slow | MPTR_READONLY | (u32)&ptr[0x0000];
MEM_PTR(0x80 + bank, 0x2000) = hi_slow | MPTR_READONLY | (u32)&ptr[0x2000];
MEM_PTR(0x80 + bank, 0x4000) = hi_slow | MPTR_READONLY | (u32)&ptr[0x4000];
MEM_PTR(0x80 + bank, 0x6000) = hi_slow | MPTR_READONLY | (u32)&ptr[0x6000];
MEM_PTR(0x80 + bank, 0x8000) = hi_slow | MPTR_READONLY | (u32)&ptr[0x8000];
MEM_PTR(0x80 + bank, 0xA000) = hi_slow | MPTR_READONLY | (u32)&ptr[0xA000];
MEM_PTR(0x80 + bank, 0xC000) = hi_slow | MPTR_READONLY | (u32)&ptr[0xC000];
MEM_PTR(0x80 + bank, 0xE000) = hi_slow | MPTR_READONLY | (u32)&ptr[0xE000];
MEM_PTR(bank - 0x40, 0x8000) = MPTR_SLOW | MPTR_READONLY | (u32)&ptr[0x8000];
MEM_PTR(bank - 0x40, 0xA000) = MPTR_SLOW | MPTR_READONLY | (u32)&ptr[0xA000];
MEM_PTR(bank - 0x40, 0xC000) = MPTR_SLOW | MPTR_READONLY | (u32)&ptr[0xC000];
MEM_PTR(bank - 0x40, 0xE000) = MPTR_SLOW | MPTR_READONLY | (u32)&ptr[0xE000];
MEM_PTR(0x40 + bank, 0x8000) = hi_slow | MPTR_READONLY | (u32)&ptr[0x8000];
MEM_PTR(0x40 + bank, 0xA000) = hi_slow | MPTR_READONLY | (u32)&ptr[0xA000];
MEM_PTR(0x40 + bank, 0xC000) = hi_slow | MPTR_READONLY | (u32)&ptr[0xC000];
MEM_PTR(0x40 + bank, 0xE000) = hi_slow | MPTR_READONLY | (u32)&ptr[0xE000];
}
}
else
{
for (; bank < 0x80; bank += ROM_NumBanks)
{
if (bank >= 0x40 && bank < 0x70)
{
MEM_PTR(bank, 0x0000) = MPTR_SLOW | MPTR_READONLY | (u32)&ptr[0x0000];
MEM_PTR(bank, 0x2000) = MPTR_SLOW | MPTR_READONLY | (u32)&ptr[0x2000];
MEM_PTR(bank, 0x4000) = MPTR_SLOW | MPTR_READONLY | (u32)&ptr[0x4000];
MEM_PTR(bank, 0x6000) = MPTR_SLOW | MPTR_READONLY | (u32)&ptr[0x6000];
MEM_PTR(0x80 + bank, 0x0000) = hi_slow | MPTR_READONLY | (u32)&ptr[0x0000];
MEM_PTR(0x80 + bank, 0x2000) = hi_slow | MPTR_READONLY | (u32)&ptr[0x2000];
MEM_PTR(0x80 + bank, 0x4000) = hi_slow | MPTR_READONLY | (u32)&ptr[0x4000];
MEM_PTR(0x80 + bank, 0x6000) = hi_slow | MPTR_READONLY | (u32)&ptr[0x6000];
}
if (bank < 0x7E)
{
MEM_PTR(bank, 0x8000) = MPTR_SLOW | MPTR_READONLY | (u32)&ptr[0x0000];
MEM_PTR(bank, 0xA000) = MPTR_SLOW | MPTR_READONLY | (u32)&ptr[0x2000];
MEM_PTR(bank, 0xC000) = MPTR_SLOW | MPTR_READONLY | (u32)&ptr[0x4000];
MEM_PTR(bank, 0xE000) = MPTR_SLOW | MPTR_READONLY | (u32)&ptr[0x6000];
}
MEM_PTR(0x80 + bank, 0x8000) = hi_slow | MPTR_READONLY | (u32)&ptr[0x0000];
MEM_PTR(0x80 + bank, 0xA000) = hi_slow | MPTR_READONLY | (u32)&ptr[0x2000];
MEM_PTR(0x80 + bank, 0xC000) = hi_slow | MPTR_READONLY | (u32)&ptr[0x4000];
MEM_PTR(0x80 + bank, 0xE000) = hi_slow | MPTR_READONLY | (u32)&ptr[0x6000];
}
}
ROM_ApplySpeedHacks(bank, ptr);
}
void Mem_Reset()
{
u32 i, a, b;
for (i = 0; i < (128 * 1024); i += 4)
*(u32*)&Mem_SysRAM[i] = 0x55555555; // idk about this
//fseek(ROM_File, ROM_BaseOffset, SEEK_SET);
//fread(ROM_Bank0, 0x8000, 1, ROM_File);
if (!ROM_CacheInited)
{
for (i = 0; i < 32 + 3; i++)
ROM_Cache[i] = 0;
ROM_CacheInited = 0;
}
for (i = 0; i < 32 + 3; i++)
ROM_CacheBank[i] = -1;
ROM_CacheIndex = 0;
for (i = 0; i < 0x200; i++)
ROM_CacheMisses[i] = 0;
if (Mem_SRAM) free(Mem_SRAM);
Mem_SRAM = malloc(Mem_SRAMMask + 1);
for (i = 0; i <= Mem_SRAMMask; i += 4)
*(u32*)&Mem_SRAM[i] = 0;
Mem_SRAMFile = fopen(Mem_SRAMPath, "r");
if (Mem_SRAMFile)
{
fread(Mem_SRAM, Mem_SRAMMask+1, 1, Mem_SRAMFile);
fclose(Mem_SRAMFile);
Mem_SRAMFile = NULL;
}
Mem_Status = &_Mem_PtrTable[0];
Mem_PtrTable = &_Mem_PtrTable[MEMSTATUS_SIZE >> 2];
Mem_Status->SRAMDirty = 0;
Mem_Status->HVBFlags = 0x00;
for (b = 0; b < 0x40; b++)
{
MEM_PTR(b, 0x0000) = MEM_PTR(0x80 + b, 0x0000) = MPTR_SLOW | (u32)&Mem_SysRAM[0];
MEM_PTR(b, 0x2000) = MEM_PTR(0x80 + b, 0x2000) = MPTR_SPECIAL;
MEM_PTR(b, 0x4000) = MEM_PTR(0x80 + b, 0x4000) = MPTR_SPECIAL;
if (Mem_HiROM)
MEM_PTR(b, 0x6000) = MEM_PTR(0x80 + b, 0x6000) = MPTR_SLOW | MPTR_SRAM | (u32)&Mem_SRAM[(b << 13) & Mem_SRAMMask];
else
MEM_PTR(b, 0x6000) = MEM_PTR(0x80 + b, 0x6000) = MPTR_SLOW | MPTR_SPECIAL;
}
//for (a = 0; a < 0x8000; a += 0x2000)
// MEM_PTR(0, 0x8000 + a) = MEM_PTR(0x80, 0x8000 + a) = MPTR_SLOW | MPTR_READONLY | (u32)&ROM_Bank0[a];
for (b = 1; b < 0x40; b++)
{
u32 offset = Mem_HiROM ? (0x8000 + (b << 16)) : (b << 15);
for (a = 0; a < 0x8000; a += 0x2000)
MEM_PTR(b, 0x8000 + a) = MEM_PTR(0x80 + b, 0x8000 + a) = MPTR_SLOW | MPTR_SPECIAL | MPTR_READONLY | (ROM_BaseOffset + offset + a);
}
if (Mem_HiROM)
{
for (b = 0; b < 0x3E; b++)
for (a = 0; a < 0x10000; a += 0x2000)
MEM_PTR(0x40 + b, a) = MEM_PTR(0xC0 + b, a) = MPTR_SLOW | MPTR_SPECIAL | MPTR_READONLY | (ROM_BaseOffset + (b << 16) + a);
for (b = 0; b < 0x02; b++)
for (a = 0; a < 0x10000; a += 0x2000)
MEM_PTR(0x7E + b, a) = MPTR_SLOW | (u32)&Mem_SysRAM[(b << 16) + a];
for (b = 0; b < 0x02; b++)
for (a = 0; a < 0x10000; a += 0x2000)
MEM_PTR(0xFE + b, a) = MPTR_SLOW | MPTR_SPECIAL | MPTR_READONLY | (ROM_BaseOffset + 0x3E0000 + (b << 16) + a);
}
else
{
for (b = 0; b < 0x30; b++)
for (a = 0; a < 0x10000; a += 0x2000)
MEM_PTR(0x40 + b, a) = MEM_PTR(0xC0 + b, a) = MPTR_SLOW | MPTR_SPECIAL | MPTR_READONLY | (ROM_BaseOffset + 0x200000 + (b << 15) + (a & 0x7FFF));
for (b = 0; b < 0x0E; b++)
for (a = 0; a < 0x8000; a += 0x2000)
MEM_PTR(0x70 + b, a) = MEM_PTR(0xF0 + b, a) = MPTR_SLOW | MPTR_SRAM | (u32)&Mem_SRAM[((b << 15) + a) & Mem_SRAMMask];
for (b = 0; b < 0x02; b++)
for (a = 0; a < 0x10000; a += 0x2000)
MEM_PTR(0x7E + b, a) = MEM_PTR(0xFE + b, a) = MPTR_SLOW | (u32)&Mem_SysRAM[(b << 16) + a];
}
for (i = 0; i < 32; i++)
{
u32 fofs = Mem_HiROM ? (i << 16) : (i << 15);
if (fofs >= ROM_FileSize - ROM_BaseOffset)
break;
_ROM_DoCacheBank(i, 0, true);
}
ROM_Bank0 = ROM_Cache[0];
ROM_Bank0End = Mem_HiROM ? (ROM_Bank0 + 0x10000) : (ROM_Bank0 + 0x8000);
ROM_ApplySpeedHacks();
ROM_FileOffset = -1;
iprintf("sysram = %08X\n", &Mem_SysRAM[0]);
// get uncached address
u32 ipcsize = (sizeof(IPCStruct) + 0x1F) & ~0x1F;
IPC = memalign(32, ipcsize);
DC_InvalidateRange(IPC, ipcsize);
IPC = memUncached(IPC);
iprintf("IPC struct = %08X\n", IPC);
fifoSendValue32(FIFO_USER_01, 3);
fifoSendAddress(FIFO_USER_01, IPC);
Mem_HVBJOY = 0x00;
Mem_MulA = 0;
Mem_MulRes = 0;
Mem_DivA = 0;
Mem_DivRes = 0;
PPU_Reset();
}
