//*****************************************************************************
//
// Writes the extended address register, allowing the full contents of the
// MX66L51235F to be accessed.
//
//*****************************************************************************
static void
MX66L51235FWriteEAR(uint32_t ui32Addr)
{
//
// See if the extended address register needs to be written.
//
if((ui32Addr & 0xff000000) == (g_ui32MX66L51235FAddr & 0xff000000)) {
//
// The extended address register does not need to be changed, so return
// without doing anything.
//
return;
}
//
// Save the new value of the extended address register.
//
g_ui32MX66L51235FAddr = ui32Addr;
//
// Enable program/erase of the SPI flash.
//
MX66L51235FWriteEnable();
//
// Assert the chip select to the MX66L51235F.
//
ROM_GPIOPinWrite(GPIO_PORTQ_BASE, GPIO_PIN_1, 0);
//
// Set the SSI module into write-only mode.
//
ROM_SSIAdvModeSet(SSI3_BASE, SSI_ADV_MODE_WRITE);
//
// Send the sector erase command.
//
ROM_SSIDataPut(SSI3_BASE, 0xc5);
//
// Send the address of the sector to be erased, marking the last byte of
// the address as the end of the frame.
//
ROM_SSIAdvDataPutFrameEnd(SSI3_BASE, (ui32Addr >> 24) & 0xff);
//
// Wait until the command has been completely transmitted.
//
while(ROM_SSIBusy(SSI3_BASE)) {
}
//
// De-assert the chip select to the MX66L51235F.
//
ROM_GPIOPinWrite(GPIO_PORTQ_BASE, GPIO_PIN_1, GPIO_PIN_1);
}
uint8_t SPIClass::transfer(uint8_t data) {
unsigned long rxData;
ROM_SSIDataPut(SSIBASE, data);
while(ROM_SSIBusy(SSIBASE));
ROM_SSIDataGet(SSIBASE, &rxData);
return (uint8_t) rxData;
}
uint8_t SPIClass::transfer(uint8_t ssPin, uint8_t data, uint8_t transferMode) {
unsigned long rxData;
digitalWrite(ssPin, LOW);
ROM_SSIDataPut(SSIBASE, data);
while(ROM_SSIBusy(SSIBASE));
if(transferMode == SPI_LAST)
digitalWrite(ssPin, HIGH);
else
digitalWrite(ssPin, LOW);
ROM_SSIDataGet(SSIBASE, &rxData);
return (uint8_t) rxData;
}
void muxInit(void)
{
// enable SSI3 and GPIOD peripherals
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI1);
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF);
// Configure GPIO pins for special functions
GPIOPinConfigure(GPIO_PF2_SSI1CLK);
GPIOPinConfigure(GPIO_PF1_SSI1TX);
GPIOPinConfigure(GPIO_PF3_SSI1FSS);
ROM_GPIOPinTypeSSI(MUX_BASE, DIN_PIN | SCLK_PIN | SYNC_PIN);
//Configure and enable SSI port
// Use internal 16Mhz RC oscillator as SSI clock source
ROM_SSIClockSourceSet(SSI1_BASE, SSI_CLOCK_PIOSC);
ROM_SSIConfigSetExpClk(SSI1_BASE, 16000000, SSI_FRF_MOTO_MODE_0,
SSI_MODE_MASTER, 8000000, 8);
ROM_SSIEnable(SSI1_BASE);
// Load default configuration parameters
ROM_SSIDataPut(SSI1_BASE, ALL_OFF);
}
unsigned char
pdlibSPI_TransferByte(unsigned char ucData)
{
unsigned long ulRxData;
/* Validate parameters */
if(g_SSI < 5)
{
#ifdef PART_LM4F120H5QR
ROM_SSIDataPut(g_SSIModule[g_SSI][SSIBASE], ucData);
/* Wait until current transmission is over */
while(ROM_SSIBusy(g_SSIModule[g_SSI][SSIBASE]));
ROM_SSIDataGet(g_SSIModule[g_SSI][SSIBASE], &ulRxData);
/* Wait until current transmission is over */
while(ROM_SSIBusy(g_SSIModule[g_SSI][SSIBASE]));
#endif
}
return ((unsigned char)(ulRxData & 0xFF));
}
void SPIWrite(unsigned short SPINum, unsigned long data) {
ROM_SSIDataPut(SSIBase[SPINum], data);
}
void muxChannelChange(unsigned char channelNum)
{
ROM_SSIDataPut(SSI1_BASE, BASE_CHANNEL + channelNum);
}
