static int init_base(uart_t uart, uint32_t baudrate) { /*The base address of the chosen UART */ unsigned long ulBase = g_ulUARTBase[uart]; ROM_SysCtlPeripheralEnable(g_ulUARTPeriph[uart]); switch(uart){ #if UART_0_EN case UART_0: ROM_SysCtlPeripheralEnable(UART_0_PORT); ROM_GPIOPinConfigure(UART_0_RX_PIN); ROM_GPIOPinConfigure(UART_0_TX_PIN); ROM_GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1); break; #endif #if UART_1_EN case UART_1: ROM_SysCtlPeripheralEnable(UART_1_PORT); ROM_GPIOPinConfigure(UART_1_RX_PIN); ROM_GPIOPinConfigure(UART_1_TX_PIN); ROM_GPIOPinTypeUART(GPIO_PORTB_BASE, GPIO_PIN_0 | GPIO_PIN_1); break; #endif } ROM_UARTDisable(ulBase); ROM_UARTConfigSetExpClk(ulBase,UART_CLK, baudrate, (UART_CONFIG_PAR_NONE | UART_CONFIG_STOP_ONE | UART_CONFIG_WLEN_8)); ROM_UARTEnable(ulBase); return 0; }
//***************************************************************************** // // Initialize UART0 and set the appropriate communication parameters. // //***************************************************************************** void SetupForUART(void) { // // We need to make sure that UART0 and its associated GPIO port are // enabled before we pass control to the boot loader. The serial boot // loader does not enable or configure these peripherals for us if we // enter it via its SVC vector. // ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0); ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA); // // Set GPIO A0 and A1 as UART. // ROM_GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1); // // Configure the UART for 115200, n, 8, 1 // ROM_UARTConfigSetExpClk(UART0_BASE, SysCtlClockGet(), 115200, (UART_CONFIG_PAR_NONE | UART_CONFIG_STOP_ONE | UART_CONFIG_WLEN_8)); // // Enable the UART operation. // ROM_UARTEnable(UART0_BASE); }
/* * UART3 is used to communicate with the Optode. Set UART3 * to 9600 baud, 8, N, 1. Also, set up and enable the RX FIFO interrupt * to receive data. */ void UART3Init(void) { // set up UART3 to the optode ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC); ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_UART3); ROM_GPIOPinConfigure(GPIO_PC6_U3RX); //set up the pins ROM_GPIOPinConfigure(GPIO_PC7_U3TX); ROM_GPIOPinTypeUART(GPIO_PORTC_BASE, GPIO_PIN_6 | GPIO_PIN_7); //9600 baud, 8, N, 1 ROM_UARTConfigSetExpClk(UART3_BASE, ROM_SysCtlClockGet(), 9600, (UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE | UART_CONFIG_PAR_NONE)); // Enable the UART. ROM_UARTEnable(UART3_BASE); //RX interrupt will occur when FIFO is 1/8 full ROM_UARTFIFOLevelSet(UART3_BASE, UART_FIFO_TX7_8, UART_FIFO_RX1_8); //enable the interrupt ROM_IntEnable(INT_UART3); //flush the RX fifo before enabling the RX interrupt to get rid of residual data while(ROM_UARTCharsAvail(UART3_BASE)) { ROM_UARTCharGetNonBlocking(UART3_BASE); } //Enable the UART peripheral interrupt...receive ROM_UARTIntEnable(UART3_BASE, UART_INT_RX); }
BOOL xMBTCPPortInit(USHORT port) { ROM_SysCtlPeripheralEnable(WIZ610_GPIO_PERIPH); ROM_GPIODirModeSet(WIZ610_GPIO_BASE,WIZ610_GPIO_PIN_CMD_ENABLE ,GPIO_DIR_MODE_OUT); ROM_GPIOPadConfigSet(WIZ610_GPIO_BASE,WIZ610_GPIO_PIN_CMD_ENABLE,GPIO_STRENGTH_8MA,GPIO_PIN_TYPE_STD_WPU); ROM_GPIOPinWrite(WIZ610_GPIO_BASE,WIZ610_GPIO_PIN_CMD_ENABLE,WIZ610_GPIO_PIN_CMD_ENABLE); // uart setup ROM_SysCtlPeripheralEnable(WIZ610_UART_PERIPH); ROM_GPIOPinConfigure(GPIO_PB0_U1RX); ROM_GPIOPinConfigure(GPIO_PB1_U1TX); ROM_GPIOPinTypeUART(WIZ610_GPIO_BASE, WIZ610_GPIO_PIN_RX | WIZ610_GPIO_PIN_TX); ROM_UARTConfigSetExpClk(WIZ610_UART_BASE, ROM_SysCtlClockGet(), 38400, (UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE | UART_CONFIG_PAR_NONE)); ROM_GPIOPinWrite(WIZ610_GPIO_BASE,WIZ610_GPIO_PIN_CMD_ENABLE,WIZ610_GPIO_PIN_CMD_ENABLE); ROM_UARTFIFOLevelSet(WIZ610_UART_BASE, UART_FIFO_TX4_8, UART_FIFO_RX1_8); ROM_IntEnable(INT_UART1); ROM_UARTEnable(WIZ610_UART_BASE); ROM_UARTDMAEnable(WIZ610_UART_BASE, UART_DMA_TX); ROM_UARTIntEnable(WIZ610_UART_BASE, UART_INT_RX); ROM_IntEnable(INT_UDMA); WIZ610Transfer(); cmd_modbus_switch=0; g_ulRxBufACount=0; modbus_tcp_rab=MODBUS_TCP_IDLE; return TRUE; }
void Terminal_Init() { ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0); ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA); ROM_GPIOPinConfigure(GPIO_PA0_U0RX); ROM_GPIOPinConfigure(GPIO_PA1_U0TX); ROM_GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_0); ROM_GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_1); ROM_UARTConfigSetExpClk(UART0_BASE, g_ui32SysClock, 57600, (UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE | UART_CONFIG_PAR_NONE)); ROM_UARTEnable(UART0_BASE); }
void HardwareSerial::begin(unsigned long baud) { // // Initialize the UART. // ROM_SysCtlPeripheralEnable(g_ulUARTInt[uartModule]); //TODO:Add functionality for PinConfigure with variable uartModule ROM_GPIOPinConfigure(GPIO_PA0_U0RX); ROM_GPIOPinConfigure(GPIO_PA1_U0TX); ROM_GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1); // // Only allow a single instance to be opened. // ASSERT(g_ulUARTBase[uartModule] == 0); // // Check to make sure the UART peripheral is present. // if(!ROM_SysCtlPeripheralPresent(g_ulUARTPeriph[uartModule])) { return; } ROM_SysCtlPeripheralEnable(g_ulUARTPeriph[uartModule]); ROM_UARTConfigSetExpClk(g_ulUARTBase[uartModule], ROM_SysCtlClockGet(), baud, (UART_CONFIG_PAR_NONE | UART_CONFIG_STOP_ONE | UART_CONFIG_WLEN_8)); // // Set the UART to interrupt whenever the TX FIFO is almost empty or // when any character is received. // ROM_UARTFIFOLevelSet(g_ulUARTBase[uartModule], UART_FIFO_TX1_8, UART_FIFO_RX1_8); flushAll(); ROM_UARTIntDisable(g_ulUARTBase[uartModule], 0xFFFFFFFF); ROM_UARTIntEnable(g_ulUARTBase[uartModule], UART_INT_RX | UART_INT_RT); ROM_IntMasterEnable(); ROM_IntEnable(g_ulUARTInt[uartModule]); // // Enable the UART operation. // ROM_UARTEnable(g_ulUARTBase[uartModule]); }
void HardwareSerial::begin(unsigned long baud) { baudRate = baud; // // Initialize the UART. // ROM_SysCtlPeripheralEnable(g_ulUARTPeriph[uartModule]); //TODO:Add functionality for PinConfigure with variable uartModule ROM_GPIOPinConfigure(g_ulUARTConfig[uartModule][0]); ROM_GPIOPinConfigure(g_ulUARTConfig[uartModule][1]); ROM_GPIOPinTypeUART(g_ulUARTPort[uartModule], g_ulUARTPins[uartModule]); ROM_UARTConfigSetExpClk(UART_BASE, F_CPU, baudRate, (UART_CONFIG_PAR_NONE | UART_CONFIG_STOP_ONE | UART_CONFIG_WLEN_8)); // // Set the UART to interrupt whenever the TX FIFO is almost empty or // when any character is received. // ROM_UARTFIFOLevelSet(UART_BASE, UART_FIFO_TX1_8, UART_FIFO_RX1_8); flushAll(); ROM_UARTIntDisable(UART_BASE, 0xFFFFFFFF); ROM_UARTIntEnable(UART_BASE, UART_INT_RX | UART_INT_RT); ROM_IntEnable(g_ulUARTInt[uartModule]); // // Enable the UART operation. // ROM_UARTEnable(UART_BASE); // Allocate TX & RX buffers if (txBuffer != (unsigned char *)0xFFFFFFFF) // Catch attempts to re-init this Serial instance by freeing old buffer first free(txBuffer); if (rxBuffer != (unsigned char *)0xFFFFFFFF) // Catch attempts to re-init this Serial instance by freeing old buffer first free(rxBuffer); txBuffer = (unsigned char *) malloc(txBufferSize); rxBuffer = (unsigned char *) malloc(rxBufferSize); SysCtlDelay(100); }
unsigned char Wiz610_put_buf(unsigned char *buf, unsigned long count) { unsigned long i; unsigned long ulMode; ulMode=ROM_uDMAChannelModeGet(UDMA_CHANNEL_UART1TX | UDMA_PRI_SELECT); if (ulMode!=UDMA_MODE_STOP) return false; i=0; while(i<count) { g_ucTxBuf[i]=*buf++; i++; } ROM_uDMAChannelTransferSet(UDMA_CHANNEL_UART1TX | UDMA_PRI_SELECT, UDMA_MODE_BASIC,(void *) g_ucTxBuf, (void *)(UART1_BASE + UART_O_DR), count); ROM_UARTEnable(WIZ610_UART_BASE); ROM_uDMAChannelEnable(UDMA_CHANNEL_UART1TX); return true; }
void wiz610_init(void) { ROM_SysCtlPeripheralEnable(WIZ610_GPIO_PERIPH); ROM_GPIODirModeSet(WIZ610_GPIO_BASE,WIZ610_GPIO_PIN_CMD_ENABLE ,GPIO_DIR_MODE_OUT); ROM_GPIOPadConfigSet(WIZ610_GPIO_BASE,WIZ610_GPIO_PIN_CMD_ENABLE,GPIO_STRENGTH_8MA,GPIO_PIN_TYPE_STD_WPU); ROM_GPIOPinWrite(WIZ610_GPIO_BASE,WIZ610_GPIO_PIN_CMD_ENABLE,WIZ610_GPIO_PIN_CMD_ENABLE); // uart setup ROM_SysCtlPeripheralEnable(WIZ610_UART_PERIPH); ROM_GPIOPinConfigure(GPIO_PB0_U1RX); ROM_GPIOPinConfigure(GPIO_PB1_U1TX); ROM_GPIOPinTypeUART(WIZ610_GPIO_BASE, WIZ610_GPIO_PIN_RX | WIZ610_GPIO_PIN_TX); ROM_UARTConfigSetExpClk(WIZ610_UART_BASE, ROM_SysCtlClockGet(), 38400, (UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE | UART_CONFIG_PAR_NONE)); ROM_GPIOPinWrite(WIZ610_GPIO_BASE,WIZ610_GPIO_PIN_CMD_ENABLE,0); ROM_UARTFIFOLevelSet(WIZ610_UART_BASE, UART_FIFO_TX4_8, UART_FIFO_RX1_8); ROM_IntEnable(INT_UART1); ROM_UARTEnable(WIZ610_UART_BASE); ROM_UARTDMAEnable(WIZ610_UART_BASE, UART_DMA_TX); ROM_UARTIntEnable(WIZ610_UART_BASE, UART_INT_RX); ROM_IntEnable(INT_UDMA); cmd_modbus_switch=1; }
static int init_base(uart_t uart, uint32_t baudrate) { switch(uart){ #if UART_0_EN case UART_0: ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0); ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA); ROM_GPIOPinConfigure(GPIO_PA0_U0RX); ROM_GPIOPinConfigure(GPIO_PA1_U0TX); ROM_GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1); ROM_UARTDisable(UART0_BASE); ROM_UARTConfigSetExpClk(UART0_BASE,ROM_SysCtlClockGet(), baudrate, (UART_CONFIG_PAR_NONE | UART_CONFIG_STOP_ONE | UART_CONFIG_WLEN_8)); ROM_UARTEnable(UART0_BASE); break; #endif } return 0; }
void enableUART(uint8_t UART, unsigned long baudRate) { // We must unlock PD7 to use UART2 if (UART == 2) { // GPIO Port D Lock Register is at 0x40007520 HWREG(0x40007520) = GPIO_LOCK_KEY; // GPIO Port D Control Register is at 0x40007524 HWREG(0x40007524) = 0x80; } // Enable the UART peripheral in SysCtl ROM_SysCtlPeripheralEnable(SysCtlGPIOs[UARTPins[UART][0] / 8]); ROM_SysCtlPeripheralSleepEnable(SysCtlGPIOs[UARTPins[UART][0] / 8]); ROM_SysCtlPeripheralEnable(SysCtlUARTs[UART]); ROM_SysCtlPeripheralSleepEnable(SysCtlUARTs[UART]); // Configure the associated GPIO pins for UART ROM_GPIOPinConfigure(UARTPins[UART][2]); ROM_GPIOPinConfigure(UARTPins[UART][3]); ROM_GPIOPinTypeUART(GPIO[UARTPins[UART][0] / 8], bit8[UARTPins[UART][0] % 8] | bit8[UARTPins[UART][1] % 8]); // Configure the UART ROM_UARTConfigSetExpClk(UARTBASE[UART], ROM_SysCtlClockGet(), baudRate, (UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE | UART_CONFIG_PAR_NONE)); ROM_UARTFIFOEnable(UARTBASE[UART]); // Configure the UART receive (rx) interrupt ROM_UARTIntEnable(UARTBASE[UART], UART_INT_RX); UARTFIFOLevelSet(UARTBASE[UART], UART_FIFO_TX4_8, UART_FIFO_RX4_8); UARTIntRegister(UARTBASE[UART], rxInterrupts[UART]); ROM_IntPrioritySet(UART_INTs[UART], 0x00); // Enable the UART ROM_UARTEnable(UARTBASE[UART]); }
//***************************************************************************** // // Initializes the UART0 peripheral and sets up the TX and RX uDMA channels. // The UART is configured for loopback mode so that any data sent on TX will be // received on RX. The uDMA channels are configured so that the TX channel // will copy data from a buffer to the UART TX output. And the uDMA RX channel // will receive any incoming data into a pair of buffers in ping-pong mode. // //***************************************************************************** void InitUART0Transfer(void) { unsigned int uIdx; // // Fill the TX buffer with a simple data pattern. // for(uIdx = 0; uIdx < UART_TXBUF_SIZE; uIdx++) { g_ucTxBuf[uIdx] = uIdx; } // // Enable the UART peripheral, and configure it to operate even if the CPU // is in sleep. // ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0); ROM_SysCtlPeripheralSleepEnable(SYSCTL_PERIPH_UART0); // // Configure the UART communication parameters. // ROM_UARTConfigSetExpClk(UART0_BASE, ROM_SysCtlClockGet(), 115200, UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE | UART_CONFIG_PAR_NONE); // // Set both the TX and RX trigger thresholds to 4. This will be used by // the uDMA controller to signal when more data should be transferred. The // uDMA TX and RX channels will be configured so that it can transfer 4 // bytes in a burst when the UART is ready to transfer more data. // ROM_UARTFIFOLevelSet(UART0_BASE, UART_FIFO_TX4_8, UART_FIFO_RX4_8); // // Enable the UART for operation, and enable the uDMA interface for both TX // and RX channels. // ROM_UARTEnable(UART0_BASE); ROM_UARTDMAEnable(UART0_BASE, UART_DMA_RX | UART_DMA_TX); // // This register write will set the UART to operate in loopback mode. Any // data sent on the TX output will be received on the RX input. // HWREG(UART0_BASE + UART_O_CTL) |= UART_CTL_LBE; // // Enable the UART peripheral interrupts. Note that no UART interrupts // were enabled, but the uDMA controller will cause an interrupt on the // UART interrupt signal when a uDMA transfer is complete. // ROM_IntEnable(INT_UART0); // // Put the attributes in a known state for the uDMA UART0RX channel. These // should already be disabled by default. // ROM_uDMAChannelAttributeDisable(UDMA_CHANNEL_UART0RX, UDMA_ATTR_ALTSELECT | UDMA_ATTR_USEBURST | UDMA_ATTR_HIGH_PRIORITY | UDMA_ATTR_REQMASK); // // Configure the control parameters for the primary control structure for // the UART RX channel. The primary contol structure is used for the "A" // part of the ping-pong receive. The transfer data size is 8 bits, the // source address does not increment since it will be reading from a // register. The destination address increment is byte 8-bit bytes. The // arbitration size is set to 4 to match the RX FIFO trigger threshold. // The uDMA controller will use a 4 byte burst transfer if possible. This // will be somewhat more effecient that single byte transfers. // ROM_uDMAChannelControlSet(UDMA_CHANNEL_UART0RX | UDMA_PRI_SELECT, UDMA_SIZE_8 | UDMA_SRC_INC_NONE | UDMA_DST_INC_8 | UDMA_ARB_4); // // Configure the control parameters for the alternate control structure for // the UART RX channel. The alternate contol structure is used for the "B" // part of the ping-pong receive. The configuration is identical to the // primary/A control structure. // ROM_uDMAChannelControlSet(UDMA_CHANNEL_UART0RX | UDMA_ALT_SELECT, UDMA_SIZE_8 | UDMA_SRC_INC_NONE | UDMA_DST_INC_8 | UDMA_ARB_4); // // Set up the transfer parameters for the UART RX primary control // structure. The mode is set to ping-pong, the transfer source is the // UART data register, and the destination is the receive "A" buffer. The // transfer size is set to match the size of the buffer. // ROM_uDMAChannelTransferSet(UDMA_CHANNEL_UART0RX | UDMA_PRI_SELECT, UDMA_MODE_PINGPONG, (void *)(UART0_BASE + UART_O_DR), g_ucRxBufA, sizeof(g_ucRxBufA)); // // Set up the transfer parameters for the UART RX alternate control // structure. The mode is set to ping-pong, the transfer source is the // UART data register, and the destination is the receive "B" buffer. The // transfer size is set to match the size of the buffer. // ROM_uDMAChannelTransferSet(UDMA_CHANNEL_UART0RX | UDMA_ALT_SELECT, UDMA_MODE_PINGPONG, (void *)(UART0_BASE + UART_O_DR), g_ucRxBufB, sizeof(g_ucRxBufB)); // // Put the attributes in a known state for the uDMA UART0TX channel. These // should already be disabled by default. // ROM_uDMAChannelAttributeDisable(UDMA_CHANNEL_UART0TX, UDMA_ATTR_ALTSELECT | UDMA_ATTR_HIGH_PRIORITY | UDMA_ATTR_REQMASK); // // Set the USEBURST attribute for the uDMA UART TX channel. This will // force the controller to always use a burst when transferring data from // the TX buffer to the UART. This is somewhat more effecient bus usage // than the default which allows single or burst transfers. // ROM_uDMAChannelAttributeEnable(UDMA_CHANNEL_UART0TX, UDMA_ATTR_USEBURST); // // Configure the control parameters for the UART TX. The uDMA UART TX // channel is used to transfer a block of data from a buffer to the UART. // The data size is 8 bits. The source address increment is 8-bit bytes // since the data is coming from a buffer. The destination increment is // none since the data is to be written to the UART data register. The // arbitration size is set to 4, which matches the UART TX FIFO trigger // threshold. // ROM_uDMAChannelControlSet(UDMA_CHANNEL_UART0TX | UDMA_PRI_SELECT, UDMA_SIZE_8 | UDMA_SRC_INC_8 | UDMA_DST_INC_NONE | UDMA_ARB_4); // // Set up the transfer parameters for the uDMA UART TX channel. This will // configure the transfer source and destination and the transfer size. // Basic mode is used because the peripheral is making the uDMA transfer // request. The source is the TX buffer and the destination is the UART // data register. // ROM_uDMAChannelTransferSet(UDMA_CHANNEL_UART0TX | UDMA_PRI_SELECT, UDMA_MODE_BASIC, g_ucTxBuf, (void *)(UART0_BASE + UART_O_DR), sizeof(g_ucTxBuf)); // // Now both the uDMA UART TX and RX channels are primed to start a // transfer. As soon as the channels are enabled, the peripheral will // issue a transfer request and the data transfers will begin. // ROM_uDMAChannelEnable(UDMA_CHANNEL_UART0RX); ROM_uDMAChannelEnable(UDMA_CHANNEL_UART0TX); }
//-----------------Program------------------------------------------// int main() { // specifies a system reset when using external reset pin SysCtlResetBehaviorSet(SYSCTL_ONRST_EXT_SYS); //------------------set sys clock to 120 MHZ ------------------------// g_ui32SysClock = MAP_SysCtlClockFreqSet((SYSCTL_XTAL_25MHZ| SYSCTL_OSC_MAIN | SYSCTL_USE_PLL | SYSCTL_CFG_VCO_480), g_freq); //-----------------Enable Periph-------------------------------------// ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOM); ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC); ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOJ); ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_UART3); ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_UART7); ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_TIMER0); ROM_TimerConfigure(TIMER0_BASE, TIMER_CFG_SPLIT_PAIR | TIMER_CFG_B_PERIODIC); ROM_TimerLoadSet(TIMER0_BASE, TIMER_B, g_freq/12000); ROM_TimerIntEnable(TIMER0_BASE, TIMER_TIMB_TIMEOUT); ROM_UARTIntEnable(UART3_BASE,UART_INT_RX); ROM_IntPrioritySet(INT_UART3, 0); ROM_IntPrioritySet(INT_TIMER0B,1); ROM_IntEnable(INT_UART3); ROM_IntEnable(INT_TIMER0B); //-------------Set Pins ---------------------------// ROM_GPIOPinTypeGPIOOutput(GPIO_PORTM_BASE, GPIO_PIN_4); ROM_GPIOPinTypeGPIOOutput(GPIO_PORTM_BASE, GPIO_PIN_5); ROM_GPIOPinTypeUART(GPIO_PORTC_BASE, GPIO_PIN_4 | GPIO_PIN_5); ROM_GPIOPinTypeUART(GPIO_PORTJ_BASE, GPIO_PIN_0 | GPIO_PIN_1); ROM_GPIOPinConfigure(GPIO_PC4_U7RX); ROM_GPIOPinConfigure(GPIO_PC5_U7TX); ROM_GPIOPinConfigure(GPIO_PJ0_U3RX); ROM_GPIOPinConfigure(GPIO_PJ1_U3TX); ROM_UARTConfigSetExpClk(UART3_BASE, g_ui32SysClock, 1000000, (UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE| UART_CONFIG_PAR_NONE)); ROM_UARTConfigSetExpClk(UART7_BASE, g_ui32SysClock, 1000000, (UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE | UART_CONFIG_PAR_NONE)); ROM_TimerEnable(TIMER0_BASE, TIMER_B); ROM_UARTEnable(UART3_BASE); ROM_UARTEnable(UART7_BASE); ROM_GPIOPinWrite(GPIO_PORTM_BASE, GPIO_PIN_4, GPIO_PIN_4); ROM_IntMasterEnable(); uart_parser_payload_write_pos = 0; uart_parser_state = RX_PREABLE0; char write_buf[2]; char* w_buf = write_buf; g_ui32Counter = 0; // ---------------------MAIN LOOP -----------------------------------// while(1) { DymxlReadDataBlocking(36,2,1); // need to turn timer off eventually state =!state; if(state) ROM_GPIOPinWrite(GPIO_PORTM_BASE, GPIO_PIN_4| GPIO_PIN_5, GPIO_PIN_4); else ROM_GPIOPinWrite(GPIO_PORTM_BASE, GPIO_PIN_4| GPIO_PIN_5, GPIO_PIN_5); } return 0; }
Fd_t uart_Open(char *ifName, unsigned long flags) { /* Configure CS (PE0) and nHIB (PE4) lines */ SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOE); ROM_GPIOPinTypeGPIOOutput(GPIO_PORTE_BASE, GPIO_PIN_4); ROM_GPIOPinWrite(GPIO_PORTE_BASE,GPIO_PIN_4, PIN_LOW); /* configuring UART interface */ SysCtlPeripheralEnable(SYSCTL_PERIPH_UART1); SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOB); SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC); GPIOPinConfigure(GPIO_PB0_U1RX); GPIOPinConfigure(GPIO_PB1_U1TX); ROM_GPIOPinTypeUART(GPIO_PORTB_BASE, GPIO_PIN_0 | GPIO_PIN_1); GPIOPinConfigure(GPIO_PC4_U1RTS); GPIOPinConfigure(GPIO_PC5_U1CTS); ROM_GPIOPinTypeUART(GPIO_PORTC_BASE, GPIO_PIN_4 | GPIO_PIN_5); GPIOPadConfigSet(GPIO_PORTB_BASE, GPIO_PIN_0, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD_WPU); /* configure with baud rate 115200 */ ROM_UARTConfigSetExpClk(UART1_BASE, ROM_SysCtlClockGet(), 115200, (UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE | UART_CONFIG_PAR_NONE)); UARTFlowControlSet(UART1_BASE, UART_FLOWCONTROL_TX | UART_FLOWCONTROL_RX); UARTFIFOLevelSet(UART1_BASE, UART_FIFO_TX1_8, UART_FIFO_RX1_8); ROM_UARTEnable(UART1_BASE); ROM_UARTFIFOEnable(UART1_BASE); ROM_IntEnable(INT_UART1); ROM_UARTIntEnable(UART1_BASE, UART_INT_RX); ROM_UARTIntDisable(UART1_BASE, UART_INT_TX | UART_INT_RT); /* configure host IRQ line */ GPIOPinTypeGPIOInput(GPIO_PORTB_BASE, GPIO_PIN_2); GPIOPadConfigSet(GPIO_PORTB_BASE, GPIO_PIN_2, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD_WPD); GPIOIntTypeSet(GPIO_PORTB_BASE, GPIO_PIN_2, GPIO_RISING_EDGE); GPIOIntClear(GPIO_PORTB_BASE,GPIO_PIN_2); GPIOIntDisable(GPIO_PORTB_BASE,GPIO_PIN_2); ROM_IntEnable(INT_GPIOB); ROM_IntMasterEnable(); IntIsMasked = FALSE; /* Enable WLAN interrupt */ CC3100_InterruptEnable(); /* 50 ms delay */ ROM_SysCtlDelay((ROM_SysCtlClockGet()/(3*1000))*50 ); return NONOS_RET_OK; }
void uart_poweron(uart_t uart) { ROM_UARTEnable(UART0_BASE); }
void uart_poweron(uart_t uart) { /*The base address of the chosen UART */ unsigned long ulBase = g_ulUARTBase[uart]; ROM_UARTEnable(ulBase); }
//***************************************************************************** // // A simple application demonstrating use of the boot loader, // //***************************************************************************** int main(void) { uint32_t ui32SysClock; tContext sContext; tRectangle sRect; // // Run from the PLL at 120 MHz. // ui32SysClock = MAP_SysCtlClockFreqSet((SYSCTL_XTAL_25MHZ | SYSCTL_OSC_MAIN | SYSCTL_USE_PLL | SYSCTL_CFG_VCO_480), 120000000); // // Configure the device pins. // PinoutSet(); // // Initialize the display driver. // Kentec320x240x16_SSD2119Init(ui32SysClock); // // Initialize the graphics context. // GrContextInit(&sContext, &g_sKentec320x240x16_SSD2119); // // Draw the application frame. // FrameDraw(&sContext, "boot-demo-uart"); // // Print instructions on the screen. // GrStringDrawCentered(&sContext, "Press the screen to start", -1, 160, 108, false); GrStringDrawCentered(&sContext, "the update process", -1, 160, 128, false); // // Initialize the touch screen driver. // TouchScreenInit(ui32SysClock); // // Set the touch screen event handler. // TouchScreenCallbackSet(TSHandler); // // Enable the UART that will be used for the firmware update. // ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0); // // Configure the UART for 115200, 8-N-1. // ROM_UARTConfigSetExpClk(UART0_BASE, ui32SysClock, 115200, (UART_CONFIG_PAR_NONE | UART_CONFIG_STOP_ONE | UART_CONFIG_WLEN_8)); // // Enable the UART operation. // ROM_UARTEnable(UART0_BASE); // // Wait until the screen has been pressed, indicating that the firwmare // update should begin. // while(!g_bFirmwareUpdate) { } // // Clear the screen. // sRect.i16XMin = 0; sRect.i16YMin = 0; sRect.i16XMax = 319; sRect.i16YMax = 239; GrContextForegroundSet(&sContext, ClrBlack); GrRectFill(&sContext, &sRect); // // Indicate that the firmware update is about to start. // GrContextForegroundSet(&sContext, ClrWhite); GrStringDrawCentered(&sContext, "Update process started...", -1, 160, 98, false); GrStringDrawCentered(&sContext, "Using UART0 with", -1, 160, 138, false); GrStringDrawCentered(&sContext, "115,200 baud, 8-N-1.", -1, 160, 158, false); // // Disable all processor interrupts. Instead of disabling them one at a // time, a direct write to NVIC is done to disable all peripheral // interrupts. // HWREG(NVIC_DIS0) = 0xffffffff; HWREG(NVIC_DIS1) = 0xffffffff; HWREG(NVIC_DIS2) = 0xffffffff; HWREG(NVIC_DIS3) = 0xffffffff; HWREG(NVIC_DIS4) = 0xffffffff; // // Call the ROM UART boot loader. // ROM_UpdateUART(); // // The boot loader should not return. In the off chance that it does, // enter a dead loop. // while(1) { } }