VOID
ODM_SetTimer(
IN PDM_ODM_T pDM_Odm,
IN PRT_TIMER pTimer,
IN u4Byte msDelay
)
{
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
mod_timer(pTimer, jiffies + RTL_MILISECONDS_TO_JIFFIES(msDelay));
#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
_set_timer(pTimer,msDelay ); //ms
#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN)
PADAPTER Adapter = pDM_Odm->Adapter;
PlatformSetTimer(Adapter, pTimer, msDelay);
#endif
}
VOID
ODM_InitializeTimer(
IN PDM_ODM_T pDM_Odm,
IN PRT_TIMER pTimer,
IN RT_TIMER_CALL_BACK CallBackFunc,
IN PVOID pContext,
IN const char* szID
)
{
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
init_timer(pTimer);
pTimer->function = CallBackFunc;
pTimer->data = (unsigned long)pDM_Odm;
mod_timer(pTimer, jiffies+RTL_MILISECONDS_TO_JIFFIES(10));
#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
PADAPTER Adapter = pDM_Odm->Adapter;
_init_timer(pTimer,Adapter->pnetdev,CallBackFunc,pDM_Odm);
#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN)
PADAPTER Adapter = pDM_Odm->Adapter;
PlatformInitializeTimer(Adapter, pTimer, CallBackFunc,pContext,szID);
#endif
}
void rtl8192cd_dfs_det_chk(struct rtl8192cd_priv *priv)
{
unsigned int regf98_value;
unsigned int reg918_value;
unsigned int reg91c_value;
unsigned int reg920_value;
unsigned int reg924_value;
unsigned int FA_count_cur=0, FA_count_inc=0;
unsigned int VHT_CRC_ok_cnt_cur=0, VHT_CRC_ok_cnt_inc=0;
unsigned int HT_CRC_ok_cnt_cur=0, HT_CRC_ok_cnt_inc=0;
unsigned int LEG_CRC_ok_cnt_cur=0, LEG_CRC_ok_cnt_inc=0;
unsigned int Total_CRC_OK_cnt_inc=0, FA_CRCOK_ratio=0;
unsigned char DFS_tri_short_pulse=0, DFS_tri_long_pulse=0, fa_mask_mid_th=0, fa_mask_lower_th=0;
unsigned char radar_type = 0; /* 0 for short, 1 for long */
unsigned int short_pulse_cnt_cur=0, short_pulse_cnt_inc=0;
unsigned int long_pulse_cnt_cur=0, long_pulse_cnt_inc=0;
unsigned int total_pulse_count_inc=0, max_sht_pusle_cnt_th=0;
unsigned int sum, k, fa_flag=0;
unsigned int st_L2H_new=0, st_L2H_tmp, index=0, fault_flag_det, fault_flag_psd;
int flags=0;
unsigned long throughput = 0;
int j;
int i, PSD_report_right[20], PSD_report_left[20];
int max_right, max_left;
int max_fa_in_hist=0, total_fa_in_hist=0, pre_post_now_acc_fa_in_hist=0;
if (priv->det_asoc_clear > 0) {
priv->det_asoc_clear--;
priv->pmib->dot11DFSEntry.DFS_detected = 0;
priv->FA_count_pre = 0;
priv->VHT_CRC_ok_cnt_pre = 0;
priv->HT_CRC_ok_cnt_pre = 0;
priv->LEG_CRC_ok_cnt_pre = 0;
priv->mask_idx = 0;
priv->mask_hist_checked = 0;
memset(priv->radar_det_mask_hist, 0, sizeof(priv->radar_det_mask_hist));
memset(priv->pulse_flag_hist, 0, sizeof(priv->pulse_flag_hist));
mod_timer(&priv->dfs_det_chk_timer, jiffies + RTL_MILISECONDS_TO_JIFFIES(priv->pshare->rf_ft_var.dfs_det_period*10));
return;
}
throughput = priv->ext_stats.tx_avarage+priv->ext_stats.rx_avarage;
#ifdef MBSSID
if (priv->pmib->miscEntry.vap_enable) {
for (j=0; j<RTL8192CD_NUM_VWLAN; j++) {
if (IS_DRV_OPEN(priv->pvap_priv[j])) {
throughput += priv->pvap_priv[j]->ext_stats.tx_avarage+priv->pvap_priv[j]->ext_stats.rx_avarage;
}
}
}
#endif
// Get FA count during past 100ms
FA_count_cur = PHY_QueryBBReg(priv, 0xf48, 0x0000ffff);
if (priv->FA_count_pre == 0)
FA_count_inc = 0;
else if (FA_count_cur >= priv->FA_count_pre)
FA_count_inc = FA_count_cur - priv->FA_count_pre;
else
FA_count_inc = FA_count_cur;
priv->FA_count_pre = FA_count_cur;
priv->fa_inc_hist[priv->mask_idx] = FA_count_inc;
for (i=0; i<5; i++) {
total_fa_in_hist = total_fa_in_hist + priv->fa_inc_hist[i];
if (priv->fa_inc_hist[i] > max_fa_in_hist)
max_fa_in_hist = priv->fa_inc_hist[i];
}
if (priv->mask_idx >= priv->pshare->rf_ft_var.dfs_det_flag_offset)
index = priv->mask_idx - priv->pshare->rf_ft_var.dfs_det_flag_offset;
else
index = priv->pshare->rf_ft_var.dfs_det_hist_len + priv->mask_idx - priv->pshare->rf_ft_var.dfs_det_flag_offset;
if (index == 0)
pre_post_now_acc_fa_in_hist = priv->fa_inc_hist[index] + priv->fa_inc_hist[index+1] + priv->fa_inc_hist[4];
else if (index == 4)
pre_post_now_acc_fa_in_hist = priv->fa_inc_hist[index] + priv->fa_inc_hist[0] + priv->fa_inc_hist[index-1];
else
pre_post_now_acc_fa_in_hist = priv->fa_inc_hist[index] + priv->fa_inc_hist[index+1] + priv->fa_inc_hist[index-1];
// Get VHT CRC32 ok count during past 100ms
VHT_CRC_ok_cnt_cur = PHY_QueryBBReg(priv, 0xf0c, 0x00003fff);
if (VHT_CRC_ok_cnt_cur >= priv->VHT_CRC_ok_cnt_pre)
VHT_CRC_ok_cnt_inc = VHT_CRC_ok_cnt_cur - priv->VHT_CRC_ok_cnt_pre;
else
VHT_CRC_ok_cnt_inc = VHT_CRC_ok_cnt_cur;
priv->VHT_CRC_ok_cnt_pre = VHT_CRC_ok_cnt_cur;
// Get HT CRC32 ok count during past 100ms
HT_CRC_ok_cnt_cur = PHY_QueryBBReg(priv, 0xf10, 0x00003fff);
if (HT_CRC_ok_cnt_cur >= priv->HT_CRC_ok_cnt_pre)
HT_CRC_ok_cnt_inc = HT_CRC_ok_cnt_cur - priv->HT_CRC_ok_cnt_pre;
else
HT_CRC_ok_cnt_inc = HT_CRC_ok_cnt_cur;
priv->HT_CRC_ok_cnt_pre = HT_CRC_ok_cnt_cur;
// Get Legacy CRC32 ok count during past 100ms
LEG_CRC_ok_cnt_cur = PHY_QueryBBReg(priv, 0xf14, 0x00003fff);
if (LEG_CRC_ok_cnt_cur >= priv->LEG_CRC_ok_cnt_pre)
LEG_CRC_ok_cnt_inc = LEG_CRC_ok_cnt_cur - priv->LEG_CRC_ok_cnt_pre;
else
LEG_CRC_ok_cnt_inc = LEG_CRC_ok_cnt_cur;
priv->LEG_CRC_ok_cnt_pre = LEG_CRC_ok_cnt_cur;
if ((VHT_CRC_ok_cnt_cur == 0x3fff) ||
(HT_CRC_ok_cnt_cur == 0x3fff) ||
(LEG_CRC_ok_cnt_cur == 0x3fff)) {
PHY_SetBBReg(priv, 0xb58, BIT(0), 1);
PHY_SetBBReg(priv, 0xb58, BIT(0), 0);
}
Total_CRC_OK_cnt_inc = VHT_CRC_ok_cnt_inc + HT_CRC_ok_cnt_inc + LEG_CRC_ok_cnt_inc;
// check if the FA occrus frequencly during 100ms
// FA_count_inc is divided by Total_CRC_OK_cnt_inc, which helps to distinguish normal trasmission from interference
if (Total_CRC_OK_cnt_inc > 0)
FA_CRCOK_ratio = FA_count_inc / Total_CRC_OK_cnt_inc;
//=====dynamic power threshold (DPT) ========
// Get short pulse count, need carefully handle the counter overflow
regf98_value = PHY_QueryBBReg(priv, 0xf98, 0xffffffff);
short_pulse_cnt_cur = regf98_value & 0x000000ff;
if (short_pulse_cnt_cur >= priv->short_pulse_cnt_pre)
short_pulse_cnt_inc = short_pulse_cnt_cur - priv->short_pulse_cnt_pre;
else
short_pulse_cnt_inc = short_pulse_cnt_cur;
priv->short_pulse_cnt_pre = short_pulse_cnt_cur;
// Get long pulse count, need carefully handle the counter overflow
long_pulse_cnt_cur = (regf98_value & 0x0000ff00) >> 8;
if (long_pulse_cnt_cur >= priv->long_pulse_cnt_pre)
long_pulse_cnt_inc = long_pulse_cnt_cur - priv->long_pulse_cnt_pre;
else
long_pulse_cnt_inc = long_pulse_cnt_cur;
priv->long_pulse_cnt_pre = long_pulse_cnt_cur;
total_pulse_count_inc = short_pulse_cnt_inc + long_pulse_cnt_inc;
if (priv->pshare->rf_ft_var.dfs_det_print) {
panic_printk("=====================================================================\n");
panic_printk("Total_CRC_OK_cnt_inc[%d] VHT_CRC_ok_cnt_inc[%d] HT_CRC_ok_cnt_inc[%d] LEG_CRC_ok_cnt_inc[%d] FA_count_inc[%d] FA_CRCOK_ratio[%d]\n",
Total_CRC_OK_cnt_inc, VHT_CRC_ok_cnt_inc, HT_CRC_ok_cnt_inc, LEG_CRC_ok_cnt_inc, FA_count_inc, FA_CRCOK_ratio);
panic_printk("Init_Gain[%x] 0x91c[%x] 0xf98[%08x] short_pulse_cnt_inc[%d] long_pulse_cnt_inc[%d]\n",
priv->ini_gain_cur, priv->st_L2H_cur, regf98_value, short_pulse_cnt_inc, long_pulse_cnt_inc);
panic_printk("Throughput: %luMbps\n", (throughput>>17));
reg918_value = PHY_QueryBBReg(priv, 0x918, 0xffffffff);
reg91c_value = PHY_QueryBBReg(priv, 0x91c, 0xffffffff);
reg920_value = PHY_QueryBBReg(priv, 0x920, 0xffffffff);
reg924_value = PHY_QueryBBReg(priv, 0x924, 0xffffffff);
printk("0x918[%08x] 0x91c[%08x] 0x920[%08x] 0x924[%08x]\n", reg918_value, reg91c_value, reg920_value, reg924_value);
}
